Add periph_uart_nonblocking. Since cc2538 has a transmit FIFO write
to the FIFO first and to a tsrb buffer only when the transmit FIFO
is full.
Rely on the FIFO TXIFLSEL condition to fill up FIFO as space becomes
available.
The bit access functions are not tied to Cortex-M CPUs, here they only
provide optimisations via bit-banding.
But the functions are generally useful - so move them to an arch independent
location.
This patch implements the real time clock module for the QN908X cpus.
This module is very straightforward with only the one notable drawback
that it doesn't have a match register like the CTIMER block to implement
the alarm function. Instead, this driver can only use the interrupt
generated ever 1 second to implement the alarm match comparison in
software.
The IRQ for each GPIO port needs to be enabled in the NVIC on top of
enabling the corresponding bit in the GPIO port.
This was not caught in tests before because I was testing with a larger
stack of commits (including UART and timers) which also had this fix.
Manually poking the GPIOs while using tests/periph_gpio now properly
fires the interrupts.
The QN908x CPU has several timer modules: one RTC (Real-Time Clock) that
can count from the 32kHz internal clock or 32.768 kHz external clock,
four CTIMER that use the APB clock and have four channels each and one
SCT timer with up to 10 channels running on the AHB clock.
This patch implements a timer driver for the CTIMER blocks only, which
is enough to make the xtimer module work. Future patches should improve
on this module to support using the RTC CNT2 32-bit free-running
counter unit and/or the SCT timer.
GPIO_BOTH gpio_flank_t; UART_PARTY_MARK and UART_PARTY_SPACE in
uart_parity_t; and UART_DATA_BITS_5 and UART_DATA_BITS_6
uart_data_bits_t enum values where missing from the periph_cpu.h header
since they are not supported by the CPU. This was causing some tests to
fail to compile, but only after adding the periph_timer module.
This patch adds those missing macros and makes the corresponding
functions fail when trying to use them.
A minor fix to the NWDT_TIME_LOWER_LIMIT value setting it to 1U to avoid
a -Werror=type-limits error in the tests/periph_wdt test. In theory 0
is a totally valid value although a bit useless since it will trigger
the WDT right away.
The QN908x has four FLEXCOMM interfaces that support a subset of UART,
SPI or I2C each one. This patch adds generic support for dealing with
the FLEXCOMM initialization and interrupts and adds a driver for
RX/TX support in UART.
With this patch is now possible to use a shell on the device over UART.
The NXP QN908x CPU family is a Cortex-M4F CPU with integrated USB,
Bluetooth Low Energy and in some variants NFC. This patch implements the
first steps for having support for this CPU.
While the QN908x can be considered the successor of similar chips from
NXP like the KW41Z when looking at the feature set, the internal
architecture, boot image format and CPU peripherals don't match those
in the Kinetis line. Therefore, this patch creates a new directory for
just the QN908x chip under cpu/qn908x.
The minimal set of peripherals are implemented in this patch to allow
the device to boot and enable a GPIO: the gpio and wdt peripheral
modules only.
The wdt driver is required to boot and disable the wdt. On reset, the
wdt is disabled by the chip, however the QN908x bootloader stored in
the internal ROM enables the wdt and sets a timer to reboot after 10
seconds, therefore it is needed to disable the wdt in RIOT OS soon
after booting. This patch sets it up such that when no periph_wdt module
is used the Watchdog is disabled, but if the periph_wdt is used it must
be configured (initialized) within the first 10 seconds.
Tests performed:
Defined a custom board for this CPU and compiled a simple application
that blinks some LEDs. Manually tested with periph_wdt and with
periph_wdt_cb as well.
In preparation for adding support for the QN908x cpus, this patch adds
a pristine copy of the vendor SDK files needed for initial support.
The only modification to these files is to add '#ifdef __cplusplus'
guards to all the header files, even if not needed or already
present as '#if defined(__cplusplus)', to make sure
./dist/tools/externc/check.sh check passes.
These files are located under vendor/ directories (both
cpu/qn908x/include/vendor/ and cpu/qn908x/vendor/) and are part of NXP's
SDK for the QN908x family available for download from:
https://mcuxpresso.nxp.com/en/builder
The files included in these vendor/ directories are released by NXP
under an Open Source license as described in each file, but only the
files used by the next patch are included here.
The basic nrf802154 driver lacks ACK handling and retransmissions,
which degrades it's usefulness.
The 802.15.4 Sub-MAC fixes all those issues.
Enable it by default for this driver to make it better behaved.
This commits adds a common type for the block writes to the flash of the
stm32. Depending on the family, the type has a different size. This
allows the removal of a number of ifdefs to track the differences
between families, simplifying the flashpage code
- Add `WORD_ALIGNED` attribute to potentially unaligned allocations
- Use intermediate cast to `uintptr_t` to silence false positives of
`-Wcast-align`
`flashpage_write_raw()` got renamed to `flashpage_write()`.
Now `sam0_flashpage_aux_write_raw()` is the only remaining 'raw'
function, even though it behaves just like `flashpage_write()`.
So let's also rename that for consistency.
Flash Customer Configuration Area (CCA) is never written when the
riotboot module is used. This required a riot application to have
been previously flashed. riotboot will completely ignore this
section, neither writing or erasing it.
Slot flashing is currenly only supported with Jlink.
Co-authored-by: Brenton Chetty <brent7984@gmail.com>
Note that Kconfig.models was not generated with gen_kconfig.py tool
due to lack of ProductsList.xlsx file for STM32MP1 family.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In STM32MP1 family, independant watchdogs (IWDG1 and IWDG2) are
dedicated to the MPU (Cortex-A7). Thus simply disable the feature
for STM32MP1 family.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
The stm32mp157c has the particularity to not having flash memory but
only SRAM.
Thus a part of SRAM must be considered as a ROM to flash the firmware
into.
In case of the stm32mp157c, the RETRAM (64kB) is used as ROM and the
4 banks of SRAM (384kB) are used as RAM.
However, as ROM_LEN, RAM_LEN, ROM_START_ADDRESS, RAM_START_ADDRESS and
ROM_OFFSET could be overloaded by user, set them with "?=" operator.
If the ROM_START_ADDRESS and the RAM_START_ADDRESS are not set at the
end of that file, it is a classic stm32 MCU with flash, thus set this
variables with common memory addresses for stm32 MCU family:
ROM_START_ADDR ?= 0x08000000
RAM_START_ADDR ?= 0x20000000
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In Engineering mode (BOOT0 off and BOOT2 on), only the Cortex-M4
core is running. It means that all clocks have to be setup
by the Cortex-M4 core.
In other modes, the clocks are setup by the Cortex-A7 and then should
not be setup by Cortex-M4.
stm32mp1_eng_mode pseudomodule have to be used in Engineering mode
to ensure clocks configuration with IS_USED(MODULE_STM32MP1_ENG_MODE)
macro.
This macro can also be used in periph_conf.h to define clock source
for each peripheral.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
STM32_PM_STOP and STM32_PM_STANDBY are always defined in periph_cpu.h,
Thus it is not needed to test them.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
According to stm32mp157 documentation:
* "The CStop mode is entered for MCU when the SLEEPDEEP bit in the Cortex®-M4 System Control
register is set." Thus set PM_STOP_CONFIG to 0.
* "The CStandby mode applies only to the MPU sub-system."
Set PM_STANDBY_CONFIG to (0) and do not enter standby mode for
stm32mp1.
As PM_STOP_CONFIG is already defined before for CPU_FAM_STM32WB, replace
it with CPU_FAM_STM32MP1.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
stm32mp1 is configuring gpio slightly differently that common stm32:
* port_num is computed differently, thus test MCU family to apply
the good calculation.
* Rising and falling edge state on interrupts. Do not test if falling
or rising edge, just launch the callback in all cases.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
Normally, CMSIS headers are retrieved as package from ST git repository
for each stm32.
However stm32mp1 family does not have a CMSIS headers repository but
have been included into RIOT source code in a previous commit.
For stm32mp1, CMSIS headers package must then not be retrieved and
vectors have to be generated from already in-source CMSIS headers.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
Include stm32mp1 vendors header. CORE_CM4 must be defined to include
Cortex-M4 core headers.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
stm32mp1 ordering informations are not the same than classical
single MCU.
And as stm32mp1 has no flash, just extract second part of model name
and pincount.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
The stm32mp1 family has no flash. The firmware is loaded directly in
RAM by stlink programmer or by Cortex-A7 bootloader/OS.
Thus bootloader is useless for this family, disable it.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
As stm32mp1 family accesses gpio pins with a different
offset than other stm32, create a specific macro.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
clk_conf is a useful tool to produce clock headers for new boards.
But it only supports STM32Fx families.
This commits add the definition of a new family: STM32MP1.
Only the STM32MP157 is supported for now.
First build clk_conf:
$ make -C cpu/stm32/dist/clk_conf/
Clock header can be generated with the following command once clk_conf is
built:
$ cpu/stm32/dist/clk_conf/clk_conf stm32mp157 208000000 24000000 1
This command line will produce a core clock of 208MHz with a 24MHz HSE
oscillator and will use LSE clock which corresponds to the STM32MP157C-DK2
board configuration.
The command will output the header to copy paste into the periph_conf.h of
the board:
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 209MHz */
#define CLOCK_CORECLOCK (208000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (24000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_MCU_DIV RCC_MCUDIVR_MCUDIV_1 /* max 209MHz */
#define CLOCK_MCU (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_APB1DIVR_APB1DIV_2 /* max 104MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_APB2DIVR_APB2DIV_2 /* max 104MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB3_DIV RCC_APB3DIVR_APB3DIV_2 /* max 104MHz */
#define CLOCK_APB3 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (2)
#define CLOCK_PLL_N (52)
#define CLOCK_PLL_P (3)
#define CLOCK_PLL_Q (13)
/** @} */
This result has been verified with STM32CubeMX, the official ST tool.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
APB1 bus clock is always enabled is not manageable by RCC register.
So avoid enabling it.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
* Setup i2c speed to I2C_SPEED_LOW by default
* enable i2c_write_regs() function.
* i2c frequency needs to be specified into board periph_conf.h
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In some CMSIS headers, "typedef enum" could be preceded by white
spaces. Thus consider them when parsing the line.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
b4f29035ce adapted the can_linux module to
the periph_can interface. This is a cleanup of some things that stayed
behind. Here the makefile is removed, the references to can_linux in the
dependency resolution and configuration Makefile are changed to the
standard periph_can, and the startup code is adapted.
Default values were wrong for WB when using HSE 32MHz as PLL input source
Default PLL input source was wrong when not using HSE and the board
provides an HSE
By using the RTC helper functions instead of POSIX mktime()/gmtime()
we can not only extend the RTC range beyond Y2038.
For tests/periph_rtc:
before:
text data bss dec hex filename
28028 248 2472 30748 781c stk3700/tests_periph_rtc.elf
after:
text data bss dec hex filename
19400 144 2424 21968 55d0 stk3700/tests_periph_rtc.elf
fixes#13277
irq_arch.h previously included cpu.h, which in term included the vendor header
files. Those were needed to get the GIE define (general interrupt enable bit).
However, the vendor files use fancy defines like `#define N (0x0004)` that
easily conflict with application code. Due to the widespread use of the IRQ API,
it is better to not include the vendor files in irq_arch.h.
This commit adds a local define for the GIE bit and uses this instead of
including cpu.h.
If no local port is specified for socket_zep to listen on, don't listen
on a local port at all instead of listening on a default port.
This does not work with multiple instances of socket_zep anyway.
The reception code hands RX DMA descriptors back to the DMA right after its
contents were copied into the network stack internal buffer. This increases
the odds that the DMA never runs out of DMA descriptors to fill, even under
high load. However, the loop fetching the Ethernet frame stops to iterate at the
end of the frame. If the DMA used one more descriptor to store the FCS, this
was not returned back to the DMA. This commit fixes it.
Some SAMD21 CPUs from the D series have an additional TCC3 and / or
an additional analog comperator.
Add those to `vectors.c`.
Also rename the i2s interrupt to the proper name used by other sam0
devices.
MCG_Lite is used in many KL parts and is a less advanced clock generator
than the full MCG used in the K series. This change lets the MCG_Lite
and MCG share the same user facing API, with some configuration
differences.
Expose the auto-negotiation feature of the Ethernet device via the
pseudo-module stm32_eth_auto. With this enabled, the static speed configuration
set in the boards periph_conf.h will only be used if the PHY lacks
auto-negotiation capabilities - which is unlikely to ever happen.
When enabling & disabling interrupts back-to-back pending interrupts
are not serviced on Cortex-M23/M33.
Flush the pipeline to give interrupts a chance of executing in `sched_arch_idle()`.
This fixes `no_idle_thread` on Cortex-M23.
The RISC-V toolchain in riotdocker has issues with picolibc and
will still include newlib headers.
This leads to conflicts like
```
In file included from [01m[Knanostubs.c:22[m[K:
[01m[K/usr/local/picolibc/riscv-none-embed/include/stdio.h:270:23:[m[K [01;31m[Kerror: [m[Kconflicting types for '[01m[K__FILE[m[K'
typedef struct __file [01;31m[K__FILE[m[K;
[01;31m[K^~~~~~[m[K
In file included from [01m[K/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/riscv-none-embed/include/reent.h:93[m[K,
from [01m[Knanostubs.c:20[m[K:
[01m[K/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/riscv-none-embed/include/sys/reent.h:287:26:[m[K [01;36m[Knote: [m[Kprevious declaration of '[01m[K__FILE[m[K' was here
typedef struct __sFILE [01;36m[K__FILE[m[K;
[01;36m[K^~~~~~[m[K
```
The problem does not occur when installing both the toolchain and picolibc
directly from the Debian / Ubuntu repositories, but CI uses an older Ubuntu
version that does not have those packages yet, so it builds them manually.
Blacklist RISC-V until CI has been updated.
> Fixes a typo on XOSC selection bitfield that would
make the CPU crash when changing it.
> Sets the other fields to their default values.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
Previously, only an link-up event was triggered, not an link down event. And
additionally, once the link-up event was sent, the link status was no longer
monitored. As a result, once a link-up was sent, no further link event were
triggered.
The methods to read from / write to MII registers had an address argument to
allow specifying the PHY to communicate with. However, only a single PHY is
available on all boards supported and the driver is not able to operate with
multiple PHYs anyway - thus, drop this parameter for ease of use.
This fixes a bug in the _get_link_status() function, which used hard coded the
address 0; which might not be correct for all boards.
read_csr() returns an unsigned long, not a uint32_t. This causes a
-Wformat warning to be emitted when compiling with clang. This commit
fixes the warning by changing the format string.
This requires -nostartfiles to be only passed to the linker, not the
compiler, as it is a linker flag and passing it to the compiler causes a
clang warning to be emitted.
Additionally, clang does not seem to support `-mcmodel=medlow` and
`-msmall-data-limit=8` but these options do not seem strictly necessary
to me anyhow thus they are deactivated conditionally when using clang.
The link status was previously not returned via the value parameter, as required
by the netdev_driver_t API. As a result, e.g. the `ifconfig` shell command
showed garbage.
It turns out hooking up an unused peripheral to a disabled GCLK
leads to surprising power savings.
Name the GCLK to be more explicit (and since not all members of
the extended samd2x family have a GCLK7).
Turns out we can just use a non-existing GCLK ID for this, this
even saves us a real GCLK that we can use for something else.
Also make sure to disable *all* peripherals by using
`GCLK_CLKCTRL_ID_Msk` instead of relying on a magic value.
Looks like we previously missed some, since this leads to some
additional power savings:
master: 4.22 mA
this patch: 4.09 mA
>Now `ROM_LEN` is the "real" length, 352K and 128K respectively
and the CCFG position is determined by subtracting it's size
from `_rom_length` symbol.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
The PWM decodeer, in LOAD=Single mode, loads data in groups of 4
half-words. Previously, if any channel was not connected to a pin (a
connection that's immaterial to the loader), a smaller number would be
given resulting in the decoder not loading anything at all.
See-Also: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf#page=256
Once PWM is running, the active PWM module overrides the PIN_CNF state;
only when PWM is stopped the pin returns into its PIN_CNF state (which,
then, the board may set to whatever idle means there).
(Moreover, the code there only worked for P0 registers, not eg. the
P1.09 of the nrf52840dongle's RGB LED).
Native CAN device was not properly ported to periph_can interface.
This commit fixes this by renaming all needed structures and files so
auto_init_can can initialize the native device. FEATURES_PROVIDED is
also updated for native.
- Enforced that ISR_STACKSIZE is indeed a multiple of 4
- With this enforced, every cast that triggers a -Wcast-align warning is now
a false positives, so those were silenced by (intermediately) casting to
`uintptr_t`.
This didn't change binaries for me. Either the linker script already took care
of it through the section names of the stacks, or I just was lucky. If I was
just luck, this fixes a bug. If not, it makes the hidden alignment explicit in
the C code, so that code review is easier.
Verified that each warning generated by -Wcast-align is indeed a false positive
and used an (intermediate) cast to `uintptr_t` to silence the warnings.
This is an implementation of the ESP32 SoftAP mode using the
`esp_wifi_ap` pseudomodule.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
> Allows flahsing CCFG configuration using Kconfig,
formely "make menuconfig".
> Supports cc26x0, cc26x2_cc13x2.
> Can be used to enable bootloader backdoor, to use
cc2538-bsl flashing script.
> Not all options are in Kconfig, most important ones,
others can be added in further commits.
> On cc13xx targets the VDDR high option can be enabled
using Kconfig.
> With this, RIOT can flash blank chips and the firmware
will run just fine.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
This add a custom ldscript for cc26xx_cc13xx CPUs,
which allows linking CCFG configuration, usage of GPRAM,
etc.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
The RTC on the fe310 is emulated using the RTT.
This only works if the RTT frequency is 1 Hz, so default to that
value in case `periph_rtc` is selected.
Use RTC helper functions instead of libc functions.
This gives us y2038 safety by the extended epoch and saves
a good chunk of memory:
picolibc mktime():
text data bss dec hex filename
15048 520 2504 18072 4698 tests/periph_rtc/bin/hifive1/tests_periph_rtc.elf
rtc_mktime():
text data bss dec hex filename
7632 40 2452 10124 278c tests/periph_rtc/bin/hifive1/tests_periph_rtc.elf
This modifies the cortex-m thread specifics to allow running the PendSV
interrupt continuously at lower priority and removes the priority
modifications during the interrupt itself. Interrupts are disabled
during the scheduling itself, but enabled briefly after the sleep to
ensure that they are handled if activated during the scheduling or the
sleep.
On samd5x only the RTC can wake the CPU from Deep Sleep (pm modes 0 & 1).
The external interrupt controller is disabled, but we can use the tamper
detection of the RTC.
If an gpio interrupt is configured on one of the five tamper detect pins,
those can be used to wake the CPU from Deep Sleep / Hibernate.
The Cortex-m0 based ATSAM devices can use the Single-cycle I/O Port for
GPIO. This commit modifies the gpio_t type to use this port when
available. It is mapped back to the peripheral memory space for
configuration access. When it is not available, the _port_iobus() and
_port() functions behave identical, which is the case for the samd51.
RTT module may get stuck during the init process if the RTC was running from
a previous boot. Unsure we don't remove the peripheral clock during the CPU
init if RTC is active from a previous boot and add a workaround to disable
this module as it will be re-init at some point later by the auto_init module
or by the user's application.
Add `TARGET_ARCH_<ARCH>` for each architecture (e.g. `TARGET_ARCH_CORTEX` for
Cortex M) to allow users to overwrite the target triple for a specific arch
from ~/.profile or ~/.bashrc (or the like) without overwriting it for all others
as well.
Declare sched_active_thread and sched_active_pid locally in the ESP code for
now. Once the code is cleaned up to no longer tap into scheduler internals but
use the API instead, those can be dropped again.
Similar to the cortex-m common linker scripts, the RISC-V linker scripts
can be unified easily, requiring only the memory addresses and lengths.
This simplifies adding new RISC-V CPU's later
This changes the prefixes of the symbols generated from USEMODULE and
USEPKG variables. The changes are as follow:
KCONFIG_MODULE_ => KCONFIG_USEMODULE_
KCONFIG_PKG_ => KCONFIG_USEPKG_
MODULE_ => USEMODULE_
PKG_ => USEPKG_
Using the TER bit in the TX descriptors when only using a single descriptor for
sending triggered a hardware bug. Thus, stop using the TER bit and store the
currently active TX descriptor in RAM instead.
The Watchdog on the CC2538 only supports 4 intervals (2ms, 16ms, 250ms & 1s).
Since the watchdog timer API specifies a `max_time`, the interval equal or
below that time is selected.
E.g. for `max_time=125ms` the 16ms interval would be selected.
This is outside the tolerance of the `tests/periph_wdt` test.
Co-authored-by: Thomas Geithner <thomas.geithner@dai-labor.de>
The rv32imac supports the A (atomic) extensions containing
read-modify-store operations. This commit modifies the GPIO code to use
these for all bitwise operations. The atomic operations are emitted with
relaxed ordering as they do not require multiprocessor synchronization.
This decreases the duration of the gpio operations from 59 ns to 50 ns
per call. depending a bit on the type of operation.
This is a small optimization to the RISC-V trap handler. By splitting
the call to sched_run from the trap_handle call, loading the previous
thread ptr can be delayed until after it is determined that a schedule
run is required. This shaves of a few cycles during regular interrupts
that do not trigger the scheduler.
This commit reworks the trap entry to only save the callee-saved
registers when a context switch is required. the caller-saved registers
are always stored and restored to adhere to the RISC-V ABI. This saves
considerable cycles on interrupts.
Use RTC helper functions instead of libc functions.
This gives us y2038 safety by the extended epoch
and saves a good chunk of memory:
mktime():
text data bss dec hex filename
24756 232 2736 27724 6c4c testssperiph_rtc/bin/openlabs-kw41z-mini/tests_periph_rtc.elf
rtc_mktime():
text data bss dec hex filename
16348 132 2696 19176 4ae8 tests/periph_rtc/bin/openlabs-kw41z-mini/tests_periph_rtc.elf
The `_zep_params_setup()` function will modify the `argv` string passed to it.
This is a problem because that string is re-used on reboot.
The modified string is then later processed in `socket_zep_setup()`, so we have to keep
the memory around.
The `strdup()` fulfills all this and the memory is freed by `execve()` on reboot.
A proper solution would be to parse the strings in `_zep_params_setup()`.
While the hard fault handler prints the offending program counter, it
does not print information about the context triggering the hard fault.
This commit adds a line printing the thread ID and name that triggered
the hard fault. If the hard fault is triggered during an ISR, it only
prints that the hard fault happened during ISR context, not which ISR
triggered it.
The RISC-V timer should only be touched by periph/timer and must not be
initialized and enabled by the IRQ code. The current code can cause an
unhandled interrupt when the timer is not used and the mtime register
hits UINT64_MAX.
We can achieve greater accuracy for the relative timer_set()
if we don't use the generic implementation.
Use the same approach as used by atmega_common to trigger interrupts
for too small offsets.
tests/periph_timer_short_relative_set should now succeed for all intervals.
In most places, picolibc and newlib are the same, so use
the existing newlib code when compiling with picolibc.
Signed-off-by: Keith Packard <keithp@keithp.com>
Allocate and initialize a thread-local block for each thread at the
top of the stack.
Set the tls base when switching to a new thread.
Add tdata/tbss linker instructions to cortex_m and risc-v scripts.
Signed-off-by: Keith Packard <keithp@keithp.com>
---
v2:
Squash fixes
v3:
Replace tabs with spaces
v4:
Add tbss to fe310 linker script
Disable the newlib-nano stubs code when picolibc is in use
Signed-off-by: Keith Packard <keithp@keithp.com>
---
v2:
Squash fixes in
v3:
call stdio_init in _PICOLIBC_ mode to initialize uart
v3:
Remove call to stdio_init from nanostubs_init, always
call from cpu_init.
Picolibc makes atexit state per-thread instead of global, so we can't
register destructors with atexit in a non-thread context as we won't
have any TLS space initialized.
Signed-off-by: Keith Packard <keithp@keithp.com>
Support for picolibc as alternative libc implementation is added with
this commit. For now only cortex-m CPU's are supported.
Enable via PICOLIBC=1
---
v2:
squash fixes in
v3:
Remove picolibc integer printf/scanf stuff from sys/Makefile.include,
it gets set in makefiles/libc/picolibc.mk
fixup for dependency
The MPU on the cortex-m23 has some differences with the MPU on the older
cortex-m devices. It is not implemented in the cortex-m MPU driver. This
removes the available feature as it gives a false sense of security by
advertising the feature, but implementing it with noop's
This adds a placeholder define for when the DMA peripheral available on
the MCU doesn't support channel/trigger filtering. This is the case on
the stm32f1 and stm32f3 family.
The stm32_eth driver was build on top of the internal API periph_eth, which
was unused anywhere. (Additionally, with two obscure exceptions, no functions
where declared in headers, making them pretty hard to use anyway.)
The separation of the driver into two layers incurs overhead, but does not
result in cleaner structure or reuse of code. Thus, this artificial separation
was dropped.
The Ethernet DMA is capable of collecting a frame from multiple chunks, just
like the send function of the netdev interface passes. The send function was
rewritten to just set up the Ethernet DMA up to collect the outgoing frame
while sending. As a result, the send function blocks until the frame is
sent to keep control over the buffers.
This frees 6 KiB of RAM previously used for TX buffers.
1. Move buffer configuration from boards to cpu/stm32
2. Allow overwriting buffer configuration
- If the default configuration ever needs touching, this will be due to a
use case and should be done by the application rather than the board
3. Reduce default RX buffer size
- Now that handling of frames split up into multiple DMA descriptors works,
we can make use of this
Note: With the significantly smaller RX buffers the driver will now perform
much worse when receiving data at maximum throughput. But as long as frames
are small (which is to be expected for IoT or boarder gateway scenarios) the
performance should not be affected.
If any incoming frame is bigger than a single DMA buffer, the Ethernet DMA will
split the content and use multiple DMA buffers instead. But only the DMA
descriptor of the last Ethernet frame segment will contain the frame length.
Previously, the frame length calculation, reassembly of the frame, and the
freeing of DMA descriptors was completely broken and only worked in case the
received frame was small enough to fit into one DMA buffer. This is now fixed,
so that smaller DMA buffers can safely be used now.
Additionally the interface was simplified: Previously two receive flavors were
implemented, with only one ever being used. None of those function was
public due to missing declarations in headers. The unused interface was
dropped and the remaining was streamlined to better fit the use case.
Either nRF52810 should define SPIM_COUNT 2 or nRF52805 should
define SPIM_COUNT 1.
But as it nRF52805 defines SPIM_COUNT 2 and nRF52810 defines SPIM_COUNT 1
even though both have a single SPI and a single, separate TWI peripheral.
Re-define SPIM_COUNT to 2 on nRF52810 as this is the easiest solution.
