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Merge pull request #14836 from aabadie/pr/cpu/stm32g4_full_speed

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cpu/stm32g4: add transition phase when raising +80MHz clock
This commit is contained in:
Alexandre Abadie 2020-08-25 10:02:13 +02:00 committed by GitHub
commit a7f9b4d793
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2 changed files with 15 additions and 6 deletions
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7
boards/common/stm32/include/g4/cfg_clock_default.h
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@ -48,15 +48,10 @@ extern "C" {
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif CLOCK_USE_PLL
/* The following parameters configure a 80MHz system clock with HSE as input clock */
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (40)
#define CLOCK_PLL_R (2)
/* Use the following to reach 170MHz
/* The following parameters configure a 170MHz system clock with HSE as input clock */
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (85)
#define CLOCK_PLL_R (2)
*/
#if CLOCK_HSE
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */

14
cpu/stm32/stmclk/stmclk_gx.c
View File

@ -155,9 +155,23 @@ void stmclk_init_sysclk(void)
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
#if CLOCK_AHB > MHZ(80)
/* Divide HCLK by before enabling the PLL */
RCC->CFGR |= RCC_CFGR_HPRE_DIV2;
#endif
/* now that the PLL is running, we use it as system clock */
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
#if CLOCK_AHB > MHZ(80)
/* Wait 1us before switching back to full speed */
/* Use volatile to prevent the compiler from optimizing the loop */
volatile uint8_t count = CLOCK_CORECLOCK / MHZ(1);
while (count--) {}
RCC->CFGR &= ~RCC_CFGR_HPRE_DIV2;
#endif
#endif
stmclk_disable_hsi();