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cpu/stm32: add clock configuration for stm32mp1
Configure stm32mp1 Cortex-M4 MCU core clock according to board configuration. Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
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Gilles DOFFE
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d78e13e906
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8279e54272
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cpu/stm32/stmclk/stmclk_mp1.c
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cpu/stm32/stmclk/stmclk_mp1.c
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/*
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* Copyright (C) 2020 Savoir-faire Linux
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration for STM32MP1
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*
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* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
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*
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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/* PLL configuration */
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define PLL_SRC RCC_RCK3SELR_PLL3SRC_1
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#else
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#define PLL_SRC RCC_RCK3SELR_PLL3SRC_0
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#endif
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/* Compute the bitfields for the PLL configuration */
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#define PLL_P (((CONFIG_CLOCK_PLL_P / 2)) \
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<< RCC_PLL3CFGR2_DIVP_Pos)
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#define PLL_M ((CONFIG_CLOCK_PLL_M) \
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<< RCC_PLL3CFGR1_DIVM3_Pos)
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#define PLL_N ((CONFIG_CLOCK_PLL_N) \
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<< RCC_PLL3CFGR1_DIVN_Pos)
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#define PLL_Q ((CONFIG_CLOCK_PLL_Q) \
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<< RCC_PLL3CFGR2_DIVQ_Pos)
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#if defined(RCC_PLL3CFGR2_DIVR) && defined(CONFIG_CLOCK_PLL_R)
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#define PLL_R ((CONFIG_CLOCK_PLL_R) \
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<< RCC_PLL3CFGR2_DIVR_Pos)
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#else
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#define PLL_R (0)
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#endif
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/* Configure HLCK and PCLK prescalers */
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#if CONFIG_CLOCK_MCU_DIV == 1
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#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_0)
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#elif CONFIG_CLOCK_MCU_DIV == 2
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#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_1)
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#elif CONFIG_CLOCK_MCU_DIV == 4
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#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_2)
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#elif CONFIG_CLOCK_MCU_DIV == 8
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#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_3)
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#elif CONFIG_CLOCK_MCU_DIV == 16
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#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_4)
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#elif CONFIG_CLOCK_MCU_DIV == 32
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#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_5)
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#elif CONFIG_CLOCK_MCU_DIV == 64
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#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_6)
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#elif CONFIG_CLOCK_MCU_DIV == 128
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#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_7)
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#elif CONFIG_CLOCK_MCU_DIV == 256
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#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_8)
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#elif CONFIG_CLOCK_MCU_DIV == 512
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#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_9)
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#else
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#error "Invalid MCU prescaler value (only 1, 2, 4, 8, 16, 32, 64, 128, 256 \
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and 512 allowed)"
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#endif
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_0)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_1)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_2)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_3)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_4)
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#else
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#error "Invalid APB1 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
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#endif
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#if CONFIG_CLOCK_APB2_DIV == 1
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#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_0)
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#elif CONFIG_CLOCK_APB2_DIV == 2
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#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_1)
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#elif CONFIG_CLOCK_APB2_DIV == 4
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#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_2)
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#elif CONFIG_CLOCK_APB2_DIV == 8
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#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_3)
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#elif CONFIG_CLOCK_APB2_DIV == 16
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#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_4)
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#else
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#error "Invalid APB2 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
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#endif
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#if CONFIG_CLOCK_APB3_DIV == 1
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#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_0)
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#elif CONFIG_CLOCK_APB3_DIV == 2
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#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_1)
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#elif CONFIG_CLOCK_APB3_DIV == 4
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#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_2)
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#elif CONFIG_CLOCK_APB3_DIV == 8
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#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_3)
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#elif CONFIG_CLOCK_APB3_DIV == 16
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#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_4)
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#else
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#error "Invalid APB3 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
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#endif
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/* Check whether PLL must be enabled:
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- When PLL is used as SYSCLK
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- When PLLQ is required
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_CLOCK_ENABLE_PLLQ)
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#define CONFIG_CLOCK_USE_PLL 1
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#else
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#define CONFIG_CLOCK_USE_PLL 0
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#endif
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/* Check whether HSE must be enabled:
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- When HSE is used as SYSCLK
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- When PLL is used as SYSCLK and the board provides HSE (since HSE will be
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used as PLL input clock)
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
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(IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_CLOCK_USE_PLL))
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#define CONFIG_CLOCK_USE_HSE 1
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#else
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#define CONFIG_CLOCK_USE_HSE 0
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#endif
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void stmclk_enable_hsi(void)
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{
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RCC->OCENSETR |= RCC_OCENSETR_HSION;
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while (!(RCC->OCRDYR & RCC_OCRDYR_HSIRDY)) {}
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}
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static void stmclk_enable_hse(void)
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{
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RCC->OCENSETR |= RCC_OCENSETR_HSEON;
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while (!(RCC->OCRDYR & RCC_OCRDYR_HSERDY)) {}
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}
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void stmclk_init_sysclk(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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RCC->MC_CIFR = 0;
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/* enable HSI clock for the duration of initialization */
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stmclk_enable_hsi();
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/* use HSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configured by the board */
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/* MCUDIV */
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RCC->MCUDIVR = CLOCK_MCU_DIV;
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while ((RCC->MCUDIVR & RCC_MCUDIVR_MCUDIVRDY)
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!= RCC_MCUDIVR_MCUDIVRDY) {}
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/* APB1DIV */
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RCC->APB1DIVR = CLOCK_APB1_DIV;
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while ((RCC->APB1DIVR & RCC_APB1DIVR_APB1DIVRDY)
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!= RCC_APB1DIVR_APB1DIVRDY) {}
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/* APB2DIV */
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RCC->APB2DIVR = CLOCK_APB2_DIV;
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while ((RCC->APB2DIVR & RCC_APB2DIVR_APB2DIVRDY)
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!= RCC_APB2DIVR_APB2DIVRDY) {}
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/* APB3DIV */
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RCC->APB3DIVR = CLOCK_APB3_DIV;
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while ((RCC->APB3DIVR & RCC_APB3DIVR_APB3DIVRDY)
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!= RCC_APB3DIVR_APB3DIVRDY) {}
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/* MCU clock source */
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RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_0; /* HSI */
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while ((RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY)
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!= RCC_MSSCKSELR_MCUSSRCRDY) {}
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/* disable all active clocks except HSI -> resets the clk configuration */
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RCC->OCENCLRR = ~(RCC_OCENSETR_HSION);
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/* if configured, we need to enable the HSE clock now */
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if (IS_ACTIVE(CONFIG_CLOCK_USE_HSE)) {
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stmclk_enable_hse();
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}
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if (IS_ACTIVE(CONFIG_CLOCK_USE_PLL)) {
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/* now we can safely configure the PLL */
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RCC->PLL3CFGR1 = (PLL_M | PLL_N);
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RCC->PLL3CFGR2 = (PLL_P | PLL_Q | PLL_R);
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RCC->RCK3SELR |= PLL_SRC;
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while (!(RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRCRDY)) {}
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/* and start the PLL */
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RCC->PLL3CR |= (RCC_PLL3CR_DIVPEN | RCC_PLL3CR_DIVQEN
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| RCC_PLL3CR_DIVREN | RCC_PLL3CR_PLLON);
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while (!(RCC->PLL3CR & RCC_PLL3CR_PLL3RDY)) {}
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}
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/* Configure SYSCLK */
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if (IS_ACTIVE(CONFIG_CLOCK_USE_PLL)) {
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RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_3; /* PLL3 */
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}
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else if (IS_ACTIVE(CONFIG_CLOCK_USE_HSE)) {
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RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_1; /* HSE */
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}
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else {
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RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_0; /* HSI by default */
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}
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/* Wait SYSCLK to be ready */
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while (!(RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY)) {}
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irq_restore(is);
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}
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