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cpu/samd5x: define CPU_COMMON_SAMD5X symbol and use it
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cc7f897cbc
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@ -625,7 +625,7 @@ static inline void sercom_clk_en(void *sercom)
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const uint8_t id = sercom_id(sercom);
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#if defined(CPU_COMMON_SAMD21)
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PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << id);
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#elif defined (CPU_FAM_SAMD5X)
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#elif defined (CPU_COMMON_SAMD5X)
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if (id < 2) {
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MCLK->APBAMASK.reg |= (1 << (id + 12));
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} else if (id < 4) {
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@ -655,7 +655,7 @@ static inline void sercom_clk_dis(void *sercom)
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const uint8_t id = sercom_id(sercom);
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#if defined(CPU_COMMON_SAMD21)
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PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << id);
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#elif defined (CPU_FAM_SAMD5X)
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#elif defined (CPU_COMMON_SAMD5X)
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if (id < 2) {
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MCLK->APBAMASK.reg &= ~(1 << (id + 12));
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} else if (id < 4) {
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@ -675,7 +675,7 @@ static inline void sercom_clk_dis(void *sercom)
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#endif
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}
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#ifdef CPU_FAM_SAMD5X
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#ifdef CPU_COMMON_SAMD5X
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static inline uint8_t _sercom_gclk_id_core(uint8_t sercom_id) {
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if (sercom_id < 2)
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return sercom_id + 7;
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@ -700,7 +700,7 @@ static inline void sercom_set_gen(void *sercom, uint8_t gclk)
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(gclk) |
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(SERCOM0_GCLK_ID_CORE + id));
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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#elif defined(CPU_FAM_SAMD5X)
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#elif defined(CPU_COMMON_SAMD5X)
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GCLK->PCHCTRL[_sercom_gclk_id_core(id)].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
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#else
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if (id < 5) {
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@ -25,7 +25,7 @@
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#include "periph/cpuid.h"
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#ifdef CPU_SAMD5X
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#ifdef CPU_COMMON_SAMD5X
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#define WORD0 (*(volatile uint32_t *)0x008061FC)
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#define WORD1 (*(volatile uint32_t *)0x00806010)
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#define WORD2 (*(volatile uint32_t *)0x00806014)
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@ -81,7 +81,7 @@ void dma_init(void)
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NVIC_EnableIRQ(DMAC_1_IRQn);
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NVIC_EnableIRQ(DMAC_2_IRQn);
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NVIC_EnableIRQ(DMAC_3_IRQn);
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#elif defined(CPU_FAM_SAMD5X)
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#elif defined(CPU_COMMON_SAMD5X)
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NVIC_EnableIRQ(DMAC_0_IRQn);
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NVIC_EnableIRQ(DMAC_1_IRQn);
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NVIC_EnableIRQ(DMAC_2_IRQn);
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@ -234,7 +234,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
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#ifdef CPU_COMMON_SAML1X
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/* EXTI[4..7] are binded to EIC_OTHER_IRQn */
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NVIC_EnableIRQ((exti > 3 )? EIC_OTHER_IRQn : (EIC_0_IRQn + exti));
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#elif defined(CPU_SAMD5X)
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#elif defined(CPU_COMMON_SAMD5X)
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NVIC_EnableIRQ(EIC_0_IRQn + exti);
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#else
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NVIC_EnableIRQ(EIC_IRQn);
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@ -360,7 +360,7 @@ void isr_eic(void)
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cortexm_isr_end();
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}
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#if defined(CPU_COMMON_SAML1X) || defined(CPU_SAMD5X)
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#if defined(CPU_COMMON_SAML1X) || defined(CPU_COMMON_SAMD5X)
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#define ISR_EICn(n) \
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void isr_eic ## n (void) \
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@ -374,7 +374,7 @@ ISR_EICn(0)
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ISR_EICn(1)
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ISR_EICn(2)
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ISR_EICn(3)
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#if defined(CPU_SAMD5X)
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#if defined(CPU_COMMON_SAMD5X)
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ISR_EICn(4)
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ISR_EICn(5)
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ISR_EICn(6)
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@ -389,8 +389,8 @@ ISR_EICn(13)
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ISR_EICn(14)
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ISR_EICn(15)
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#endif /* NUMOF_IRQS > 8 */
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#endif /* CPU_SAMD5X */
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#endif /* CPU_COMMON_SAML1X || CPU_SAMD5X */
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#endif /* CPU_COMMON_SAMD5X */
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#endif /* CPU_COMMON_SAML1X || CPU_COMMON_SAMD5X */
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#else /* MODULE_PERIPH_GPIO_IRQ */
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@ -45,7 +45,7 @@
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#define BUSSTATE_OWNER SERCOM_I2CM_STATUS_BUSSTATE(2)
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#define BUSSTATE_BUSY SERCOM_I2CM_STATUS_BUSSTATE(3)
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#if defined(CPU_COMMON_SAML21) || defined(CPU_COMMON_SAML1X) || defined(CPU_SAMD5X)
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#if defined(CPU_COMMON_SAML21) || defined(CPU_COMMON_SAML1X) || defined(CPU_COMMON_SAMD5X)
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#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER SERCOM_I2CM_CTRLA_MODE(5)
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#endif
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@ -32,7 +32,7 @@
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#if defined (CPU_COMMON_SAML1X) || defined (CPU_SAMD5X)
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#if defined (CPU_COMMON_SAML1X) || defined (CPU_COMMON_SAMD5X)
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#define UART_HAS_TX_ISR
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#endif
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@ -363,7 +363,7 @@ static void _usbdev_init(usbdev_t *dev)
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_block_pm();
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usbdev->usbdev.cb(&usbdev->usbdev, USBDEV_EVENT_HOST_CONNECT);
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/* Interrupt configuration */
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#ifdef CPU_FAM_SAMD5X
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#ifdef CPU_COMMON_SAMD5X
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NVIC_EnableIRQ(USB_0_IRQn);
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NVIC_EnableIRQ(USB_1_IRQn);
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NVIC_EnableIRQ(USB_2_IRQn);
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@ -5,6 +5,8 @@ ifneq (,$(filter same54%,$(CPU_MODEL)))
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CFLAGS += -DCPU_SAME54
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endif
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CFLAGS += -DCPU_COMMON_SAMD5X
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# Slot size is determined by "((total_flash_size - RIOTBOOT_LEN) / 2)".
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# If RIOTBOOT_LEN uses an uneven number of flashpages, the remainder of the
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# flash cannot be divided by two slots while staying FLASHPAGE_SIZE aligned.
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