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sam0: Add periph_gpio_fast_read feature where applicable
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@ -10,6 +10,7 @@ config CPU_FAM_SAMD21
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select CPU_COMMON_SAM0
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select CPU_CORE_CORTEX_M0PLUS
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select HAS_CPU_SAMD21
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select HAS_PERIPH_GPIO_FAST_READ
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select HAS_PUF_SRAM
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## CPU Models
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@ -2,5 +2,6 @@ CPU_CORE = cortex-m0plus
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CPU_FAM = samd21
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FEATURES_PROVIDED += puf_sram
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FEATURES_PROVIDED += periph_gpio_fast_read
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-include $(RIOTCPU)/sam0_common/Makefile.features
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@ -11,6 +11,7 @@ config CPU_COMMON_SAML1X
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select CPU_CORE_CORTEX_M23
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select HAS_CORTEXM_MPU
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select HAS_CPU_SAML1X
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select HAS_PERIPH_GPIO_FAST_READ
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select HAS_PERIPH_HWRNG
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config CPU_FAM_SAML10
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@ -10,5 +10,6 @@ endif
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += periph_gpio_fast_read
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include $(RIOTCPU)/sam0_common/Makefile.features
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@ -11,6 +11,7 @@ config CPU_FAM_SAML21
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select CPU_CORE_CORTEX_M0PLUS
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select HAS_BACKUP_RAM
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select HAS_CPU_SAML21
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select HAS_PERIPH_GPIO_FAST_READ
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## CPU Models
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config CPU_MODEL_SAML21J18A
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@ -4,6 +4,8 @@ CPU_FAM = saml21
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# The SAMR30 line of MCUs does not contain a TRNG
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CPU_MODELS_WITHOUT_HWRNG += samr30%
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FEATURES_PROVIDED += periph_gpio_fast_read
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# Low Power SRAM is *not* retained during Backup Sleep.
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# It therefore does not fulfill the requirements of the 'backup_ram' interface.
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# It can still be used in normal and standby mode, but code that relies on it
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@ -143,6 +143,13 @@ config HAS_PERIPH_GPIO_IRQ
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Indicates that the GPIO peripheral supports external interrupts is
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present.
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config HAS_PERIPH_GPIO_FAST_READ
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bool
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help
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Indicates that the GPIO peripheral supports a mode in which pin read
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operations are faster, usually with a tradeoff against a different
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property.
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config HAS_PERIPH_HWRNG
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bool
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help
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