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Merge pull request #9012 from gebart/pr/frdm-kl43z

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frdm-kl43z: NXP Kinetis FRDM-KL43Z development board
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benpicco 2020-10-26 00:06:46 +01:00 committed by GitHub
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26 changed files with 9236 additions and 13 deletions
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19
boards/frdm-kl43z/Kconfig Normal file
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@ -0,0 +1,19 @@
# Copyright (c) 2020 Benjamin Valentin
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
config BOARD
default "frdm-kl43z" if BOARD_FRDM_KL43Z
config BOARD_FRDM_KL43Z
bool
default y
select CPU_MODEL_MKL43Z256VLH4
select HAS_PERIPH_ADC
select HAS_PERIPH_I2C
select HAS_PERIPH_RTC
select HAS_PERIPH_RTT
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART

3
boards/frdm-kl43z/Makefile Normal file
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@ -0,0 +1,3 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

6
boards/frdm-kl43z/Makefile.dep Normal file
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@ -0,0 +1,6 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
USEMODULE += saul_adc
USEMODULE += mag3110
USEMODULE += mma8x5x
endif

11
boards/frdm-kl43z/Makefile.features Normal file
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@ -0,0 +1,11 @@
# define the cpu used by the board
CPU = kinetis
CPU_MODEL = mkl43z256vlh4
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart

8
boards/frdm-kl43z/Makefile.include Normal file
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@ -0,0 +1,8 @@
# This board comes with OpenSDA configured with a P&E debugger application,
# which we do not have any support for. Update your OpenSDA firmware with
# the latest CMSIS-DAP firmware for your board from
# https://www.nxp.com/support/developer-resources/run-time-software/kinetis-developer-resources/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA
DEBUG_ADAPTER ?= dap
# Include default FRDM board config
include $(RIOTBOARD)/common/frdm/Makefile.include

34
boards/frdm-kl43z/board.c Normal file
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@ -0,0 +1,34 @@
/*
* Copyright (C) 2018 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_frdm-kl43z
* @{
*
* @file
* @brief Board specific implementations for the FRDM-KL43Z
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU core */
cpu_init();
/* initialize and turn off the on-board RGB-LED */
gpio_init(LED0_PIN, GPIO_OUT);
gpio_set(LED0_PIN);
gpio_init(LED1_PIN, GPIO_OUT);
gpio_set(LED1_PIN);
}

61
boards/frdm-kl43z/include/adc_params.h Normal file
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@ -0,0 +1,61 @@
/*
* Copyright (C) 2018 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_frdm-kl43z
* @{
*
* @file
* @brief Board specific configuration of direct mapped ADC
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef ADC_PARAMS_H
#define ADC_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ADC configuration
*/
static const saul_adc_params_t saul_adc_params[] =
{
{
.name = "A0",
.line = ADC_LINE(0),
.res = ADC_RES_16BIT,
},
{
.name = "A1",
.line = ADC_LINE(1),
.res = ADC_RES_16BIT,
},
{
.name = "A2",
.line = ADC_LINE(2),
.res = ADC_RES_16BIT,
},
{
.name = "A3",
.line = ADC_LINE(3),
.res = ADC_RES_16BIT,
},
};
#ifdef __cplusplus
}
#endif
#endif /* ADC_PARAMS_H */
/** @} */

108
boards/frdm-kl43z/include/board.h Normal file
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@ -0,0 +1,108 @@
/*
* Copyright (C) 2018 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup boards_frdm-kl43z NXP FRDM-KL43Z Board
* @ingroup boards
* @brief Support for the NXP FRDM-KL43Z
* @{
*
* @file
* @brief Board specific definitions for the FRDM-KL43Z
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef BOARD_H
#define BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @brief FOPT setting
*/
/* Disable ROM bootloader, launch user application from flash */
#define KINETIS_FOPT (0xff & ~(NV_FOPT_BOOTSRC_SEL_MASK | NV_FOPT_BOOTPIN_OPT_MASK))
/**
* @name LED pin definitions and handlers
* @{
*/
/* LEDs are named LED1, LED2 in the original board schematics, we remap the LEDs
* to 0-indexed: NXP LED1 -> RIOT LED0, NXP LED2 -> RIOT LED1 */
#define LED0_PIN GPIO_PIN(PORT_D, 5)
#define LED1_PIN GPIO_PIN(PORT_E, 31)
#define LED0_MASK (1 << 5)
#define LED1_MASK (1 << 31)
#define LED0_ON (GPIOD->PCOR = LED0_MASK)
#define LED0_OFF (GPIOD->PSOR = LED0_MASK)
#define LED0_TOGGLE (GPIOD->PTOR = LED0_MASK)
#define LED1_ON (GPIOE->PCOR = LED1_MASK)
#define LED1_OFF (GPIOE->PSOR = LED1_MASK)
#define LED1_TOGGLE (GPIOE->PTOR = LED1_MASK)
/** @} */
/**
* @name xtimer configuration
* @{
*/
#if KINETIS_XTIMER_SOURCE_PIT
/* PIT xtimer configuration */
#define XTIMER_DEV (TIMER_PIT_DEV(0))
#define XTIMER_CHAN (0)
/* Default xtimer settings should work on the PIT */
#else
/* LPTMR xtimer configuration */
#define XTIMER_DEV (TIMER_LPTMR_DEV(0))
#define XTIMER_CHAN (0)
/* LPTMR is 16 bits wide and runs at 32768 Hz (clocked by the RTC) */
#define XTIMER_WIDTH (16)
#define XTIMER_BACKOFF (5)
#define XTIMER_ISR_BACKOFF (5)
#define XTIMER_OVERHEAD (4)
#define XTIMER_HZ (32768ul)
#endif
/** @} */
/**
* @name MAG3110 3-axis magnetometer bus configuration
* @{
*/
#define MAG3110_PARAM_I2C I2C_DEV(0)
#define MAG3110_PARAM_ADDR 0x0E
/** @} */
/**
* @name MMA8451Q 3-axis accelerometer bus configuration
* @{
*/
#define MMA8X5X_PARAM_I2C I2C_DEV(0)
#define MMA8X5X_PARAM_ADDR 0x1D
#define MMA8X5X_PARAM_TYPE (MMA8X5X_TYPE_MMA8451)
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

58
boards/frdm-kl43z/include/gpio_params.h Normal file
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@ -0,0 +1,58 @@
/*
* Copyright (C) 2018 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_frdm-kl43z
* @{
*
* @file
* @brief Board specific configuration of direct mapped GPIOs
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief LED configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LED1(green)",
.pin = LED0_PIN,
.mode = GPIO_OUT,
.flags = SAUL_GPIO_INVERTED
},
{
.name = "LED2(red)",
.pin = LED1_PIN,
.mode = GPIO_OUT,
.flags = SAUL_GPIO_INVERTED
},
{
.name = "SW1",
.pin = GPIO_PIN(PORT_C, 3),
.mode = GPIO_IN_PU
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

177
boards/frdm-kl43z/include/periph_conf.h Normal file
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@ -0,0 +1,177 @@
/*
* Copyright (C) 2018 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_frdm-kl43z
* @{
*
* @file
* @name Peripheral MCU configuration for the FRDM-KL43Z
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @name Clock system configuration
* @{
*/
static const clock_config_t clock_config = {
/*
* This configuration results in the system running with the internal clock
* with the following clock frequencies:
* Core: 8 MHz
* Bus: 8 MHz
* Flash: 8 MHz
*/
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(0),
/* unsure if this RTC load cap configuration is correct */
.rtc_clc = RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK,
/* Use the 32 kHz system oscillator output as ERCLK32K. */
.osc32ksel = SIM_SOPT1_OSC32KSEL(0),
.clock_flags =
KINETIS_CLOCK_RTCOSC_EN |
KINETIS_CLOCK_USE_FAST_IRC |
KINETIS_CLOCK_MCGIRCLK_EN | /* Used for LPUART clocking */
KINETIS_CLOCK_MCGIRCLK_STOP_EN |
0,
/* Using LIRC8M mode by default */
.default_mode = KINETIS_MCG_MODE_LIRC8M,
/* The crystal connected to EXTAL0 is 32.768 kHz */
.erc_range = KINETIS_MCG_ERC_RANGE_LOW,
.osc_clc = 0, /* no load cap configuration, rtc_clc overrides this value on KL43Z */
.fcrdiv = MCG_SC_FCRDIV(0), /* LIRC_DIV1 divide by 1 => 8 MHz */
.lirc_div2 = MCG_MC_LIRC_DIV2(0), /* LIRC_DIV2 divide by 1 => 8 MHz */
};
#define CLOCK_CORECLOCK ( 8000000ul)
#define CLOCK_MCGIRCLK ( 8000000ul)
#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
/** @} */
/**
* @name Timer configuration
* @{
*/
#define PIT_NUMOF (1U)
#define PIT_CONFIG { \
{ \
.prescaler_ch = 0, \
.count_ch = 1, \
}, \
}
#define LPTMR_NUMOF (1U)
#define LPTMR_CONFIG { \
{ \
.dev = LPTMR0, \
.irqn = LPTMR0_IRQn, \
.src = 2, \
.base_freq = 32768u, \
}, \
}
#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
#define PIT_ISR_0 isr_pit1
#define LPTMR_ISR_0 isr_lptmr0
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = LPUART0,
.freq = CLOCK_MCGIRCLK,
.pin_rx = GPIO_PIN(PORT_A, 1),
.pin_tx = GPIO_PIN(PORT_A, 2),
.pcr_rx = PORT_PCR_MUX(2),
.pcr_tx = PORT_PCR_MUX(2),
.irqn = LPUART0_IRQn,
.scgc_addr = &SIM->SCGC5,
.scgc_bit = SIM_SCGC5_LPUART0_SHIFT,
.mode = UART_MODE_8N1,
.type = KINETIS_LPUART,
},
};
#define UART_NUMOF ARRAY_SIZE(uart_config)
#define LPUART_0_ISR isr_lpuart0
/* Use MCGIRCLK (internal reference 4 MHz clock) */
#define LPUART_0_SRC 3
/** @} */
/**
* @name ADC configuration
* @{
*/
static const adc_conf_t adc_config[] = {
/* dev, pin, channel */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8, .avg = ADC_AVG_MAX }, /* Arduino A0 */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9, .avg = ADC_AVG_MAX }, /* Arduino A1 */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 2), .chan = 15, .avg = ADC_AVG_MAX }, /* Arduino A2 */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 3), .chan = 4, .avg = ADC_AVG_MAX }, /* Arduino A3 */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 11, .avg = ADC_AVG_MAX }, /* Arduino A4 */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15, .avg = ADC_AVG_MAX }, /* Arduino A5 */
};
#define ADC_NUMOF ARRAY_SIZE(adc_config)
/*
* KL43Z ADC reference settings:
* 0: VREFH/VREFL external pin pair
* 1: VDDA/VSSA supply pins
* 2-3: reserved
*/
#define ADC_REF_SETTING 0
/** @} */
/**
* @name I2C configuration
* @{
*/
static const i2c_conf_t i2c_config[] = {
{
.i2c = I2C0,
.scl_pin = GPIO_PIN(PORT_E, 24),
.sda_pin = GPIO_PIN(PORT_E, 25),
.freq = CLOCK_CORECLOCK,
.speed = I2C_SPEED_FAST,
.irqn = I2C0_IRQn,
.scl_pcr = (PORT_PCR_MUX(5)),
.sda_pcr = (PORT_PCR_MUX(5)),
},
{
.i2c = I2C1,
.scl_pin = GPIO_PIN(PORT_E, 1),
.sda_pin = GPIO_PIN(PORT_E, 0),
.freq = CLOCK_CORECLOCK,
.speed = I2C_SPEED_FAST,
.irqn = I2C1_IRQn,
.scl_pcr = (PORT_PCR_MUX(6)),
.sda_pcr = (PORT_PCR_MUX(6)),
},
};
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
#define I2C_0_ISR isr_i2c0
#define I2C_1_ISR isr_i2c1
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

35
cpu/kinetis/Kconfig
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@ -24,6 +24,11 @@ config CPU_FAM_K
select HAS_PERIPH_FLASHPAGE_RAW
select HAS_PERIPH_MCG
config CPU_FAM_L
bool
select CPU_COMMON_KINETIS
select HAS_PERIPH_MCG_LITE
config CPU_FAM_W
bool
select CPU_COMMON_KINETIS
@ -44,6 +49,26 @@ config CPU_MODEL_MK22FN512VLH12
select CPU_FAM_K
select HAS_PERIPH_HWRNG
config CPU_MODEL_MKL43Z256VLH4
bool
select CPU_CORE_CORTEX_M0PLUS
select CPU_FAM_L
config CPU_MODEL_MKL43Z256VMP4
bool
select CPU_CORE_CORTEX_M0PLUS
select CPU_FAM_L
config CPU_MODEL_MKL43Z128VLH4
bool
select CPU_CORE_CORTEX_M0PLUS
select CPU_FAM_L
config CPU_MODEL_MKL43Z128VMP4
bool
select CPU_CORE_CORTEX_M0PLUS
select CPU_FAM_L
config CPU_MODEL_MK60DN512VLL10
bool
select CPU_CORE_CORTEX_M4
@ -101,6 +126,11 @@ config HAS_PERIPH_MCG
help
Indicates that the cpu uses the Kinetis Multipurpose Clock Generator.
config HAS_PERIPH_MCG_LITE
bool
help
Indicates that the cpu uses the lite version of the Kinetis Multipurpose Clock Generator.
config HAS_PERIPH_ICS
bool
help
@ -111,6 +141,7 @@ config HAS_PERIPH_ICS
config CPU_FAM
default "ea" if CPU_FAM_EA
default "k" if CPU_FAM_K
default "l" if CPU_FAM_L
default "w" if CPU_FAM_W
config CPU_MODEL
@ -123,6 +154,10 @@ config CPU_MODEL
default "mkw22d512vha5" if CPU_MODEL_MKW22D512VHA5
default "mkw41z256vht4" if CPU_MODEL_MKW41Z256VHT4
default "mkw41z512vht4" if CPU_MODEL_MKW41Z512VHT4
default "mkl43z256vlh4" if CPU_MODEL_MKL43Z256VLH4
default "mkl43z256vmp4" if CPU_MODEL_MKL43Z256VMP4
default "mkl43z128vlh4" if CPU_MODEL_MKL43Z128VLH4
default "mkl43z128vmp4" if CPU_MODEL_MKL43Z128VMP4
default "s9keaz128aclh" if CPU_MODEL_S9KEAZ128ACLH
config CPU

3
cpu/kinetis/Makefile.dep
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@ -10,11 +10,14 @@ endif
# and check FEATURES_USED instead.
FEATURES_OPTIONAL += periph_ics
FEATURES_OPTIONAL += periph_mcg
FEATURES_OPTIONAL += periph_mcg_lite
ifneq (,$(filter periph_ics,$(FEATURES_USED)))
USEMODULE += periph_ics
else ifneq (,$(filter periph_mcg,$(FEATURES_USED)))
USEMODULE += periph_mcg
else ifneq (,$(filter periph_mcg_lite,$(FEATURES_USED)))
USEMODULE += periph_mcg_lite
endif
USEMODULE += periph_wdog

4
cpu/kinetis/Makefile.features
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@ -3,6 +3,8 @@ FEATURES_PROVIDED += periph_pm
# TRNG driver is not implemented for mkw41z models
_KINETIS_CPU_MODELS_WITHOUT_HWRNG += mkw41z256vht4 mkw41z512vht4
# TRNG driver is not implemented for kl43z models
_KINETIS_CPU_MODELS_WITHOUT_HWRNG += mkl43z%
# No HWRNG in mk20d7 devices
_KINETIS_CPU_MODELS_WITHOUT_HWRNG += mk20dx256vlh7
@ -24,6 +26,8 @@ endif
ifeq (ea,$(CPU_FAM))
FEATURES_PROVIDED += periph_ics
else ifeq (l,$(CPU_FAM))
FEATURES_PROVIDED += periph_mcg_lite
else
FEATURES_PROVIDED += periph_mcg
endif

11
cpu/kinetis/include/cpu_conf_kinetis_l.h
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@ -21,9 +21,14 @@
#ifndef CPU_CONF_KINETIS_L_H
#define CPU_CONF_KINETIS_L_H
#if (KINETIS_FAMILY == 2)
#if (KINETIS_SUBFAMILY == 2)
/* Put your vendor includes here */
#if (KINETIS_FAMILY == 4)
#if (KINETIS_SUBFAMILY == 3)
#if defined(CPU_MODEL_MKL43Z128VLH4) || \
defined(CPU_MODEL_MKL43Z128VMP4) || \
defined(CPU_MODEL_MKL43Z256VLH4) || \
defined(CPU_MODEL_MKL43Z256VMP4)
#include "vendor/MKL43Z4.h"
#endif
#endif /* (KINETIS_SUBFAMILY == y) */
#endif /* (KINETIS_FAMILY == x) */

3
cpu/kinetis/include/mcg.h
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@ -7,7 +7,8 @@
* details.
*/
#ifdef MODULE_PERIPH_MCG /* please doxygen by hiding dangling references */
/* please doxygen by hiding dangling references */
#if defined(MODULE_PERIPH_MCG) || defined(MODULE_PERIPH_MCG_LITE)
/**
* @defgroup cpu_kinetis_mcg Kinetis MCG
* @ingroup cpu_kinetis

62
cpu/kinetis/include/periph_cpu.h
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@ -311,10 +311,17 @@ typedef enum {
#ifdef KINETIS_HAVE_MK_SPI
#define HAVE_SPI_MODE_T
typedef enum {
#if defined(SPI_CTAR_CPHA_MASK)
SPI_MODE_0 = 0, /**< CPOL=0, CPHA=0 */
SPI_MODE_1 = (SPI_CTAR_CPHA_MASK), /**< CPOL=0, CPHA=1 */
SPI_MODE_2 = (SPI_CTAR_CPOL_MASK), /**< CPOL=1, CPHA=0 */
SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK) /**< CPOL=1, CPHA=1 */
#elif defined(SPI_C1_CPHA_MASK)
SPI_MODE_0 = 0, /**< CPOL=0, CPHA=0 */
SPI_MODE_1 = (SPI_C1_CPHA_MASK), /**< CPOL=0, CPHA=1 */
SPI_MODE_2 = (SPI_C1_CPOL_MASK), /**< CPOL=1, CPHA=0 */
SPI_MODE_3 = (SPI_C1_CPOL_MASK | SPI_C1_CPHA_MASK) /**< CPOL=1, CPHA=1 */
#endif
} spi_mode_t;
/** @} */
#endif /* KINETIS_HAVE_MK_SPI */
@ -525,8 +532,8 @@ typedef struct {
uart_type_t type; /**< Hardware module type (KINETIS_UART or KINETIS_LPUART)*/
} uart_conf_t;
#if !defined(KINETIS_HAVE_PLL)
#if defined(MCG_C6_PLLS_MASK) || DOXYGEN
#if !defined(KINETIS_HAVE_PLL) && defined(MODULE_PERIPH_MCG) \
&& defined(MCG_C6_PLLS_MASK) || DOXYGEN
/**
* @brief Defined to 1 if the MCG in this Kinetis CPU has a PLL
*/
@ -534,7 +541,19 @@ typedef struct {
#else
#define KINETIS_HAVE_PLL 0
#endif
#endif /* !defined(KINETIS_HAVE_PLL) */
#ifdef MODULE_PERIPH_MCG_LITE
/**
* @brief Kinetis possible MCG modes
*/
typedef enum kinetis_mcg_mode {
KINETIS_MCG_MODE_LIRC8M = 0, /**< LIRC 8 MHz mode*/
KINETIS_MCG_MODE_HIRC = 1, /**< HIRC 48 MHz mode */
KINETIS_MCG_MODE_EXT = 2, /**< External clocking mode */
KINETIS_MCG_MODE_LIRC2M = 3, /**< LIRC 2 MHz mode */
KINETIS_MCG_MODE_NUMOF, /**< Number of possible modes */
} kinetis_mcg_mode_t;
#endif /* MODULE_PERIPH_MCG_LITE */
#ifdef MODULE_PERIPH_MCG
/**
@ -576,6 +595,9 @@ typedef enum {
KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK),
} kinetis_mcg_fll_t;
#endif /* MODULE_PERIPH_MCG */
#if defined(MODULE_PERIPH_MCG) || defined(MODULE_PERIPH_MCG_LITE)
/**
* @brief Kinetis FLL external reference clock range settings
*/
@ -618,6 +640,8 @@ typedef enum {
* @note This flag affects the clock frequency of the CPU when using the MCG
* in FBI, or BLPI clocking modes.
*
* @note This flag is ignored on MCG_Lite parts
*
* - If this flag is set, the fast internal reference clock (up to 4 MHz,
* depends on settings) will be routed to the MCGIRCLK internal clock signal.
* - If not set, the slow internal reference clock (32 kHz) will be routed to
@ -645,6 +669,17 @@ typedef enum {
* CPU STOP modes.
*/
KINETIS_CLOCK_MCGIRCLK_STOP_EN = (1 << 4),
/**
* @brief Enable MCGPCLK (HIRC) internal clock signal
*
* This flag corresponds to the HIRCEN bit in the MCG_MC register.
*
* This clock source is only available on MCG_Lite parts
*
* - If this flag is set, the MCG will provide MCGPCLK for use by other
* peripherals.
*/
KINETIS_CLOCK_MCGPCLK_EN = (1 << 5),
} kinetis_clock_flags_t;
/**
@ -716,6 +751,7 @@ typedef struct {
* @see CPU reference manual, OSC_CR[SCxP]
*/
uint8_t osc_clc;
#ifdef MODULE_PERIPH_MCG
/**
* @brief MCG external reference oscillator selection
*
@ -726,9 +762,12 @@ typedef struct {
* @see CPU reference manual, MCG_C7[OSCSEL]
*/
uint8_t oscsel;
#endif /* MODULE_PERIPH_MCG */
/**
* @brief Fast internal reference clock divider
*
* This field is also known as LIRC_DIV1 on MCG_Lite parts.
*
* The bits will be passed directly to the MCG_SC register without any
* transformation, use the MCG_SC_FCRDIV() macro to ensure the proper bit
* shift for the chosen setting.
@ -736,6 +775,20 @@ typedef struct {
* @see CPU reference manual, MCG_SC[FCRDIV]
*/
uint8_t fcrdiv;
#ifdef MODULE_PERIPH_MCG_LITE
/**
* @brief LIRC second clock divider
*
* The bits will be passed directly to the MCG_MC register without any
* transformation, use the MCG_MC_LIRC_DIV2() macro to ensure the proper bit
* shift for the chosen setting.
* This divider only affects the MCGIRCLK output, it does not affect the
* core frequency when running the MCU in a LIRC clocking mode.
*
* @see CPU reference manual, MCG_MC[LIRC_DIV2]
*/
uint8_t lirc_div2;
#else
/**
* @brief FLL ERC divider setting
*
@ -782,8 +835,9 @@ typedef struct {
*/
uint8_t pll_vdiv;
#endif /* KINETIS_HAVE_PLL */
} clock_config_t;
#endif /* MODULE_PERIPH_MCG */
} clock_config_t;
#endif /* MODULE_PERIPH_MCG || MODULE_PERIPH_MCG_LITE */
/**
* @brief CPU internal function for initializing PORTs
*

3
cpu/kinetis/include/vectors_kinetis.h
View File

@ -109,6 +109,7 @@ void isr_i2c0(void); /**< I2C0 interrupt handler */
void isr_i2c1(void); /**< I2C1 interrupt handler */
void isr_i2c2(void); /**< I2C2 interrupt handler */
void isr_i2c3(void); /**< I2C3 interrupt handler */
void isr_i2s0(void); /**< I2S0 interrupt handler */
void isr_i2s0_rx(void); /**< I2S0 receive interrupt handler */
void isr_i2s0_tx(void); /**< I2S0 transmit interrupt handler */
void isr_llwu(void); /**< Low leakage wakeup interrupt handler */
@ -134,6 +135,7 @@ void isr_portc(void); /**< Port C pin detect interrupt handler */
void isr_portd(void); /**< Port D pin detect interrupt handler */
void isr_porte(void); /**< Port E pin detect interrupt handler */
void isr_portb_portc(void); /**< Port B, C combined pin detect interrupt handler */
void isr_portc_portd(void); /**< Port C, D combined pin detect interrupt handler */
void isr_radio_0(void); /**< Radio transceiver INT0 interrupt handler */
void isr_radio_1(void); /**< Radio transceiver INT1 interrupt handler */
void isr_rng(void); /**< RNG interrupt handler */
@ -158,6 +160,7 @@ void isr_uart1_err(void); /**< UART1 error interrupt handler */
void isr_uart1_rx_tx(void); /**< UART1 receive/transmit interrupt handler */
void isr_uart2(void); /**< UART2 unified interrupt handler */
void isr_uart2_err(void); /**< UART2 error interrupt handler */
void isr_uart2_flexio(void); /**< UART2 or FlexIO interrupt handler */
void isr_uart2_rx_tx(void); /**< UART2 receive/transmit interrupt handler */
void isr_uart3(void); /**< UART3 unified interrupt handler */
void isr_uart3_err(void); /**< UART3 error interrupt handler */

8326
cpu/kinetis/include/vendor/MKL43Z4.h vendored Normal file
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File diff suppressed because it is too large Load Diff

3
cpu/kinetis/isr_kinetis.c
View File

@ -155,6 +155,7 @@ WEAK_DEFAULT void isr_i2c0(void);
WEAK_DEFAULT void isr_i2c1(void);
WEAK_DEFAULT void isr_i2c2(void);
WEAK_DEFAULT void isr_i2c3(void);
WEAK_DEFAULT void isr_i2s0(void);
WEAK_DEFAULT void isr_i2s0_rx(void);
WEAK_DEFAULT void isr_i2s0_tx(void);
WEAK_DEFAULT void isr_llwu(void);
@ -180,6 +181,7 @@ WEAK_DEFAULT void isr_portc(void);
WEAK_DEFAULT void isr_portd(void);
WEAK_DEFAULT void isr_porte(void);
WEAK_DEFAULT void isr_portb_portc(void);
WEAK_DEFAULT void isr_portc_portd(void);
WEAK_DEFAULT void isr_radio_0(void);
WEAK_DEFAULT void isr_radio_1(void);
WEAK_DEFAULT void isr_rng(void);
@ -204,6 +206,7 @@ WEAK_DEFAULT void isr_uart1_err(void);
WEAK_DEFAULT void isr_uart1_rx_tx(void);
WEAK_DEFAULT void isr_uart2(void);
WEAK_DEFAULT void isr_uart2_err(void);
WEAK_DEFAULT void isr_uart2_flexio(void);
WEAK_DEFAULT void isr_uart2_rx_tx(void);
WEAK_DEFAULT void isr_uart3(void);
WEAK_DEFAULT void isr_uart3_err(void);

21
cpu/kinetis/kinetis-info.mk
View File

@ -104,6 +104,27 @@ ifeq ($(KINETIS_SERIES),K)
# There seems to be a cap on SRAM_L at 64 kB across the whole K series
KINETIS_SRAM_L_SIZE = 64
endif
else ifeq ($(KINETIS_SERIES),L)
ifeq ($(KINETIS_FAMILY),8)
# KL81, KL82
KINETIS_RAMSIZE = 96
else ifeq ($(KINETIS_SUBFAMILY),7)
# KL17, KL27
ifeq ($(KINETIS_ROMSIZE),256)
KINETIS_RAMSIZE = 32
else
KINETIS_RAMSIZE = $(KINETIS_ROMSIZE)/4
endif
else ifeq ($(KINETIS_FAMILY)$(KINETIS_SUBFAMILY),28)
# KL28
KINETIS_RAMSIZE = 128
else ifeq ($(KINETIS_FAMILY)$(KINETIS_SUBFAMILY),03)
# KL03
KINETIS_RAMSIZE = 2
else
KINETIS_RAMSIZE = $(KINETIS_ROMSIZE)/8
endif
KINETIS_SRAM_L_SIZE = $(KINETIS_RAMSIZE)/4
else ifeq ($(KINETIS_SERIES),W)
KINETIS_RAMSIZE = $(KINETIS_ROMSIZE)/8
ifeq ($(KINETIS_CORE),D)

8
cpu/kinetis/periph/gpio.c
View File

@ -412,4 +412,12 @@ void isr_portb_portc(void)
cortexm_isr_end();
}
#endif
#if defined(PORTC_BASE) && defined(PORTD_BASE)
/* Combined ISR used in certain KL devices */
void isr_portc_portd(void)
{
irq_handler(PORTC, 2);
irq_handler(PORTD, 3);
}
#endif
#endif /* MODULE_PERIPH_GPIO_IRQ */

1
cpu/kinetis/periph/mcg.c
View File

@ -283,7 +283,6 @@ static void kinetis_mcg_set_fbe(void)
current_mode = KINETIS_MCG_MODE_FBE;
}
/**
* @brief Initialize the FLL Bypassed Low Power Internal Mode.
*

260
cpu/kinetis/periph/mcg_lite.c Normal file
View File

@ -0,0 +1,260 @@
/*
* Copyright (C) 2015 PHYTEC Messtechnik GmbH
* Copyright (C) 2017 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_kinetis
* @ingroup cpu_kinetis_mcg
* @{
*
* @file
* @brief Implementation of the Kinetis Multipurpose Clock Generator (Lite version)
*
* @author Johann Fischer <j.fischer@phytec.de>
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*
*/
#include <stdint.h>
#include "periph_conf.h"
#include "mcg.h"
#include "bit.h"
/* The CPU is in LIRC8M mode after hardware reset */
static kinetis_mcg_mode_t current_mode = KINETIS_MCG_MODE_LIRC8M;
/**
* @brief Enable Oscillator module
*/
static void kinetis_mcg_enable_osc(void)
{
/* Configure ERC range for the DCO input. */
MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | clock_config.erc_range;
#if defined(OSC0)
/* Kinetis CPU with OSC module */
/* Enable Oscillator */
if (clock_config.clock_flags & KINETIS_CLOCK_OSC0_EN) {
/* Configure oscillator */
OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK | clock_config.osc_clc;
bit_set8(&MCG->C2, MCG_C2_EREFS0_SHIFT);
/* wait for OSC initialization */
while ((MCG->S & MCG_S_OSCINIT0_MASK) == 0) {}
}
else {
bit_clear8(&MCG->C2, MCG_C2_EREFS0_SHIFT);
}
#elif defined(RSIM)
/* Kinetis CPU with a radio system integration module which can provide an
* oscillator output. */
/* The CPUs with RSIM (currently only KW41Z, KW31Z, KW21Z) ignore the EREFS0
* bit in MCG_C2 because they have no OSC module. These CPUs need to use the
* RF oscillator inside the RSIM module if an oscillator is needed. */
/* The external reference clock line on these CPUs is permanently connected
* to the RSIM clock output, thus the RSIM, instead of the MCG, controls the
* external clock source selection. */
if (clock_config.clock_flags & KINETIS_CLOCK_OSC0_EN) {
/* Disable RF oscillator bypass, if it was enabled before */
bit_clear32(&RSIM->RF_OSC_CTRL, RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT);
}
else {
/* Enable RF oscillator bypass, to use the EXTAL pin as external clock
* source without the oscillator circuit */
bit_set32(&RSIM->RF_OSC_CTRL, RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT);
}
/* Enable RF oscillator circuit */
/* Current setting is that the OSC only runs in RUN and WAIT modes, see ref.man. */
RSIM->CONTROL = (RSIM->CONTROL & ~RSIM_CONTROL_RF_OSC_EN_MASK) | RSIM_CONTROL_RF_OSC_EN(1);
/* Wait for oscillator ready signal */
while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {}
#endif /* defined OSC0/RSIM */
}
/**
* @brief Initialize the 32 kHz reference clock (ERCLK32K)
*
* This will enable the RTC oscillator if enabled in the configuration.
*/
static void kinetis_mcg_init_erclk32k(void)
{
/* Enable RTC oscillator if selected */
if (clock_config.clock_flags & KINETIS_CLOCK_RTCOSC_EN) {
RTC_CLKEN();
if (!(RTC->CR & RTC_CR_OSCE_MASK)) {
/* Only touch if it was previously not running. The RTC is not reset
* by software resets, only by power on reset */
RTC->CR = RTC_CR_OSCE_MASK | RTC_CR_SUP_MASK | clock_config.rtc_clc;
}
}
/* Select ERCLK32K source */
SIM->SOPT1 = (SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | clock_config.osc32ksel;
}
/**
* @brief Initialize the MCG internal reference clock (MCGIRCLK)
*
* This clock signal can be used for directly clocking certain peripherals, and
* can be chosen as the MCG output clock (MCGOUTCLK).
*/
static void kinetis_mcg_init_mcgirclk(void)
{
/* Configure internal reference clock */
/* On MCG_Lite, LIRC is divided first by LIRC_DIV1, controlled by
* MCG_SC[FCRDIV], then by LIRC_DIV2, controlled by MCG_MC[LIRC_DIV2] */
MCG->SC = (MCG->SC & ~MCG_SC_FCRDIV_MASK) | clock_config.fcrdiv;
MCG->MC = (MCG->MC & ~MCG_MC_LIRC_DIV2_MASK) | clock_config.lirc_div2;
/* on MCG_Lite, we control the IRCS flag via the mode selection (LIRC2M vs LIRC8M) */
/* Enable/disable MCGIRCLK */
/* MCGIRCLK can be used as an alternate clock source for certain modules */
if (clock_config.clock_flags & KINETIS_CLOCK_MCGIRCLK_EN) {
bit_set8(&MCG->C1, MCG_C1_IRCLKEN_SHIFT);
}
else {
bit_clear8(&MCG->C1, MCG_C1_IRCLKEN_SHIFT);
}
if (clock_config.clock_flags & KINETIS_CLOCK_MCGIRCLK_STOP_EN) {
/* Enable MCGIRCLK during STOP (but only when also IRCLKEN is set) */
bit_set8(&MCG->C1, MCG_C1_IREFSTEN_SHIFT);
}
else {
bit_clear8(&MCG->C1, MCG_C1_IREFSTEN_SHIFT);
}
}
/**
* @brief Initialize the MCG high speed peripheral clock (MCGPCLK)
*
* This clock signal can be used for directly clocking certain peripherals
*/
static void kinetis_mcg_init_mcgpclk(void)
{
if (clock_config.clock_flags & KINETIS_CLOCK_MCGPCLK_EN) {
bit_set8(&MCG->MC, MCG_MC_HIRCEN_SHIFT);
}
else {
bit_clear8(&MCG->MC, MCG_MC_HIRCEN_SHIFT);
}
}
/**
* @brief Initialize HIRC (48 MHz) mode.
*/
static void kinetis_mcg_set_hirc(void)
{
/* select HIRC mode */
MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | (MCG_C1_CLKS(0));
/* Wait until HIRC is selected */
while ((MCG->S & (MCG_S_CLKST_MASK)) != 0) {}
current_mode = KINETIS_MCG_MODE_HIRC;
}
/**
* @brief Initialize EXT (external clock) mode.
*/
static void kinetis_mcg_set_ext(void)
{
kinetis_mcg_enable_osc();
/* select EXT mode */
MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | (MCG_C1_CLKS(0));
/* Wait until HIRC is selected */
while ((MCG->S & (MCG_S_CLKST_MASK)) != 0) {}
current_mode = KINETIS_MCG_MODE_HIRC;
}
/**
* @brief Initialize LIRC mode.
*
* Use @p ircs to select between LIRC8M (8 MHz) and LIRC2M (2 MHz).
*
* @param[in] lirc8m set to 1 -> LIRC8M, 0 -> LIRC2M
*/
static void kinetis_mcg_set_lirc(unsigned lirc8m)
{
uint32_t clkdiv = SIM->CLKDIV1;
if ((lirc8m && (current_mode == KINETIS_MCG_MODE_LIRC8M)) ||
(!lirc8m && (current_mode == KINETIS_MCG_MODE_LIRC2M))) {
/* We can not switch directly between LIRC2M <-> LIRC8M, go via HIRC */
/* Set safe clock dividers so we don't run out of specs while switching */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3); /* divide clock by 4 => 12 MHz */
kinetis_mcg_set_hirc();
}
if (lirc8m) {
/* Select 8 MHz mode */
bit_set8(&MCG->C2, MCG_C2_IRCS_SHIFT);
current_mode = KINETIS_MCG_MODE_LIRC8M;
}
else {
/* Select 2 MHz mode */
bit_clear8(&MCG->C2, MCG_C2_IRCS_SHIFT);
current_mode = KINETIS_MCG_MODE_LIRC2M;
}
/* select LIRC as clock source */
MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | (MCG_C1_CLKS(1));
/* Wait until LIRC is selected */
while ((MCG->S & (MCG_S_CLKST_MASK)) != MCG_S_CLKST(1)) {}
/* Restore clock divider settings */
SIM->CLKDIV1 = clkdiv;
}
int kinetis_mcg_set_mode(kinetis_mcg_mode_t mode)
{
switch(mode) {
case KINETIS_MCG_MODE_LIRC8M:
kinetis_mcg_set_lirc(1);
break;
case KINETIS_MCG_MODE_HIRC:
kinetis_mcg_set_hirc();
break;
case KINETIS_MCG_MODE_EXT:
kinetis_mcg_set_ext();
break;
case KINETIS_MCG_MODE_LIRC2M:
kinetis_mcg_set_lirc(0);
break;
default:
return -1;
}
return 0;
}
void kinetis_mcg_init(void)
{
unsigned mask = irq_disable();
/* Set module clock dividers */
SIM->CLKDIV1 = clock_config.clkdiv1;
kinetis_mcg_init_mcgpclk();
kinetis_mcg_init_mcgirclk();
kinetis_mcg_init_erclk32k();
/* Switch to the selected MCG mode */
kinetis_mcg_set_mode(clock_config.default_mode);
irq_restore(mask);
}
/** @} */

22
cpu/kinetis/vectors.c
View File

@ -183,8 +183,14 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[SPI2_IRQn ] = isr_spi2, /* SPI2 Interrupt */
#endif
#ifdef I2S0
#ifdef I2S_TCR1_TFW_MASK
/* K parts */
[I2S0_Tx_IRQn ] = isr_i2s0_tx, /* I2S0 transmit interrupt */
[I2S0_Rx_IRQn ] = isr_i2s0_rx, /* I2S0 receive interrupt */
#else
/* KL parts */
[I2S0_IRQn ] = isr_i2s0, /* I2S0 interrupt */
#endif
#endif
#ifdef UART0
#ifdef KINETIS_SINGLE_UART_IRQ
@ -206,8 +212,11 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
#endif
#endif
#ifdef UART2
#ifdef KINETIS_SINGLE_UART_IRQ
[UART2_IRQn] = isr_uart2, /* UART2 interrupt */
#if defined(KINETIS_SINGLE_UART_IRQ)
[UART2_IRQn] = isr_uart2, /* UART2 interrupt */
#elif defined(FLEXIO_VERID_MAJOR_MASK)
/* KL parts with FlexIO uses combined IRQ */
[UART2_FLEXIO_IRQn] = isr_uart2_flexio, /* UART2 or FLEXIO */
#else
[UART2_RX_TX_IRQn] = isr_uart2_rx_tx, /* UART2 Receive/Transmit interrupt */
[UART2_ERR_IRQn ] = isr_uart2_err, /* UART2 Error interrupt */
@ -310,8 +319,11 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[DAC1_IRQn ] = isr_dac1, /* DAC1 interrupt */
#endif
#ifdef MCG
#ifndef MCG_MC_LIRC_DIV2_MASK
/* Only on full MCG, not MCG_Lite */
[MCG_IRQn ] = isr_mcg, /* MCG Interrupt */
#endif
#endif /* MCG_MC_LIRC_DIV2_MASK */
#endif /* MCG */
#ifdef LPTMR0
[LPTMR0_IRQn ] = isr_lptmr0, /* LPTimer interrupt */
#endif
@ -319,8 +331,10 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[PORTA_IRQn ] = isr_porta, /* Port A interrupt */
#endif
#ifdef KINETIS_CORE_Z
#if defined(PORTB) && defined(PORTC)
#if defined(PORTB) && defined(PORTC) && !defined(PORTD)
[PORTB_PORTC_IRQn] = isr_portb_portc, /* Port B, C combined interrupt */
#elif defined(PORTC) && defined(PORTD)
[PORTC_PORTD_IRQn] = isr_portc_portd, /* Port C, D combined interrupt */
#endif
#else
#ifdef PORTB

1
examples/lua_REPL/Makefile.ci
View File

@ -22,6 +22,7 @@ BOARD_INSUFFICIENT_MEMORY := \
feather-m0 \
feather-m0-wifi \
firefly \
frdm-kl43z \
hamilton \
i-nucleo-lrwan1 \
ikea-tradfri \

1
tests/unittests/Makefile.ci
View File

@ -28,6 +28,7 @@ BOARD_INSUFFICIENT_MEMORY := \
esp8266-olimex-mod \
esp8266-sparkfun-thing \
feather-m0 \
frdm-kl43z \
hamilton \
hifive1 \
hifive1b \