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frdm-kl43z: NXP Kinetis FRDM-KL43Z development board

Browse Source 
https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/freedom-development-platform-for-kinetis-kl43-kl33-kl27-kl17-and-kl13-mcus:FRDM-KL43Z
This commit is contained in:
Joakim Nohlgård 2018-04-24 18:51:06 +02:00 committed by Benjamin Valentin
parent dc84ccdfe0
commit f006938936
12 changed files with 487 additions and 0 deletions
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19
boards/frdm-kl43z/Kconfig Normal file
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# Copyright (c) 2020 Benjamin Valentin
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
config BOARD
default "frdm-kl43z" if BOARD_FRDM_KL43Z
config BOARD_FRDM_KL43Z
bool
default y
select CPU_MODEL_MKL43Z256VLH4
select HAS_PERIPH_ADC
select HAS_PERIPH_I2C
select HAS_PERIPH_RTC
select HAS_PERIPH_RTT
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART

3
boards/frdm-kl43z/Makefile Normal file
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MODULE = board
include $(RIOTBASE)/Makefile.base

6
boards/frdm-kl43z/Makefile.dep Normal file
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ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
USEMODULE += saul_adc
USEMODULE += mag3110
USEMODULE += mma8x5x
endif

11
boards/frdm-kl43z/Makefile.features Normal file
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# define the cpu used by the board
CPU = kinetis
CPU_MODEL = mkl43z256vlh4
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart

8
boards/frdm-kl43z/Makefile.include Normal file
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# This board comes with OpenSDA configured with a P&E debugger application,
# which we do not have any support for. Update your OpenSDA firmware with
# the latest CMSIS-DAP firmware for your board from
# https://www.nxp.com/support/developer-resources/run-time-software/kinetis-developer-resources/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA
DEBUG_ADAPTER ?= dap
# Include default FRDM board config
include $(RIOTBOARD)/common/frdm/Makefile.include

34
boards/frdm-kl43z/board.c Normal file
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/*
* Copyright (C) 2018 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_frdm-kl43z
* @{
*
* @file
* @brief Board specific implementations for the FRDM-KL43Z
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU core */
cpu_init();
/* initialize and turn off the on-board RGB-LED */
gpio_init(LED0_PIN, GPIO_OUT);
gpio_set(LED0_PIN);
gpio_init(LED1_PIN, GPIO_OUT);
gpio_set(LED1_PIN);
}

61
boards/frdm-kl43z/include/adc_params.h Normal file
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/*
* Copyright (C) 2018 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_frdm-kl43z
* @{
*
* @file
* @brief Board specific configuration of direct mapped ADC
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef ADC_PARAMS_H
#define ADC_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ADC configuration
*/
static const saul_adc_params_t saul_adc_params[] =
{
{
.name = "A0",
.line = ADC_LINE(0),
.res = ADC_RES_16BIT,
},
{
.name = "A1",
.line = ADC_LINE(1),
.res = ADC_RES_16BIT,
},
{
.name = "A2",
.line = ADC_LINE(2),
.res = ADC_RES_16BIT,
},
{
.name = "A3",
.line = ADC_LINE(3),
.res = ADC_RES_16BIT,
},
};
#ifdef __cplusplus
}
#endif
#endif /* ADC_PARAMS_H */
/** @} */

108
boards/frdm-kl43z/include/board.h Normal file
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/*
* Copyright (C) 2018 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup boards_frdm-kl43z NXP FRDM-KL43Z Board
* @ingroup boards
* @brief Support for the NXP FRDM-KL43Z
* @{
*
* @file
* @brief Board specific definitions for the FRDM-KL43Z
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef BOARD_H
#define BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @brief FOPT setting
*/
/* Disable ROM bootloader, launch user application from flash */
#define KINETIS_FOPT (0xff & ~(NV_FOPT_BOOTSRC_SEL_MASK | NV_FOPT_BOOTPIN_OPT_MASK))
/**
* @name LED pin definitions and handlers
* @{
*/
/* LEDs are named LED1, LED2 in the original board schematics, we remap the LEDs
* to 0-indexed: NXP LED1 -> RIOT LED0, NXP LED2 -> RIOT LED1 */
#define LED0_PIN GPIO_PIN(PORT_D, 5)
#define LED1_PIN GPIO_PIN(PORT_E, 31)
#define LED0_MASK (1 << 5)
#define LED1_MASK (1 << 31)
#define LED0_ON (GPIOD->PCOR = LED0_MASK)
#define LED0_OFF (GPIOD->PSOR = LED0_MASK)
#define LED0_TOGGLE (GPIOD->PTOR = LED0_MASK)
#define LED1_ON (GPIOE->PCOR = LED1_MASK)
#define LED1_OFF (GPIOE->PSOR = LED1_MASK)
#define LED1_TOGGLE (GPIOE->PTOR = LED1_MASK)
/** @} */
/**
* @name xtimer configuration
* @{
*/
#if KINETIS_XTIMER_SOURCE_PIT
/* PIT xtimer configuration */
#define XTIMER_DEV (TIMER_PIT_DEV(0))
#define XTIMER_CHAN (0)
/* Default xtimer settings should work on the PIT */
#else
/* LPTMR xtimer configuration */
#define XTIMER_DEV (TIMER_LPTMR_DEV(0))
#define XTIMER_CHAN (0)
/* LPTMR is 16 bits wide and runs at 32768 Hz (clocked by the RTC) */
#define XTIMER_WIDTH (16)
#define XTIMER_BACKOFF (5)
#define XTIMER_ISR_BACKOFF (5)
#define XTIMER_OVERHEAD (4)
#define XTIMER_HZ (32768ul)
#endif
/** @} */
/**
* @name MAG3110 3-axis magnetometer bus configuration
* @{
*/
#define MAG3110_PARAM_I2C I2C_DEV(0)
#define MAG3110_PARAM_ADDR 0x0E
/** @} */
/**
* @name MMA8451Q 3-axis accelerometer bus configuration
* @{
*/
#define MMA8X5X_PARAM_I2C I2C_DEV(0)
#define MMA8X5X_PARAM_ADDR 0x1D
#define MMA8X5X_PARAM_TYPE (MMA8X5X_TYPE_MMA8451)
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

58
boards/frdm-kl43z/include/gpio_params.h Normal file
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/*
* Copyright (C) 2018 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_frdm-kl43z
* @{
*
* @file
* @brief Board specific configuration of direct mapped GPIOs
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief LED configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LED1(green)",
.pin = LED0_PIN,
.mode = GPIO_OUT,
.flags = SAUL_GPIO_INVERTED
},
{
.name = "LED2(red)",
.pin = LED1_PIN,
.mode = GPIO_OUT,
.flags = SAUL_GPIO_INVERTED
},
{
.name = "SW1",
.pin = GPIO_PIN(PORT_C, 3),
.mode = GPIO_IN_PU
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

177
boards/frdm-kl43z/include/periph_conf.h Normal file
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/*
* Copyright (C) 2018 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_frdm-kl43z
* @{
*
* @file
* @name Peripheral MCU configuration for the FRDM-KL43Z
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @name Clock system configuration
* @{
*/
static const clock_config_t clock_config = {
/*
* This configuration results in the system running with the internal clock
* with the following clock frequencies:
* Core: 8 MHz
* Bus: 8 MHz
* Flash: 8 MHz
*/
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(0),
/* unsure if this RTC load cap configuration is correct */
.rtc_clc = RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK,
/* Use the 32 kHz system oscillator output as ERCLK32K. */
.osc32ksel = SIM_SOPT1_OSC32KSEL(0),
.clock_flags =
KINETIS_CLOCK_RTCOSC_EN |
KINETIS_CLOCK_USE_FAST_IRC |
KINETIS_CLOCK_MCGIRCLK_EN | /* Used for LPUART clocking */
KINETIS_CLOCK_MCGIRCLK_STOP_EN |
0,
/* Using LIRC8M mode by default */
.default_mode = KINETIS_MCG_MODE_LIRC8M,
/* The crystal connected to EXTAL0 is 32.768 kHz */
.erc_range = KINETIS_MCG_ERC_RANGE_LOW,
.osc_clc = 0, /* no load cap configuration, rtc_clc overrides this value on KL43Z */
.fcrdiv = MCG_SC_FCRDIV(0), /* LIRC_DIV1 divide by 1 => 8 MHz */
.lirc_div2 = MCG_MC_LIRC_DIV2(0), /* LIRC_DIV2 divide by 1 => 8 MHz */
};
#define CLOCK_CORECLOCK ( 8000000ul)
#define CLOCK_MCGIRCLK ( 8000000ul)
#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
/** @} */
/**
* @name Timer configuration
* @{
*/
#define PIT_NUMOF (1U)
#define PIT_CONFIG { \
{ \
.prescaler_ch = 0, \
.count_ch = 1, \
}, \
}
#define LPTMR_NUMOF (1U)
#define LPTMR_CONFIG { \
{ \
.dev = LPTMR0, \
.irqn = LPTMR0_IRQn, \
.src = 2, \
.base_freq = 32768u, \
}, \
}
#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
#define PIT_ISR_0 isr_pit1
#define LPTMR_ISR_0 isr_lptmr0
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = LPUART0,
.freq = CLOCK_MCGIRCLK,
.pin_rx = GPIO_PIN(PORT_A, 1),
.pin_tx = GPIO_PIN(PORT_A, 2),
.pcr_rx = PORT_PCR_MUX(2),
.pcr_tx = PORT_PCR_MUX(2),
.irqn = LPUART0_IRQn,
.scgc_addr = &SIM->SCGC5,
.scgc_bit = SIM_SCGC5_LPUART0_SHIFT,
.mode = UART_MODE_8N1,
.type = KINETIS_LPUART,
},
};
#define UART_NUMOF ARRAY_SIZE(uart_config)
#define LPUART_0_ISR isr_lpuart0
/* Use MCGIRCLK (internal reference 4 MHz clock) */
#define LPUART_0_SRC 3
/** @} */
/**
* @name ADC configuration
* @{
*/
static const adc_conf_t adc_config[] = {
/* dev, pin, channel */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8, .avg = ADC_AVG_MAX }, /* Arduino A0 */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9, .avg = ADC_AVG_MAX }, /* Arduino A1 */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 2), .chan = 15, .avg = ADC_AVG_MAX }, /* Arduino A2 */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 3), .chan = 4, .avg = ADC_AVG_MAX }, /* Arduino A3 */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 11, .avg = ADC_AVG_MAX }, /* Arduino A4 */
{ .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15, .avg = ADC_AVG_MAX }, /* Arduino A5 */
};
#define ADC_NUMOF ARRAY_SIZE(adc_config)
/*
* KL43Z ADC reference settings:
* 0: VREFH/VREFL external pin pair
* 1: VDDA/VSSA supply pins
* 2-3: reserved
*/
#define ADC_REF_SETTING 0
/** @} */
/**
* @name I2C configuration
* @{
*/
static const i2c_conf_t i2c_config[] = {
{
.i2c = I2C0,
.scl_pin = GPIO_PIN(PORT_E, 24),
.sda_pin = GPIO_PIN(PORT_E, 25),
.freq = CLOCK_CORECLOCK,
.speed = I2C_SPEED_FAST,
.irqn = I2C0_IRQn,
.scl_pcr = (PORT_PCR_MUX(5)),
.sda_pcr = (PORT_PCR_MUX(5)),
},
{
.i2c = I2C1,
.scl_pin = GPIO_PIN(PORT_E, 1),
.sda_pin = GPIO_PIN(PORT_E, 0),
.freq = CLOCK_CORECLOCK,
.speed = I2C_SPEED_FAST,
.irqn = I2C1_IRQn,
.scl_pcr = (PORT_PCR_MUX(6)),
.sda_pcr = (PORT_PCR_MUX(6)),
},
};
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
#define I2C_0_ISR isr_i2c0
#define I2C_1_ISR isr_i2c1
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

1
examples/lua_REPL/Makefile.ci
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@ -22,6 +22,7 @@ BOARD_INSUFFICIENT_MEMORY := \
feather-m0 \
feather-m0-wifi \
firefly \
frdm-kl43z \
hamilton \
i-nucleo-lrwan1 \
ikea-tradfri \

1
tests/unittests/Makefile.ci
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@ -28,6 +28,7 @@ BOARD_INSUFFICIENT_MEMORY := \
esp8266-olimex-mod \
esp8266-sparkfun-thing \
feather-m0 \
frdm-kl43z \
hamilton \
hifive1 \
hifive1b \