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cpu/stm32: setup power management for stm32mp1

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According to stm32mp157 documentation:
* "The CStop mode is entered for MCU when the SLEEPDEEP bit in the Cortex®-M4 System Control
   register is set." Thus set PM_STOP_CONFIG to 0.
* "The CStandby mode applies only to the MPU sub-system."
  Set PM_STANDBY_CONFIG to (0) and do not enter standby mode for
  stm32mp1.

As PM_STOP_CONFIG is already defined before for CPU_FAM_STM32WB, replace
it with CPU_FAM_STM32MP1.

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
This commit is contained in:
Gilles DOFFE 2020-08-03 00:43:59 +02:00
parent e9a6b448cf
commit 6bac94fb6d
1 changed files with 8 additions and 2 deletions
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10
cpu/stm32/periph/pm.c
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@ -53,7 +53,8 @@
#define PM_STOP_CONFIG (PWR_CR1_LPMS_0)
#elif defined(CPU_FAM_STM32F7)
#define PM_STOP_CONFIG (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS)
#elif defined(CPU_FAM_STM32WB)
#elif defined(CPU_FAM_STM32MP1)
#define PM_STOP_CONFIG (0)
#else
#define PM_STOP_CONFIG (PWR_CR_LPDS | PWR_CR_FPDS)
#endif
@ -74,6 +75,8 @@
#define PM_STANDBY_CONFIG (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
#elif defined(CPU_FAM_STM32F7)
#define PM_STANDBY_CONFIG (PWR_CR1_PDDS | PWR_CR1_CSBF)
#elif defined(CPU_FAM_STM32MP1)
#define PM_STANDBY_CONFIG (0)
#else
#define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF)
#endif
@ -92,6 +95,9 @@
#elif defined(CPU_FAM_STM32F7)
#define PWR_CR_REG PWR->CR1
#define PWR_WUP_REG PWR->CSR2
#elif defined(CPU_FAM_STM32MP1)
#define PWR_CR_REG PWR->CR1
#define PWR_WUP_REG PWR->MCUWKUPENR
#else
#define PWR_CR_REG PWR->CR
#define PWR_WUP_REG PWR->CSR
@ -102,7 +108,7 @@ void pm_set(unsigned mode)
int deep;
switch (mode) {
#ifdef STM32_PM_STANDBY
#if defined(STM32_PM_STANDBY) && !defined(CPU_FAM_STM32MP1)
case STM32_PM_STANDBY:
PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
PWR_CR_REG |= PM_STANDBY_CONFIG;