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cpu/samd21: define CPU_COMMON_SAMD21 symbol and use it

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This commit is contained in:
Benjamin Valentin 2020-08-21 12:06:42 +02:00
parent 582da9b233
commit e32b0783c4
8 changed files with 20 additions and 18 deletions
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6
cpu/sam0_common/include/periph_cpu_common.h
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@ -623,7 +623,7 @@ static inline uint8_t sercom_id(const void *sercom)
static inline void sercom_clk_en(void *sercom)
{
const uint8_t id = sercom_id(sercom);
#if defined(CPU_FAM_SAMD21)
#if defined(CPU_COMMON_SAMD21)
PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << id);
#elif defined (CPU_FAM_SAMD5X)
if (id < 2) {
@ -653,7 +653,7 @@ static inline void sercom_clk_en(void *sercom)
static inline void sercom_clk_dis(void *sercom)
{
const uint8_t id = sercom_id(sercom);
#if defined(CPU_FAM_SAMD21)
#if defined(CPU_COMMON_SAMD21)
PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << id);
#elif defined (CPU_FAM_SAMD5X)
if (id < 2) {
@ -696,7 +696,7 @@ static inline void sercom_set_gen(void *sercom, uint8_t gclk)
{
const uint8_t id = sercom_id(sercom);
sam0_gclk_enable(gclk);
#if defined(CPU_FAM_SAMD21)
#if defined(CPU_COMMON_SAMD21)
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(gclk) |
(SERCOM0_GCLK_ID_CORE + id));
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}

2
cpu/sam0_common/periph/flashpage.c
View File

@ -139,7 +139,7 @@ static void _erase_page(void* page, void (*cmd_erase)(void))
/* ADDR drives the hardware (16-bit) address to the NVM when a command is executed using CMDEX.
* 8-bit addresses must be shifted one bit to the right before writing to this register.
*/
#if defined(CPU_SAMD21) || defined(CPU_SAML21)
#if defined(CPU_COMMON_SAMD21) || defined(CPU_SAML21)
page_addr >>= 1;
#endif

8
cpu/sam0_common/periph/gpio.c
View File

@ -180,7 +180,7 @@ void gpio_write(gpio_t pin, int value)
#ifdef MODULE_PERIPH_GPIO_IRQ
#ifdef CPU_FAM_SAMD21
#ifdef CPU_COMMON_SAMD21
#define EIC_SYNC() while (_EIC->STATUS.bit.SYNCBUSY)
#else
#define EIC_SYNC() while (_EIC->SYNCBUSY.bit.ENABLE)
@ -212,7 +212,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
/* configure pin as input and set MUX to peripheral function A */
gpio_init(pin, mode);
gpio_init_mux(pin, GPIO_MUX_A);
#ifdef CPU_FAM_SAMD21
#ifdef CPU_COMMON_SAMD21
/* enable clocks for the EIC module */
PM->APBAMASK.reg |= PM_APBAMASK_EIC;
GCLK->CLKCTRL.reg = EIC_GCLK_ID
@ -242,7 +242,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
/* clear interrupt flag and enable the interrupt line and line wakeup */
_EIC->INTFLAG.reg = (1 << exti);
_EIC->INTENSET.reg = (1 << exti);
#ifdef CPU_FAM_SAMD21
#ifdef CPU_COMMON_SAMD21
_EIC->WAKEUP.reg |= (1 << exti);
/* enable the EIC module*/
_EIC->CTRL.reg = EIC_CTRL_ENABLE;
@ -256,7 +256,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
}
inline static void reenable_eic(gpio_eic_clock_t clock) {
#if defined(CPU_SAMD21)
#if defined(CPU_COMMON_SAMD21)
if (clock == _EIC_CLOCK_SLOW) {
GCLK->CLKCTRL.reg = EIC_GCLK_ID
| GCLK_CLKCTRL_CLKEN

6
cpu/sam0_common/periph/rtc_rtt.c
View File

@ -131,7 +131,7 @@ static inline void _rtt_reset(void)
#endif
}
#ifdef CPU_SAMD21
#ifdef CPU_COMMON_SAMD21
static void _rtc_clock_setup(void)
{
/* Use 1024 Hz GCLK */
@ -150,7 +150,7 @@ static void _rtt_clock_setup(void)
while (GCLK->STATUS.bit.SYNCBUSY) {}
}
#else /* CPU_SAMD21 - Clock Setup */
#else /* CPU_COMMON_SAMD21 - Clock Setup */
static void _rtc_clock_setup(void)
{
@ -192,7 +192,7 @@ static void _rtt_clock_setup(void)
#error "No clock source for RTT selected. "
#endif
}
#endif /* !CPU_SAMD21 - Clock Setup */
#endif /* !CPU_COMMON_SAMD21 - Clock Setup */
static void _rtc_init(void)
{

4
cpu/sam0_common/periph/spi.c
View File

@ -233,14 +233,14 @@ static void _blocking_transfer(spi_t bus, const void *out, void *in, size_t len)
static void _dma_execute(spi_t bus)
{
#if defined(CPU_FAM_SAMD21)
#if defined(CPU_COMMON_SAMD21)
pm_block(SAMD21_PM_IDLE_1);
#endif
dma_start(_dma_state[bus].rx_dma);
dma_start(_dma_state[bus].tx_dma);
dma_wait(_dma_state[bus].rx_dma);
#if defined(CPU_FAM_SAMD21)
#if defined(CPU_COMMON_SAMD21)
pm_unblock(SAMD21_PM_IDLE_1);
#endif
}

6
cpu/sam0_common/periph/usbdev.c
View File

@ -242,7 +242,7 @@ static inline void _poweron(sam0_common_usb_t *dev)
PM->APBBMASK.reg |= PM_APBBMASK_USB;
#endif
#if defined(CPU_FAM_SAMD21)
#if defined(CPU_COMMON_SAMD21)
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN(dev->config->gclk_src)
| GCLK_CLKCTRL_ID(USB_GCLK_ID);
@ -294,14 +294,14 @@ static usbdev_ep_t *_usbdev_new_ep(usbdev_t *dev, usb_ep_type_t type,
static void _block_pm(void)
{
#if defined(CPU_FAM_SAMD21)
#if defined(CPU_COMMON_SAMD21)
pm_block(SAMD21_PM_IDLE_1);
#endif
}
static void _unblock_pm(void)
{
#if defined(CPU_FAM_SAMD21)
#if defined(CPU_COMMON_SAMD21)
pm_unblock(SAMD21_PM_IDLE_1);
#endif
}

4
cpu/sam0_common/periph/wdt.c
View File

@ -45,7 +45,7 @@
static inline void _set_enable(bool on)
{
/* work around strange watchdog behaviour if IDLE2 is used on samd21 */
#ifdef CPU_FAM_SAMD21
#ifdef CPU_COMMON_SAMD21
if (on) {
pm_block(1);
}
@ -80,7 +80,7 @@ static uint32_t ms_to_per(uint32_t ms)
return 29 - __builtin_clz(cycles - 1);
}
#ifdef CPU_SAMD21
#ifdef CPU_COMMON_SAMD21
static void _wdt_clock_setup(void)
{
/* Connect to GCLK3 (~1.024 kHz) */

2
cpu/samd21/Makefile.include
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@ -14,5 +14,7 @@ ifneq (,$(filter samr21%,$(CPU_MODEL)))
CFLAGS += -DCPU_SAMR21
endif
CFLAGS += -DCPU_COMMON_SAMD21
include $(RIOTCPU)/sam0_common/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk