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cpu/esp32: add support for IP101G Ethernet phy
As used in ESP32-Ethernet-Kit board: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-ethernet-kit.html Inspired by existing code for lan8720 PHY as well as latest ESP32 code: https://github.com/espressif/esp-idf/blob/master/components/esp_eth/src/esp_eth_phy_ip101.c Phy datasheet available: http://www.bdtic.com/ICplus/IP101G.html
This commit is contained in:
Erik Ekman
parent
7237e38436
commit
f28de6a544
@ -1142,7 +1142,7 @@ ESP32 provides different built-in possibilities to realize network devices:
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\anchor esp32_ethernet_network_interface
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## <a name="esp32_ethernet_network_interface"> Ethernet MAC Network Interface </a> [[TOC](#esp32_toc)]
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ESP32 provides an <b>Ethernet MAC layer module (EMAC)</b> according to the IEEE 802.3 standard which can be used together with an external physical layer chip (PHY) to realize a 100/10 Mbps Ethernet interface. Supported PHY chips are the Microchip LAN8710/LAN8720 and the Texas Instruments TLK110.
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ESP32 provides an <b>Ethernet MAC layer module (EMAC)</b> according to the IEEE 802.3 standard which can be used together with an external physical layer chip (PHY) to realize a 100/10 Mbps Ethernet interface. Supported PHY chips are the Microchip LAN8710/LAN8720, the IC Plus 101G, and the Texas Instruments TLK110.
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The RIOT port for ESP32 realizes with module ```esp_eth``` a ```netdev``` driver for the EMAC which uses RIOT's standard Ethernet interface.
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@ -16,7 +16,7 @@
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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ESP32 provides an <b>Ethernet MAC layer module (EMAC)</b> according to the IEEE 802.3 standard which can be used together with an external physical layer chip (PHY) to realize a 100/10 Mbps Ethernet interface. Supported PHY chips are the Microchip LAN8710/LAN8720 and the Texas Instruments TLK110.
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ESP32 provides an <b>Ethernet MAC layer module (EMAC)</b> according to the IEEE 802.3 standard which can be used together with an external physical layer chip (PHY) to realize a 100/10 Mbps Ethernet interface. Supported PHY chips are the Microchip LAN8710/LAN8720, the IC Plus 101G, and the Texas Instruments TLK110.
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The RIOT port for ESP32 realizes with module ```esp_eth``` a ```netdev``` driver for the EMAC which uses RIOT's standard Ethernet interface.
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@ -56,6 +56,10 @@
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#include "eth_phy/phy_lan8720.h"
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#define EMAC_ETHERNET_PHY_CONFIG phy_lan8720_default_ethernet_config
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#endif
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#ifdef EMAC_PHY_IP101G
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#include "eth_phy/phy_ip101g.h"
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#define EMAC_ETHERNET_PHY_CONFIG phy_ip101g_default_ethernet_config
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#endif
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#ifdef EMAC_PHY_TLK110
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#include "eth_phy/phy_tlk110.h"
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#define EMAC_ETHERNET_PHY_CONFIG phy_tlk110_default_ethernet_config
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154
cpu/esp32/vendor/esp-idf/ethernet/eth_phy/phy_ip101g.c
vendored
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154
cpu/esp32/vendor/esp-idf/ethernet/eth_phy/phy_ip101g.c
vendored
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@ -0,0 +1,154 @@
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_eth.h"
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#include "eth_phy/phy_ip101g.h"
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#include "eth_phy/phy_reg.h"
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/* Value of MII_PHY_IDENTIFIER_REGs for IC Plus IP101G
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* (Except for bottom 4 bits of ID2, used for model revision)
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*/
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#define IP101G_PHY_ID1 0x0243
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#define IP101G_PHY_ID2 0x0C50
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#define IP101G_PHY_ID2_MASK 0xFFF0
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/* IP101G-specific registers */
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#define PAGE_CONTROL_REG (0x14)
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#define POWER_DOWN BIT(11)
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#define PHY_SPECIAL_CONTROL_STATUS_REG (0x12)
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#define AUTO_NEGOTIATION_DONE BIT(11)
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#define PHY_CTRL_AND_SPECIFIC_STATUS_REG (0x1e)
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#define SPEED_DUPLEX_INDICATION_MASK (0x7)
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#define SPEED_DUPLEX_INDICATION_10T_HALF 0x01
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#define SPEED_DUPLEX_INDICATION_10T_FULL 0x05
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#define SPEED_DUPLEX_INDICATION_100T_HALF 0x02
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#define SPEED_DUPLEX_INDICATION_100T_FULL 0x06
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static const char *TAG = "ip101";
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static void phy_ip101g_page_select(uint8_t page)
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{
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ESP_LOGD(TAG, "phy_ip101g_page_select(%u)", page);
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esp_eth_smi_write(PAGE_CONTROL_REG, page);
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}
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void phy_ip101g_check_phy_init(void)
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{
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phy_ip101g_dump_registers();
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esp_eth_smi_wait_set(MII_BASIC_MODE_STATUS_REG, MII_AUTO_NEGOTIATION_COMPLETE, 0);
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phy_ip101g_page_select(16);
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esp_eth_smi_wait_set(PHY_SPECIAL_CONTROL_STATUS_REG, AUTO_NEGOTIATION_DONE, 0);
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}
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eth_speed_mode_t phy_ip101g_get_speed_mode(void)
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{
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phy_ip101g_page_select(16);
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uint16_t speed = esp_eth_smi_read(PHY_CTRL_AND_SPECIFIC_STATUS_REG) & SPEED_DUPLEX_INDICATION_MASK;
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if (speed == SPEED_DUPLEX_INDICATION_100T_HALF || speed == SPEED_DUPLEX_INDICATION_100T_FULL) {
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ESP_LOGD(TAG, "phy_ip101g_get_speed_mode(100)");
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return ETH_SPEED_MODE_100M;
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}
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ESP_LOGD(TAG, "phy_ip101g_get_speed_mode(10)");
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return ETH_SPEED_MODE_10M;
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}
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eth_duplex_mode_t phy_ip101g_get_duplex_mode(void)
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{
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phy_ip101g_page_select(16);
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uint16_t speed = esp_eth_smi_read(PHY_CTRL_AND_SPECIFIC_STATUS_REG) & SPEED_DUPLEX_INDICATION_MASK;
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if (speed == SPEED_DUPLEX_INDICATION_10T_FULL || speed == SPEED_DUPLEX_INDICATION_100T_FULL) {
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ESP_LOGD(TAG, "phy_ip101g_get_duplex_mode(FULL)");
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return ETH_MODE_FULLDUPLEX;
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}
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ESP_LOGD(TAG, "phy_ip101g_get_duplex_mode(HALF)");
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return ETH_MODE_HALFDUPLEX;
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}
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void phy_ip101g_power_enable(bool enable)
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{
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ESP_LOGD(TAG, "phy_ip101g_power_enable(%d)", enable);
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uint16_t cfg = esp_eth_smi_read(MII_BASIC_MODE_CONTROL_REG);
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if (enable) {
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cfg &= (UINT16_MAX ^ POWER_DOWN);
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} else {
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cfg |= POWER_DOWN;
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}
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esp_eth_smi_write(MII_BASIC_MODE_CONTROL_REG, cfg);
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// TODO: only enable if config.flow_ctrl_enable == true
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phy_mii_enable_flow_ctrl();
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}
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void phy_ip101g_init(void)
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{
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ESP_LOGD(TAG, "phy_ip101g_init()");
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phy_ip101g_dump_registers();
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esp_eth_smi_write(MII_BASIC_MODE_CONTROL_REG, MII_SOFTWARE_RESET);
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esp_err_t res1, res2;
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do {
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// Call esp_eth_smi_wait_value() with a timeout so it prints an error periodically
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res1 = esp_eth_smi_wait_value(MII_PHY_IDENTIFIER_1_REG, IP101G_PHY_ID1, UINT16_MAX, 1000);
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res2 = esp_eth_smi_wait_value(MII_PHY_IDENTIFIER_2_REG, IP101G_PHY_ID2, IP101G_PHY_ID2_MASK, 1000);
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} while(res1 != ESP_OK || res2 != ESP_OK);
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ets_delay_us(300);
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// TODO: only enable if config.flow_ctrl_enable == true
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phy_mii_enable_flow_ctrl();
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}
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const eth_config_t phy_ip101g_default_ethernet_config = {
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// By default, the PHY address is 0 or 1 based on PHYAD0
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// pin. Can also be overriden in software. See datasheet
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// for defaults.
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.phy_addr = 1,
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.mac_mode = ETH_MODE_RMII,
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.clock_mode = ETH_CLOCK_GPIO0_IN,
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//Only FULLDUPLEX mode support flow ctrl now!
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.flow_ctrl_enable = true,
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.phy_init = phy_ip101g_init,
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.phy_check_init = phy_ip101g_check_phy_init,
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.phy_power_enable = phy_ip101g_power_enable,
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.phy_check_link = phy_mii_check_link_status,
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.phy_get_speed_mode = phy_ip101g_get_speed_mode,
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.phy_get_duplex_mode = phy_ip101g_get_duplex_mode,
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.phy_get_partner_pause_enable = phy_mii_get_partner_pause_enable,
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};
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void phy_ip101g_dump_registers(void)
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{
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ESP_LOGD(TAG, "IP101G Registers:");
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ESP_LOGD(TAG, "BCR 0x%04x", esp_eth_smi_read(0x0));
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ESP_LOGD(TAG, "BSR 0x%04x", esp_eth_smi_read(0x1));
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ESP_LOGD(TAG, "PHY1 0x%04x", esp_eth_smi_read(0x2));
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ESP_LOGD(TAG, "PHY2 0x%04x", esp_eth_smi_read(0x3));
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ESP_LOGD(TAG, "ANAR 0x%04x", esp_eth_smi_read(0x4));
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ESP_LOGD(TAG, "ANLPAR 0x%04x", esp_eth_smi_read(0x5));
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ESP_LOGD(TAG, "ANER 0x%04x", esp_eth_smi_read(0x6));
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phy_ip101g_page_select(16);
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ESP_LOGD(TAG, "PSCR 0x%04x", esp_eth_smi_read(0x10));
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ESP_LOGD(TAG, "PSMR 0x%04x", esp_eth_smi_read(0x18));
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ESP_LOGD(TAG, "PMCSSR 0x%04x", esp_eth_smi_read(0x1e));
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}
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73
cpu/esp32/vendor/esp-idf/include/ethernet/eth_phy/phy_ip101g.h
vendored
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73
cpu/esp32/vendor/esp-idf/include/ethernet/eth_phy/phy_ip101g.h
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@ -0,0 +1,73 @@
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef ETHERNET_ETH_PHY_PHY_IP101G_H
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#define ETHERNET_ETH_PHY_PHY_IP101G_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef RIOT_VERSION
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#include "eth_phy/phy.h"
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#else
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#include "phy.h"
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#endif
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/** @brief Dump all IP101G PHY SMI configuration registers
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*
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* @note These registers are dumped at 'debug' level, so output
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* may not be visible depending on default log levels.
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*/
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void phy_ip101g_dump_registers(void);
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/** @brief Default IP101G phy_check_init function.
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*/
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void phy_ip101g_check_phy_init(void);
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/** @brief Default IP101G phy_get_speed_mode function.
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*/
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eth_speed_mode_t phy_ip101g_get_speed_mode(void);
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/** @brief Default IP101G phy_get_duplex_mode function.
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*/
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eth_duplex_mode_t phy_ip101g_get_duplex_mode(void);
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/** @brief Default IP101G phy_power_enable function.
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*
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* @note This function may need to be replaced with a custom function
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* if the PHY has a GPIO to enable power or start a clock.
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*
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* Consult the ethernet example to see how this is done.
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*/
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void phy_ip101g_power_enable(bool);
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/** @brief Default IP101G phy_init function.
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*/
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void phy_ip101g_init(void);
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/** @brief Default IP101G PHY configuration
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*
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* This configuration is not suitable for use as-is, it will need
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* to be modified for your particular PHY hardware setup.
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*
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* Consult the Ethernet example to see how this is done.
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*/
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extern const eth_config_t phy_ip101g_default_ethernet_config;
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#ifdef __cplusplus
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}
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#endif
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#endif /* ETHERNET_ETH_PHY_PHY_IP101G_H */
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