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Add vendor files for the NXP QN908x cpu

Browse Source 
In preparation for adding support for the QN908x cpus, this patch adds
a pristine copy of the vendor SDK files needed for initial support.
The only modification to these files is to add '#ifdef __cplusplus'
guards to all the header files, even if not needed or already
present as '#if defined(__cplusplus)', to make sure
./dist/tools/externc/check.sh check passes.

These files are located under vendor/ directories (both
cpu/qn908x/include/vendor/ and cpu/qn908x/vendor/) and are part of NXP's
SDK for the QN908x family available for download from:
  https://mcuxpresso.nxp.com/en/builder

The files included in these vendor/ directories are released by NXP
under an Open Source license as described in each file, but only the
files used by the next patch are included here.
This commit is contained in:
iosabi 2020-11-30 02:53:59 +00:00
parent 3234b918e3
commit 21fd1f9258
6 changed files with 11150 additions and 0 deletions
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9491
cpu/qn908x/include/vendor/QN908XC.h vendored Normal file
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/*
** ###################################################################
** Version: rev. 1.0, 2017-03-27
** Build: b170421
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2017-03-27)
** Initial version.
**
** ###################################################################
*/
#ifndef _QN908XC_FEATURES_H_
#define _QN908XC_FEATURES_H_
#ifdef __cplusplus
extern "C" {
#endif
/* SOC module features */
/* @brief ACMP availability on the SoC. */
#define FSL_FEATURE_SOC_ACMP_COUNT (2)
/* @brief ADC availability on the SoC. */
#define FSL_FEATURE_SOC_ADC_COUNT (1)
/* @brief ADC12 availability on the SoC. */
#define FSL_FEATURE_SOC_ADC12_COUNT (0)
/* @brief ADC16 availability on the SoC. */
#define FSL_FEATURE_SOC_ADC16_COUNT (0)
/* @brief ADC_5HC availability on the SoC. */
#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0)
/* @brief AES availability on the SoC. */
#define FSL_FEATURE_SOC_AES_COUNT (0)
/* @brief HW AES availability on the SoC. */
#define FSL_FEATURE_SOC_AES_HW (1)
/* @brief AFE availability on the SoC. */
#define FSL_FEATURE_SOC_AFE_COUNT (0)
/* @brief AGC availability on the SoC. */
#define FSL_FEATURE_SOC_AGC_COUNT (1)
/* @brief AIPS availability on the SoC. */
#define FSL_FEATURE_SOC_AIPS_COUNT (0)
/* @brief AIPSTZ availability on the SoC. */
#define FSL_FEATURE_SOC_AIPSTZ_COUNT (0)
/* @brief ANATOP availability on the SoC. */
#define FSL_FEATURE_SOC_ANATOP_COUNT (0)
/* @brief AOI availability on the SoC. */
#define FSL_FEATURE_SOC_AOI_COUNT (0)
/* @brief APBH availability on the SoC. */
#define FSL_FEATURE_SOC_APBH_COUNT (0)
/* @brief ASMC availability on the SoC. */
#define FSL_FEATURE_SOC_ASMC_COUNT (0)
/* @brief ASRC availability on the SoC. */
#define FSL_FEATURE_SOC_ASRC_COUNT (0)
/* @brief ASYNC_SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0)
/* @brief ATX availability on the SoC. */
#define FSL_FEATURE_SOC_ATX_COUNT (0)
/* @brief AXBS availability on the SoC. */
#define FSL_FEATURE_SOC_AXBS_COUNT (0)
/* @brief BCH availability on the SoC. */
#define FSL_FEATURE_SOC_BCH_COUNT (0)
/* @brief BLEDP availability on the SoC. */
#define FSL_FEATURE_SOC_BLEDP_COUNT (1)
/* @brief BOD availability on the SoC. */
#define FSL_FEATURE_SOC_BOD_COUNT (1)
/* @brief CAAM availability on the SoC. */
#define FSL_FEATURE_SOC_CAAM_COUNT (0)
/* @brief CADC availability on the SoC. */
#define FSL_FEATURE_SOC_CADC_COUNT (0)
/* @brief CALIB availability on the SoC. */
#define FSL_FEATURE_SOC_CALIB_COUNT (1)
/* @brief CAN availability on the SoC. */
#define FSL_FEATURE_SOC_CAN_COUNT (0)
/* @brief CAU availability on the SoC. */
#define FSL_FEATURE_SOC_CAU_COUNT (0)
/* @brief CAU3 availability on the SoC. */
#define FSL_FEATURE_SOC_CAU3_COUNT (0)
/* @brief CCM availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_COUNT (0)
/* @brief CCM_ANALOG availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (0)
/* @brief CHRG availability on the SoC. */
#define FSL_FEATURE_SOC_CHRG_COUNT (0)
/* @brief CMP availability on the SoC. */
#define FSL_FEATURE_SOC_CMP_COUNT (0)
/* @brief CMT availability on the SoC. */
#define FSL_FEATURE_SOC_CMT_COUNT (0)
/* @brief CNC availability on the SoC. */
#define FSL_FEATURE_SOC_CNC_COUNT (0)
/* @brief COP availability on the SoC. */
#define FSL_FEATURE_SOC_COP_COUNT (0)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (1)
/* @brief CS availability on the SoC. */
#define FSL_FEATURE_SOC_CS_COUNT (1)
/* @brief CSI availability on the SoC. */
#define FSL_FEATURE_SOC_CSI_COUNT (0)
/* @brief CT32B availability on the SoC. */
#define FSL_FEATURE_SOC_CT32B_COUNT (0)
/* @brief CTI availability on the SoC. */
#define FSL_FEATURE_SOC_CTI_COUNT (0)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (4)
/* @brief DAC availability on the SoC. */
#define FSL_FEATURE_SOC_DAC_COUNT (1)
/* @brief DAC32 availability on the SoC. */
#define FSL_FEATURE_SOC_DAC32_COUNT (0)
/* @brief DCDC availability on the SoC. */
#define FSL_FEATURE_SOC_DCDC_COUNT (0)
/* @brief DCP availability on the SoC. */
#define FSL_FEATURE_SOC_DCP_COUNT (0)
/* @brief DDR availability on the SoC. */
#define FSL_FEATURE_SOC_DDR_COUNT (0)
/* @brief DDRC availability on the SoC. */
#define FSL_FEATURE_SOC_DDRC_COUNT (0)
/* @brief DDRC_MP availability on the SoC. */
#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0)
/* @brief DDR_PHY availability on the SoC. */
#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (1)
/* @brief DMAMUX availability on the SoC. */
#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
/* @brief DMIC availability on the SoC. */
#define FSL_FEATURE_SOC_DMIC_COUNT (0)
/* @brief DRY availability on the SoC. */
#define FSL_FEATURE_SOC_DRY_COUNT (0)
/* @brief DSPI availability on the SoC. */
#define FSL_FEATURE_SOC_DSPI_COUNT (0)
/* @brief ECSPI availability on the SoC. */
#define FSL_FEATURE_SOC_ECSPI_COUNT (0)
/* @brief EDMA availability on the SoC. */
#define FSL_FEATURE_SOC_EDMA_COUNT (0)
/* @brief EEPROM availability on the SoC. */
#define FSL_FEATURE_SOC_EEPROM_COUNT (0)
/* @brief EIM availability on the SoC. */
#define FSL_FEATURE_SOC_EIM_COUNT (0)
/* @brief EMC availability on the SoC. */
#define FSL_FEATURE_SOC_EMC_COUNT (0)
/* @brief EMVSIM availability on the SoC. */
#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
/* @brief ENC availability on the SoC. */
#define FSL_FEATURE_SOC_ENC_COUNT (0)
/* @brief ENET availability on the SoC. */
#define FSL_FEATURE_SOC_ENET_COUNT (0)
/* @brief EPDC availability on the SoC. */
#define FSL_FEATURE_SOC_EPDC_COUNT (0)
/* @brief EPIT availability on the SoC. */
#define FSL_FEATURE_SOC_EPIT_COUNT (0)
/* @brief ESAI availability on the SoC. */
#define FSL_FEATURE_SOC_ESAI_COUNT (0)
/* @brief EWM availability on the SoC. */
#define FSL_FEATURE_SOC_EWM_COUNT (0)
/* @brief FB availability on the SoC. */
#define FSL_FEATURE_SOC_FB_COUNT (0)
/* @brief FGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
/* @brief FLASH availability on the SoC. */
#define FSL_FEATURE_SOC_FLASH_COUNT (1)
/* @brief FLEXCAN availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
/* @brief FLEXCOMM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (4)
/* @brief FLEXIO availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
/* @brief FLEXRAM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXRAM_COUNT (0)
/* @brief FLEXSPI availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXSPI_COUNT (0)
/* @brief FMC availability on the SoC. */
#define FSL_FEATURE_SOC_FMC_COUNT (0)
/* @brief FSKDT availability on the SoC. */
#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
/* @brief FSP availability on the SoC. */
#define FSL_FEATURE_SOC_FSP_COUNT (1)
/* @brief FTFA availability on the SoC. */
#define FSL_FEATURE_SOC_FTFA_COUNT (0)
/* @brief FTFE availability on the SoC. */
#define FSL_FEATURE_SOC_FTFE_COUNT (0)
/* @brief FTFL availability on the SoC. */
#define FSL_FEATURE_SOC_FTFL_COUNT (0)
/* @brief FTM availability on the SoC. */
#define FSL_FEATURE_SOC_FTM_COUNT (0)
/* @brief FTMRA availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
/* @brief FTMRE availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
/* @brief FTMRH availability on the SoC. */
#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
/* @brief GINT availability on the SoC. */
#define FSL_FEATURE_SOC_GINT_COUNT (0)
/* @brief GPC availability on the SoC. */
#define FSL_FEATURE_SOC_GPC_COUNT (0)
/* @brief GPC_PGC availability on the SoC. */
#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0)
/* @brief GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_GPIO_COUNT (2)
/* @brief GPMI availability on the SoC. */
#define FSL_FEATURE_SOC_GPMI_COUNT (0)
/* @brief GPT availability on the SoC. */
#define FSL_FEATURE_SOC_GPT_COUNT (0)
/* @brief HSADC availability on the SoC. */
#define FSL_FEATURE_SOC_HSADC_COUNT (0)
/* @brief I2C availability on the SoC. */
#define FSL_FEATURE_SOC_I2C_COUNT (2)
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (0)
/* @brief ICS availability on the SoC. */
#define FSL_FEATURE_SOC_ICS_COUNT (0)
/* @brief IEE availability on the SoC. */
#define FSL_FEATURE_SOC_IEE_COUNT (0)
/* @brief IEER availability on the SoC. */
#define FSL_FEATURE_SOC_IEER_COUNT (0)
/* @brief IGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_IGPIO_COUNT (0)
/* @brief II2C availability on the SoC. */
#define FSL_FEATURE_SOC_II2C_COUNT (0)
/* @brief INPUTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (0)
/* @brief INTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
/* @brief IOCON availability on the SoC. */
#define FSL_FEATURE_SOC_IOCON_COUNT (0)
/* @brief IOMUXC availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_COUNT (0)
/* @brief IOMUXC_GPR availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (0)
/* @brief IOMUXC_LPSR availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0)
/* @brief IOMUXC_LPSR_GPR availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0)
/* @brief IOMUXC_SNVS availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (0)
/* @brief IPWM availability on the SoC. */
#define FSL_FEATURE_SOC_IPWM_COUNT (0)
/* @brief IRQ availability on the SoC. */
#define FSL_FEATURE_SOC_IRQ_COUNT (0)
/* @brief IUART availability on the SoC. */
#define FSL_FEATURE_SOC_IUART_COUNT (0)
/* @brief KBI availability on the SoC. */
#define FSL_FEATURE_SOC_KBI_COUNT (0)
/* @brief KPP availability on the SoC. */
#define FSL_FEATURE_SOC_KPP_COUNT (0)
/* @brief L2CACHEC availability on the SoC. */
#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0)
/* @brief LCD availability on the SoC. */
#define FSL_FEATURE_SOC_LCD_COUNT (0)
/* @brief LCDC availability on the SoC. */
#define FSL_FEATURE_SOC_LCDC_COUNT (0)
/* @brief LCDIF availability on the SoC. */
#define FSL_FEATURE_SOC_LCDIF_COUNT (0)
/* @brief LDO availability on the SoC. */
#define FSL_FEATURE_SOC_LDO_COUNT (0)
/* @brief LLWU availability on the SoC. */
#define FSL_FEATURE_SOC_LLWU_COUNT (0)
/* @brief LMEM availability on the SoC. */
#define FSL_FEATURE_SOC_LMEM_COUNT (0)
/* @brief LPADC availability on the SoC. */
#define FSL_FEATURE_SOC_LPADC_COUNT (0)
/* @brief LPCMP availability on the SoC. */
#define FSL_FEATURE_SOC_LPCMP_COUNT (0)
/* @brief LPDAC availability on the SoC. */
#define FSL_FEATURE_SOC_LPDAC_COUNT (0)
/* @brief LPI2C availability on the SoC. */
#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
/* @brief LPIT availability on the SoC. */
#define FSL_FEATURE_SOC_LPIT_COUNT (0)
/* @brief LPSCI availability on the SoC. */
#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
/* @brief LPSPI availability on the SoC. */
#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
/* @brief LPTMR availability on the SoC. */
#define FSL_FEATURE_SOC_LPTMR_COUNT (0)
/* @brief LPTPM availability on the SoC. */
#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
/* @brief LPUART availability on the SoC. */
#define FSL_FEATURE_SOC_LPUART_COUNT (0)
/* @brief LTC availability on the SoC. */
#define FSL_FEATURE_SOC_LTC_COUNT (0)
/* @brief MAILBOX availability on the SoC. */
#define FSL_FEATURE_SOC_MAILBOX_COUNT (0)
/* @brief MC availability on the SoC. */
#define FSL_FEATURE_SOC_MC_COUNT (0)
/* @brief MCG availability on the SoC. */
#define FSL_FEATURE_SOC_MCG_COUNT (0)
/* @brief MCGLITE availability on the SoC. */
#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
/* @brief MCM availability on the SoC. */
#define FSL_FEATURE_SOC_MCM_COUNT (0)
/* @brief MIPI_CSI2 availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0)
/* @brief MIPI_DSI availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0)
/* @brief MIPI_DSI_HOST availability on the SoC. */
#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0)
/* @brief MMAU availability on the SoC. */
#define FSL_FEATURE_SOC_MMAU_COUNT (0)
/* @brief MMCAU availability on the SoC. */
#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
/* @brief MMDC availability on the SoC. */
#define FSL_FEATURE_SOC_MMDC_COUNT (0)
/* @brief MMDVSQ availability on the SoC. */
#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
/* @brief MPU availability on the SoC. */
#define FSL_FEATURE_SOC_MPU_COUNT (0)
/* @brief MRT availability on the SoC. */
#define FSL_FEATURE_SOC_MRT_COUNT (0)
/* @brief MSCAN availability on the SoC. */
#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
/* @brief MSCM availability on the SoC. */
#define FSL_FEATURE_SOC_MSCM_COUNT (0)
/* @brief MTB availability on the SoC. */
#define FSL_FEATURE_SOC_MTB_COUNT (0)
/* @brief MTBDWT availability on the SoC. */
#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
/* @brief MU availability on the SoC. */
#define FSL_FEATURE_SOC_MU_COUNT (0)
/* @brief NFC availability on the SoC. */
#define FSL_FEATURE_SOC_NFC_COUNT (0)
/* @brief OCOTP availability on the SoC. */
#define FSL_FEATURE_SOC_OCOTP_COUNT (0)
/* @brief OPAMP availability on the SoC. */
#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
/* @brief OSC availability on the SoC. */
#define FSL_FEATURE_SOC_OSC_COUNT (0)
/* @brief OSC32 availability on the SoC. */
#define FSL_FEATURE_SOC_OSC32_COUNT (0)
/* @brief OTFAD availability on the SoC. */
#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
/* @brief PCC availability on the SoC. */
#define FSL_FEATURE_SOC_PCC_COUNT (0)
/* @brief PCIE_PHY_CMN availability on the SoC. */
#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0)
/* @brief PCIE_PHY_TRSV availability on the SoC. */
#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0)
/* @brief PDB availability on the SoC. */
#define FSL_FEATURE_SOC_PDB_COUNT (0)
/* @brief PGA availability on the SoC. */
#define FSL_FEATURE_SOC_PGA_COUNT (0)
/* @brief PINT availability on the SoC. */
#define FSL_FEATURE_SOC_PINT_COUNT (1)
/* @brief PIT availability on the SoC. */
#define FSL_FEATURE_SOC_PIT_COUNT (0)
/* @brief PMC availability on the SoC. */
#define FSL_FEATURE_SOC_PMC_COUNT (0)
/* @brief PMU availability on the SoC. */
#define FSL_FEATURE_SOC_PMU_COUNT (0)
/* @brief PORT availability on the SoC. */
#define FSL_FEATURE_SOC_PORT_COUNT (0)
/* @brief PROP availability on the SoC. */
#define FSL_FEATURE_SOC_PROP_COUNT (1)
/* @brief PWM availability on the SoC. */
#define FSL_FEATURE_SOC_PWM_COUNT (0)
/* @brief PWT availability on the SoC. */
#define FSL_FEATURE_SOC_PWT_COUNT (0)
/* @brief PXP availability on the SoC. */
#define FSL_FEATURE_SOC_PXP_COUNT (0)
/* @brief QDEC availability on the SoC. */
#define FSL_FEATURE_SOC_QDEC_COUNT (2)
/* @brief QuadSPI availability on the SoC. */
#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
/* @brief RCM availability on the SoC. */
#define FSL_FEATURE_SOC_RCM_COUNT (0)
/* @brief RDC availability on the SoC. */
#define FSL_FEATURE_SOC_RDC_COUNT (0)
/* @brief RDC_SEMAPHORE availability on the SoC. */
#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0)
/* @brief RFSYS availability on the SoC. */
#define FSL_FEATURE_SOC_RFSYS_COUNT (0)
/* @brief RFVBAT availability on the SoC. */
#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
/* @brief RIT availability on the SoC. */
#define FSL_FEATURE_SOC_RIT_COUNT (0)
/* @brief RNG availability on the SoC. */
#define FSL_FEATURE_SOC_RNG_COUNT (1)
/* @brief RNGB availability on the SoC. */
#define FSL_FEATURE_SOC_RNGB_COUNT (0)
/* @brief ROM availability on the SoC. */
#define FSL_FEATURE_SOC_ROM_COUNT (0)
/* @brief ROMC availability on the SoC. */
#define FSL_FEATURE_SOC_ROMC_COUNT (0)
/* @brief RSIM availability on the SoC. */
#define FSL_FEATURE_SOC_RSIM_COUNT (0)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (1)
/* @brief SCG availability on the SoC. */
#define FSL_FEATURE_SOC_SCG_COUNT (0)
/* @brief SCI availability on the SoC. */
#define FSL_FEATURE_SOC_SCI_COUNT (0)
/* @brief SCT availability on the SoC. */
#define FSL_FEATURE_SOC_SCT_COUNT (1)
/* @brief SDHC availability on the SoC. */
#define FSL_FEATURE_SOC_SDHC_COUNT (0)
/* @brief SDIF availability on the SoC. */
#define FSL_FEATURE_SOC_SDIF_COUNT (0)
/* @brief SDIO availability on the SoC. */
#define FSL_FEATURE_SOC_SDIO_COUNT (0)
/* @brief SDMA availability on the SoC. */
#define FSL_FEATURE_SOC_SDMA_COUNT (0)
/* @brief SDMAARM availability on the SoC. */
#define FSL_FEATURE_SOC_SDMAARM_COUNT (0)
/* @brief SDMABP availability on the SoC. */
#define FSL_FEATURE_SOC_SDMABP_COUNT (0)
/* @brief SDMACORE availability on the SoC. */
#define FSL_FEATURE_SOC_SDMACORE_COUNT (0)
/* @brief SDMCORE availability on the SoC. */
#define FSL_FEATURE_SOC_SDMCORE_COUNT (0)
/* @brief SDRAM availability on the SoC. */
#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
/* @brief SEMA4 availability on the SoC. */
#define FSL_FEATURE_SOC_SEMA4_COUNT (0)
/* @brief SEMA42 availability on the SoC. */
#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
/* @brief SHA availability on the SoC. */
#define FSL_FEATURE_SOC_SHA_COUNT (0)
/* @brief SIM availability on the SoC. */
#define FSL_FEATURE_SOC_SIM_COUNT (0)
/* @brief SIMDGO availability on the SoC. */
#define FSL_FEATURE_SOC_SIMDGO_COUNT (0)
/* @brief SJC availability on the SoC. */
#define FSL_FEATURE_SOC_SJC_COUNT (0)
/* @brief SLCD availability on the SoC. */
#define FSL_FEATURE_SOC_SLCD_COUNT (0)
/* @brief SMARTCARD availability on the SoC. */
#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0)
/* @brief SMC availability on the SoC. */
#define FSL_FEATURE_SOC_SMC_COUNT (0)
/* @brief SNVS availability on the SoC. */
#define FSL_FEATURE_SOC_SNVS_COUNT (0)
/* @brief SPBA availability on the SoC. */
#define FSL_FEATURE_SOC_SPBA_COUNT (0)
/* @brief SPDIF availability on the SoC. */
#define FSL_FEATURE_SOC_SPDIF_COUNT (0)
/* @brief SPI availability on the SoC. */
#define FSL_FEATURE_SOC_SPI_COUNT (2)
/* @brief SPIFI availability on the SoC. */
#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
/* @brief SPM availability on the SoC. */
#define FSL_FEATURE_SOC_SPM_COUNT (0)
/* @brief SRC availability on the SoC. */
#define FSL_FEATURE_SOC_SRC_COUNT (0)
/* @brief SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
/* @brief TEMPMON availability on the SoC. */
#define FSL_FEATURE_SOC_TEMPMON_COUNT (0)
/* @brief TMR availability on the SoC. */
#define FSL_FEATURE_SOC_TMR_COUNT (0)
/* @brief TPM availability on the SoC. */
#define FSL_FEATURE_SOC_TPM_COUNT (0)
/* @brief TRGMUX availability on the SoC. */
#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
/* @brief TRIAMP availability on the SoC. */
#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
/* @brief TRNG availability on the SoC. */
#define FSL_FEATURE_SOC_TRNG_COUNT (0)
/* @brief TSC availability on the SoC. */
#define FSL_FEATURE_SOC_TSC_COUNT (0)
/* @brief TSI availability on the SoC. */
#define FSL_FEATURE_SOC_TSI_COUNT (0)
/* @brief TSTMR availability on the SoC. */
#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
/* @brief UART availability on the SoC. */
#define FSL_FEATURE_SOC_UART_COUNT (0)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_USART_COUNT (2)
/* @brief USB availability on the SoC. */
#define FSL_FEATURE_SOC_USB_COUNT (1)
/* @brief USBHS availability on the SoC. */
#define FSL_FEATURE_SOC_USBHS_COUNT (0)
/* @brief USBDCD availability on the SoC. */
#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
/* @brief USBFSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBFSH_COUNT (0)
/* @brief USBHSD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSD_COUNT (0)
/* @brief USBHSDCD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
/* @brief USBHSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSH_COUNT (0)
/* @brief USBNC availability on the SoC. */
#define FSL_FEATURE_SOC_USBNC_COUNT (0)
/* @brief USBPHY availability on the SoC. */
#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
/* @brief USB_HSIC availability on the SoC. */
#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0)
/* @brief USB_OTG availability on the SoC. */
#define FSL_FEATURE_SOC_USB_OTG_COUNT (0)
/* @brief USDHC availability on the SoC. */
#define FSL_FEATURE_SOC_USDHC_COUNT (0)
/* @brief UTICK availability on the SoC. */
#define FSL_FEATURE_SOC_UTICK_COUNT (0)
/* @brief VIU availability on the SoC. */
#define FSL_FEATURE_SOC_VIU_COUNT (0)
/* @brief VREF availability on the SoC. */
#define FSL_FEATURE_SOC_VREF_COUNT (0)
/* @brief VFIFO availability on the SoC. */
#define FSL_FEATURE_SOC_VFIFO_COUNT (0)
/* @brief WDOG availability on the SoC. */
#define FSL_FEATURE_SOC_WDOG_COUNT (1)
/* @brief WKPU availability on the SoC. */
#define FSL_FEATURE_SOC_WKPU_COUNT (0)
/* @brief WWDT availability on the SoC. */
#define FSL_FEATURE_SOC_WWDT_COUNT (0)
/* @brief XBAR availability on the SoC. */
#define FSL_FEATURE_SOC_XBAR_COUNT (0)
/* @brief XBARA availability on the SoC. */
#define FSL_FEATURE_SOC_XBARA_COUNT (0)
/* @brief XBARB availability on the SoC. */
#define FSL_FEATURE_SOC_XBARB_COUNT (0)
/* @brief XCVR availability on the SoC. */
#define FSL_FEATURE_SOC_XCVR_COUNT (0)
/* @brief XRDC availability on the SoC. */
#define FSL_FEATURE_SOC_XRDC_COUNT (0)
/* @brief XTALOSC availability on the SoC. */
#define FSL_FEATURE_SOC_XTALOSC_COUNT (0)
/* @brief XTALOSC24M availability on the SoC. */
#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (0)
/* @brief ZLL availability on the SoC. */
#define FSL_FEATURE_SOC_ZLL_COUNT (0)
/* CRC module features */
/* @brief CRC for boot info */
#define FSL_FEATURE_CRC_BASE_ADDR (0x210B0700)
/* @brief Boot version */
#define FSL_FEATURE_CRC_READ_BASE_ADDR (0x31000000)
/* @brief Boot feature */
#define FSL_FEATURE_CRC_LOCK_BIT_STORE_ADDR (0x2107F800)
/* CTIMER module features */
/* @brief Has CTIMER IR_CR3INT (register bit IR[CR3INT]). */
#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (0)
/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (0)
/* DMA module features */
/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20)
/* FLASH module features */
/* @brief Flash size in bytes */
#define FSL_FEATURE_FLASH_SIZE_BYTES (524288U)
/* @brief Flash page size in bytes */
#define FSL_FEATURE_FLASH_PAGE_SIZE_BYTES (2048U)
/* @brief Flash block write unit in bytes */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (0x4U)
/* @brief P-Flash block count */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
/* @brief P-Flash block size */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x40000U)
/* @brief Flash base address */
#define FSL_FEATURE_FLASH_BASE_ADDR (0x21000000U)
/* @brief Flash read base address */
#define FSL_FEATURE_FLASH_READ_BASE_ADDR (0x31000000U)
/* @brief Flash lock bit address */
#define FSL_FEATURE_FLASH_LOCK_BIT_STORE_ADDR (0x2107F800U)
/* @brief Flash information page address */
#define FSL_FEATURE_FLASH_INFO_BASE_ADDR (0x210B0000U)
/* @brief CRC for boot info (4 Bytes) */
#define FSL_FEATURE_FLASH_ADDR_OF_BOOT_CRC (0x210B0700U)
/* @brief Boot version (4 Bytes) */
#define FSL_FEATURE_FLASH_ADDR_OF_BOOT_VERSION (0x210B0704U)
/* @brief Boot feature (4 Bytes) */
#define FSL_FEATURE_FLASH_ADDR_OF_BOOT_FEATURE (0x210B0708U)
/* @brief Temperature sensor calibration value (4 Bytes) */
#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL (0x210B07F0U)
/* @brief Bandgap voltage for ADC reference calibration (4 Bytes) */
#define FSL_FEATURE_FLASH_ADDR_OF_BANDGAP_VOL (0x210B07F4U)
/* @brief Main Bandgap voltage calibration (4 Bytes) */
#define FSL_FEATURE_FLASH_ADDR_OF_MAINBANDGAP_VOL (0x210B070CU)
/* @brief Vendor bluetooth address(MAC) (6 Bytes) */
#define FSL_FEATURE_FLASH_ADDR_OF_VENDOR_BD_ADDR (0x210B07FAU)
/* PINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
/* RTC module features */
/* @brief RTC has Free Running Counter */
#define FSL_FEATURE_RTC_HAS_FRC (1)
/* SCT module features */
/* @brief Number of events */
#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10)
/* @brief Number of states */
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10)
/* @brief Number of match capture */
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10)
#ifdef __cplusplus
}
#endif
#endif /* _QN908XC_FEATURES_H_ */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016 - 2017 , NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CLOCK_H_
#define _FSL_CLOCK_H_
#include "fsl_common.h"
/*! @addtogroup clock */
/*! @{ */
/*! @file */
/*******************************************************************************
* Definitions
*****************************************************************************/
/* To calculate flexcomm clock for baud rate correction */
#define FLEXCOMM_CLK(srcClock_Hz, baudrate_Bps) ((((srcClock_Hz) / 8) / baudrate_Bps) * baudrate_Bps * 8)
/*! @brief Configure whether driver controls clock
*
* When set to 0, peripheral drivers will enable clock in initialize function
* and disable clock in de-initialize function. When set to 1, peripheral
* driver will not control the clock, application could contol the clock out of
* the driver.
*
* @note All drivers share this feature switcher. If it is set to 1, application
* should handle clock enable and disable for all drivers.
*/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
#endif
/*! @brief Clock ip name array for LPUART. */
#define LPUART_CLOCKS \
{ \
kCLOCK_Flexcomm0, kCLOCK_Flexcomm1 \
}
/*! @brief Clock ip name array for BI2C. */
#define BI2C_CLOCKS \
{ \
kCLOCK_Flexcomm1, kCLOCK_Flexcomm2 \
}
/*! @brief Clock ip name array for FLEXCOMM. */
#define FLEXCOMM_CLOCKS \
{ \
kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3 \
}
/*! @brief Clock ip name array for CRC. */
#define CRC_CLOCKS \
{ \
kCLOCK_Crc \
}
/*! @brief Clock ip name array for CTIMER. */
#define CTIMER_CLOCKS \
{ \
kCLOCK_Ctimer0, kCLOCK_Ctimer1, kCLOCK_Ctimer2, kCLOCK_Ctimer3 \
}
/*! @brief Clock ip name array for SCTimer. */
#define SCT_CLOCKS \
{ \
kCLOCK_Sct0 \
}
/*! @brief Clock ip name array for GPIO. */
#define GPIO_CLOCKS \
{ \
kCLOCK_Gpio \
}
/*! @brief Clock ip name array for Calibration. */
#define CAL_CLOCKS \
{ \
kCLOCK_Cal \
}
/*! @brief Clock ip name array for USBD. */
#define USBD_CLOCKS \
{ \
kCLOCK_Usbd0 \
}
/*! @brief Clock ip name array for WDT. */
#define WDT_CLOCKS \
{ \
kCLOCK_Wdt \
}
/*! @brief Clock ip name array for BIV(including RTC and SYSCON clock). Enabled as default */
#define BIV_CLOCKS \
{ \
kCLOCK_Biv \
}
/*! @brief Clock ip name array for ADC. */
#define ADC_CLOCKS \
{ \
kCLOCK_Adc \
}
/*! @brief Clock ip name array for DAC. */
#define DAC_CLOCKS \
{ \
kCLOCK_Dac \
}
/*! @brief Clock ip name array for CS. */
#define CS_CLOCKS \
{ \
kCLOCK_Cs \
}
/*! @brief Clock ip name array for FSP. */
#define FSP_CLOCKS \
{ \
kCLOCK_Fsp \
}
/*! @brief Clock ip name array for DMA. */
#define DMA_CLOCKS \
{ \
kCLOCK_Dma \
}
/*! @brief Clock ip name array for QDEC. */
#define QDEC_CLOCKS \
{ \
kCLOCK_Qdec0, kCLOCK_Qdec1 \
}
/*! @brief Clock ip name array for DP. */
#define DP_CLOCKS \
{ \
kCLOCK_Dp \
}
/*! @brief Clock ip name array for SPIFI. */
#define SPIFI_CLOCKS \
{ \
kCLOCK_Spifi \
}
/*! @brief Clock ip name array for BLE. */
#define BLE_CLOCKS \
{ \
kCLOCK_Ble \
}
/*! @brief Clock ip name array for PROP. */
#define PROP_CLOCKS \
{ \
kCLOCK_Prop \
}
/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
/*------------------------------------------------------------------------------
clock_ip_name_t definition:
------------------------------------------------------------------------------*/
/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
typedef enum _clock_ip_name
{
kCLOCK_IpInvalid = 33U,
kCLOCK_Flexcomm0 = 0U,
kCLOCK_Flexcomm1 = 1U,
kCLOCK_Flexcomm2 = 2U,
kCLOCK_Flexcomm3 = 3U,
kCLOCK_Ctimer0 = 4U,
kCLOCK_Ctimer1 = 5U,
kCLOCK_Ctimer2 = 6U,
kCLOCK_Ctimer3 = 7U,
kCLOCK_Sct0 = 8U,
kCLOCK_Wdt = 9U,
kCLOCK_Usbd0 = 10U,
kCLOCK_Gpio = 11U,
kCLOCK_Biv = 12U,
kCLOCK_Adc = 13U,
kCLOCK_Dac = 14U,
kCLOCK_Cs = 15U,
kCLOCK_Crc = 16U,
kCLOCK_Fsp = 16U,
kCLOCK_Dma = 17U,
kCLOCK_Pint = 17U,
kCLOCK_InputMux = 17U,
kCLOCK_Qdec0 = 19U,
kCLOCK_Qdec1 = 20U,
kCLOCK_Dp = 21U,
kCLOCK_Spifi = 22U,
kCLOCK_Cal = 25U,
kCLOCK_Ble = 27U,
kCLOCK_Prop = 29U,
} clock_ip_name_t;
/*! @brief Clock name used to get clock frequency. */
typedef enum _clock_name
{
kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
kCLOCK_ApbClk, /*!< Apb clock */
kCLOCK_WdtClk, /*!< Wdt clock*/
kCLOCK_FroHf, /*!< FRO */
kCLOCK_Xin, /*!< 16/32 MHz XIN */
kCLOCK_32KClk /*!< 32K clock */
} clock_name_t;
/*! @brief Clock Mux Switches
*
* [4 bits for choice] [8 bits mux ID]
*/
#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8))
#define CM_32KCLKSEL 0
#define CM_SYSCLKSEL 1
#define CM_WDTCLKSEL 2
#define CM_BLECLKSEL 3
#define CM_XTALCLKSEL 4
typedef enum _clock_attach_id
{
kXTAL32K_to_32K_CLK = MUX_A(CM_32KCLKSEL, 0), /*!< XTAL 32K clock */
kRCO32K_to_32K_CLK = MUX_A(CM_32KCLKSEL, 1), /*!< RCO 32KHz clock */
kOSC32M_to_SYS_CLK = MUX_A(CM_SYSCLKSEL, 0), /*!< OSC 32MHz clock */
kXTAL_to_SYS_CLK = MUX_A(CM_SYSCLKSEL, 1), /*!< XTAL 16MHz/32MHz clock */
k32K_to_SYS_CLK = MUX_A(CM_SYSCLKSEL, 2), /*!< 32KHz clock */
k32K_to_WDT_CLK = MUX_A(CM_WDTCLKSEL, 0), /*!< 32KHz clock */
kAPB_to_WDT_CLK = MUX_A(CM_WDTCLKSEL, 1), /*!< APB clock */
k8M_to_BLE_CLK = MUX_A(CM_BLECLKSEL, 0), /*!< 8M CLOCK */
k16M_to_BLE_CLK = MUX_A(CM_BLECLKSEL, 1), /*!< 16M CLOCK */
k16M_to_XTAL_CLK = MUX_A(CM_XTALCLKSEL, 0), /*!< 16M XTAL */
k32M_to_XTAL_CLK = MUX_A(CM_XTALCLKSEL, 1), /*!< 32M XTAL */
kNONE_to_NONE = 0x80000000U,
} clock_attach_id_t;
/* Clock dividers */
typedef enum _clock_div_name
{
kCLOCK_DivXtalClk,
kCLOCK_DivOsc32mClk,
kCLOCK_DivAhbClk,
kCLOCK_DivApbClk,
kCLOCK_DivFrg0,
kCLOCK_DivFrg1,
kCLOCK_DivClkOut
} clock_div_name_t;
/*! @brief USB clock source definition. */
typedef enum _clock_usb_src
{
kCLOCK_UsbSrcFro =
(uint32_t)kCLOCK_FroHf, /*!< Fake USB src clock, temporary fix until USB clock control is done properly */
} clock_usb_src_t;
/* Clock clock out source */
typedef enum _clock_clkout_src
{
kCLOCK_Clkout_32K = SYSCON_CLK_CTRL_CLK_32K_OE_MASK, /*!< 32KHz clock out */
kCLOCK_Clkout_XTAL = SYSCON_CLK_CTRL_CLK_XTAL_OE_MASK /*!< XTAL clock out */
} clock_clkout_src_t;
/* Clock clock out pin */
typedef enum _clock_clkout_pin
{
kCLOCK_Clkout_PA04_32K = SYSCON_PIO_WAKEUP_EN1_PA04_32K_OE_MASK,
kCLOCK_Clkout_PA05_XTAL = SYSCON_PIO_WAKEUP_EN1_PA05_XTAL_OE_MASK,
kCLOCK_Clkout_PA10_32K = SYSCON_PIO_WAKEUP_EN1_PA10_32K_OE_MASK,
kCLOCK_Clkout_PA11_XTAL = SYSCON_PIO_WAKEUP_EN1_PA11_XTAL_OE_MASK,
kCLOCK_Clkout_PA18_32K = SYSCON_PIO_WAKEUP_EN1_PA18_32K_OE_MASK,
kCLOCK_Clkout_PA19_XTAL = SYSCON_PIO_WAKEUP_EN1_PA19_XTAL_OE_MASK,
kCLOCK_Clkout_PA24_32K = SYSCON_PIO_WAKEUP_EN1_PA24_32K_OE_MASK,
kCLOCK_Clkout_PA25_XTAL = SYSCON_PIO_WAKEUP_EN1_PA25_XTAL_OE_MASK
} clock_clkout_pin_t;
/*******************************************************************************
* API
******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/*!
* @brief Enable the specified peripheral clock
*/
void CLOCK_EnableClock(clock_ip_name_t clk);
/*!
* @brief Disable the specified peripheral clock
*/
void CLOCK_DisableClock(clock_ip_name_t clk);
/*!
* @brief Configure the clock selection muxes.
*
* @param connection: Clock to be configured.
*/
void CLOCK_AttachClk(clock_attach_id_t connection);
/*!
* @brief Setup peripheral clock dividers.
*
* @param div_name: Clock divider name
* @param divided_by_value: Value to be divided
*/
void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value);
/*!
* @brief Get frequency of selected clock
*
* @return Frequency of selected clock
*/
uint32_t CLOCK_GetFreq(clock_name_t clk);
/*!
* @brief Disable USB FS clock.
*
* Disable USB FS clock.
*/
static inline void CLOCK_DisableUsbfs0Clock(void)
{
CLOCK_DisableClock(kCLOCK_Usbd0);
}
bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
/*!
* @brief Enable/Disable clock out source.
*
* @param mask Mask value for the clock source, See "clock_clkout_src_t".
* @param enable Enable/Disable the clock out source.
*/
void CLOCK_EnableClkoutSource(uint32_t mask, bool enable);
/*!
* @brief Enable/Disable clock out pin.
*
* @param mask Mask value for the clock source, See "clock_clkout_pin_t".
* @param enable Enable/Disable the clock out pin.
*/
void CLOCK_EnableClkoutPin(uint32_t mask, bool enable);
/*! @brief Return Input frequency for the Fractional baud rate generator
* @return Input Frequency for FRG
*/
uint32_t CLOCK_GetFRGInputClock(void);
/*!
* @brief Set output of the Fractional baud rate generator
*
* @param div_name: Clock divider name: kCLOCK_DivFrg0 and kCLOCK_DivFrg1
* @param freq: Desired output frequency
* @return Error Code 0 - fail 1 - success
*/
uint32_t CLOCK_SetFRGClock(clock_div_name_t div_name, uint32_t freq);
#ifdef __cplusplus
}
#endif /* __cplusplus */
/*! @} */
#endif /* _FSL_CLOCK_H_ */

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_IOCON_H_
#define _FSL_IOCON_H_
#include "fsl_common.h"
/*!
* @addtogroup qn_iocon
* @{
*/
/*! @file */
/*******************************************************************************
* Definitions
******************************************************************************/
#define IOCON SYSCON
/*! @name Driver version */
/*@{*/
/*! @brief IOCON driver version 2.0.0. */
#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/**
* @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
*/
typedef struct _iocon_group
{
uint32_t port : 8; /* Pin port */
uint32_t pin : 8; /* Pin number */
uint32_t modefunc : 16; /* Function and mode */
} iocon_group_t;
/**
* @brief IOCON function, mode and drive selection definitions
* @note See the User Manual for specific drive levels, modes and functions supported by the various pins.
*/
#define IOCON_FUNC0 0x0U /*!< Selects pin function 0 */
#define IOCON_FUNC1 0x1U /*!< Selects pin function 1 */
#define IOCON_FUNC2 0x2U /*!< Selects pin function 2 */
#define IOCON_FUNC3 0x3U /*!< Selects pin function 3 */
#define IOCON_FUNC4 0x4U /*!< Selects pin function 4 */
#define IOCON_FUNC5 0x5U /*!< Selects pin function 5 */
#define IOCON_FUNC6 0x6U /*!< Selects pin function 6 */
#define IOCON_FUNC7 0x7U /*!< Selects pin function 7 */
#define IOCON_MODE_HIGHZ (0x0U << 4U) /*!< Selects High-Z function */
#define IOCON_MODE_PULLDOWN (0x1U << 4U) /*!< Selects pull-down function */
#define IOCON_MODE_PULLUP (0x2U << 4U) /*!< Selects pull-up function */
#define IOCON_DRIVE_LOW (0x0U << 6U) /*!< Enable low drive strength */
#define IOCON_DRIVE_HIGH (0x1U << 6U) /*!< Enable high drive strength */
#define IOCON_DRIVE_EXTRA (0x1U << 7U) /*!< Enable extra drive, only valid for PA06/PA11/PA19/PA26/PA27 */
/**
* @brief Pull mode
*/
typedef enum _iocon_pull_mode
{
kIOCON_HighZ = 0U, /*!< High Z */
kIOCON_PullDown, /*!< Pull down */
kIOCON_PullUp /*!< Pull up */
} iocon_pull_mode_t;
/**
* @brief Drive strength
*/
typedef enum _iocon_drive_strength
{
kIOCON_LowDriveStrength = 0U, /*!< Low-drive */
kIOCON_HighDriveStrength, /*!< High-drive */
kIOCON_LowDriveWithExtraStrength, /*!< Low-drive with extra */
kIOCON_HighDriveWithExtraStrength, /*!< High-drive with extra */
} iocon_drive_strength_t;
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Sets I/O control pin mux
* @param base The base of SYSCON peripheral on the chip
* @param port GPIO port to mux (value from 0 ~ 1)
* @param pin GPIO pin to mux (value from 0 ~ 31)
* @param modeFunc OR'ed values of type IOCON_*
* @return Nothing
*/
__STATIC_INLINE void IOCON_PinMuxSet(SYSCON_Type *base, uint8_t port, uint8_t pin, uint32_t modeFunc)
{
assert(((port == 0U) && (pin <= 31U)) || ((port == 1U) && (pin <= 2U)));
uint8_t pinMuxIndex = (pin >> 3U);
uint8_t pinMuxLocation = ((pin & 0x7U) << 2U);
uint8_t pinPullIndex = (pin >> 4U);
uint8_t pinPullLocation = ((pin & 0xFU) << 1U);
if (port == 0U)
{
base->PIO_FUNC_CFG[pinMuxIndex] &= ~(0x07U << pinMuxLocation);
base->PIO_FUNC_CFG[pinMuxIndex] |= (modeFunc & 0x07U) << pinMuxLocation;
pinPullIndex = (pin >> 4U);
}
else if (port == 1U)
{
pinPullIndex = 2U;
if ((pin == 0U) || (pin == 1U))
{
base->PIO_CFG_MISC &= ~(1U << pin);
base->PIO_CFG_MISC |= (modeFunc & 0x01U) << pin;
}
else if (pin == 2U)
{
base->PIO_CFG_MISC &= ~(1U << 16U);
base->PIO_CFG_MISC |= (modeFunc & 0x01U) << 16U;
}
else
{
return;
}
}
else
{
return;
}
base->PIO_PULL_CFG[pinPullIndex] &= ~(0x03U << pinPullLocation);
base->PIO_PULL_CFG[pinPullIndex] |= ((modeFunc >> 4U) & 0x03U) << pinPullLocation;
base->PIO_DRV_CFG[port] &= ~(1U << pin);
base->PIO_DRV_CFG[port] |= (((modeFunc >> 6U) & 0x01U)) << pin;
if ((port == 0U) && ((pin == 6U) || (pin == 11U) || (pin == 19U) || (pin == 26U) || (pin == 27U)))
{
base->PIO_DRV_CFG[2U] &= ~(1U << pin);
base->PIO_DRV_CFG[2U] |= (((modeFunc >> 7U) & 0x01U)) << pin;
}
}
/**
* @brief Set all I/O control pin muxing
* @param base The base of SYSCON peripheral on the chip
* @param pinArray Pointer to array of pin mux selections
* @param arrayLength Number of entries in pinArray
* @return Nothing
*/
__STATIC_INLINE void IOCON_SetPinMuxing(SYSCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
{
uint32_t i;
for (i = 0U; i < arrayLength; i++)
{
IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
}
}
/**
* @brief Sets I/O control pin function
* @param base The base of SYSCON peripheral on the chip
* @param port GPIO port (value from 0 ~ 1)
* @param pin GPIO pin (value from 0 ~ 31)
* @param func Pin fucntion (value from 0 ~ 7)
* @return Nothing
*/
__STATIC_INLINE void IOCON_FuncSet(SYSCON_Type *base, uint8_t port, uint8_t pin, uint8_t func)
{
assert(((port == 0U) && (pin <= 31U)) || ((port == 1U) && (pin <= 2U)));
uint8_t index = (pin >> 3);
uint8_t pinLocation = ((pin & 0x7U) << 2U);
if (port == 0U)
{
base->PIO_FUNC_CFG[index] &= ~(0x07U << pinLocation);
base->PIO_FUNC_CFG[index] |= (func & 0x07U) << pinLocation;
}
else if (port == 1U)
{
if ((pin == 0U) || (pin == 1U))
{
base->PIO_CFG_MISC &= ~(1U << pin);
base->PIO_CFG_MISC |= (func & 0x01U) << pin;
}
else if (pin == 2U)
{
base->PIO_CFG_MISC &= ~(1U << 16U);
base->PIO_CFG_MISC |= (func & 0x01U) << 16U;
}
else
{
return;
}
}
else
{
return;
}
}
/**
* @brief Sets I/O control drive capability
* @param base The base of SYSCON peripheral on the chip
* @param port GPIO port (value from 0 ~ 1)
* @param pin GPIO pin (value from 0 ~ 31)
* @param strength Drive strength (Extra option is only valid for PA06/PA11/PA19/PA26/PA27)
* - kIOCON_LowDriveStrength = 0U - Low-drive strength is configured.
* - kIOCON_HighDriveStrength = 1U - High-drive strength is configured
* - kIOCON_LowDriveWithExtraStrength = 2U - Low-drive with extra strength is configured
* - kIOCON_HighDriveWithExtraStrength = 3U - High-drive with extra strength is configured
* @return Nothing
*/
__STATIC_INLINE void IOCON_DriveSet(SYSCON_Type *base, uint8_t port, uint8_t pin, uint8_t strength)
{
assert(((port == 0U) && (pin <= 31U)) || ((port == 1U) && (pin <= 2U)));
base->PIO_DRV_CFG[port] &= ~(1U << pin);
base->PIO_DRV_CFG[port] |= (strength & 0x01U) << pin;
if ((port == 0U) && ((pin == 6U) || (pin == 11U) || (pin == 19U) || (pin == 26U) || (pin == 27U)))
{
base->PIO_DRV_CFG[2U] &= ~(1U << pin);
base->PIO_DRV_CFG[2U] |= (((strength >> 1U) & 0x01U)) << pin;
}
}
/**
* @brief Sets I/O control pull configuration
* @param base The base of SYSCON peripheral on the chip
* @param port GPIO port (value from 0 ~ 1)
* @param pin GPIO pin (value from 0 ~ 31)
* @param pullMode Pull mode
* - kIOCON_HighZ = 0U - High Z is configured.
* - kIOCON_PullDown = 1U - Pull-down is configured
* - kIOCON_PullUp = 2U - Pull-up is configured
* @return Nothing
*/
__STATIC_INLINE void IOCON_PullSet(SYSCON_Type *base, uint8_t port, uint8_t pin, uint8_t pullMode)
{
assert(((port == 0U) && (pin <= 31U)) || ((port == 1U) && (pin <= 2U)));
uint8_t index = (port == 1U) ? 2U : (pin >> 4U);
uint8_t pinLocation = ((pin & 0xFU) << 1U);
base->PIO_PULL_CFG[index] &= ~(0x03U << pinLocation);
base->PIO_PULL_CFG[index] |= (uint32_t)pullMode << pinLocation;
}
/* @} */
#ifdef __cplusplus
}
#endif
#endif /* _FSL_IOCON_H_ */

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/*
** ###################################################################
** Processors: QN9080C
** QN9083C
**
** Compilers: Keil ARM C/C++ Compiler
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: QN908X User manual Rev.1.0 21 Mar 2017
** Version: rev. 1.0, 2017-03-27
** Build: b170328
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2017-03-27)
** Initial version.
**
** ###################################################################
*/
/*!
* @file QN908XC
* @version 1.0
* @date 2017-03-27
* @brief Device specific configuration file for QN908XC (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef _SYSTEM_QN908XC_H_
#define _SYSTEM_QN908XC_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define CLK_XTAL_16MHZ 16000000u /* 16 MHz XTAL clock */
#define CLK_XTAL_32MHZ 32000000u /* 32 MHz XTAL clock */
#define CLK_OSC_32MHZ 32000000u /* OSC 32 MHz */
#define CLK_XTAL_32KHZ 32768u /* XTAL 32 kHz */
#define CLK_RCO_32KHZ 32000u /* RCO 32 kHz */
#define DEFAULT_SYSTEM_CLOCK 16000000u /* Default System clock value */
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_QN908XC_H_ */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016 - 2017 , NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_clock.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define getSysconClkMux() ((SYSCON->CLK_CTRL & SYSCON_CLK_CTRL_SYS_CLK_SEL_MASK) >> SYSCON_CLK_CTRL_SYS_CLK_SEL_SHIFT)
/*******************************************************************************
* Variables
******************************************************************************/
typedef union
{
struct
{
uint8_t crcClkRefCnt;
uint8_t dmaClkRefCnt;
} ref_cnt_t;
uint8_t clkRefCnt[2];
} clock_ref_cnt_t;
/** Clock reference count */
static clock_ref_cnt_t clk_ref_cnt;
/*******************************************************************************
* Code
******************************************************************************/
static void Clk32KConfig(uint8_t choice)
{
SYSCON->CLK_CTRL = (SYSCON->CLK_CTRL & ~SYSCON_CLK_CTRL_CLK_32K_SEL_MASK) | SYSCON_CLK_CTRL_CLK_32K_SEL(choice);
}
static void ClkSysConfig(uint8_t choice)
{
if (choice == 0)
{
/* RCO 32MHz ,wait for ready */
while (!(SYSCON->SYS_MODE_CTRL & SYSCON_SYS_MODE_CTRL_OSC32M_RDY_MASK))
{
}
}
/* Switch to the clock source */
SYSCON->CLK_CTRL = (SYSCON->CLK_CTRL & ~SYSCON_CLK_CTRL_SYS_CLK_SEL_MASK) | SYSCON_CLK_CTRL_SYS_CLK_SEL(choice);
}
static void ClkWdtConfig(uint8_t choice)
{
SYSCON->CLK_CTRL = (SYSCON->CLK_CTRL & ~SYSCON_CLK_CTRL_CLK_WDT_SEL_MASK) | SYSCON_CLK_CTRL_CLK_WDT_SEL(choice);
}
static void ClkBleConfig(uint8_t choice)
{
SYSCON->CLK_CTRL = (SYSCON->CLK_CTRL & ~SYSCON_CLK_CTRL_CLK_BLE_SEL_MASK) | SYSCON_CLK_CTRL_CLK_BLE_SEL(choice);
}
static void ClkXTALConfig(uint8_t choice)
{
switch (choice)
{
/* 16M XTAL */
case 0:
SYSCON->CLK_CTRL &= ~SYSCON_CLK_CTRL_CLK_XTAL_SEL_MASK;
break;
/* 32M XTAL */
case 1:
SYSCON->CLK_CTRL |= SYSCON_CLK_CTRL_CLK_XTAL_SEL_MASK;
break;
default:
break;
}
/* wait for ready */
while (!(SYSCON->SYS_MODE_CTRL & SYSCON_SYS_MODE_CTRL_XTAL_RDY_MASK))
{
}
}
void CLOCK_EnableClock(clock_ip_name_t clk)
{
uint32_t regPrimask = 0U;
if ((clk == kCLOCK_Crc) || (clk == kCLOCK_Dma))
{
regPrimask = DisableGlobalIRQ();
clk_ref_cnt.clkRefCnt[clk - kCLOCK_Crc] += 1U;
EnableGlobalIRQ(regPrimask);
}
SYSCON->CLK_EN = (1U << clk);
}
void CLOCK_DisableClock(clock_ip_name_t clk)
{
uint32_t regPrimask = 0U;
if (((clk == kCLOCK_Crc) || (clk == kCLOCK_Dma)) && (clk_ref_cnt.clkRefCnt[clk - kCLOCK_Crc] > 0))
{
regPrimask = DisableGlobalIRQ();
clk_ref_cnt.clkRefCnt[clk - kCLOCK_Crc] -= 1U;
EnableGlobalIRQ(regPrimask);
if (clk_ref_cnt.clkRefCnt[clk - kCLOCK_Crc] > 0)
{
return;
}
}
SYSCON->CLK_DIS = (1U << clk);
}
void CLOCK_AttachClk(clock_attach_id_t connection)
{
uint8_t mux, choice;
mux = (uint8_t)connection;
choice = (uint8_t)(((connection & 0xf00) >> 8) - 1);
switch (mux)
{
case CM_32KCLKSEL:
Clk32KConfig(choice);
break;
case CM_SYSCLKSEL:
ClkSysConfig(choice);
break;
case CM_WDTCLKSEL:
ClkWdtConfig(choice);
break;
case CM_BLECLKSEL:
ClkBleConfig(choice);
break;
case CM_XTALCLKSEL:
ClkXTALConfig(choice);
break;
default:
break;
}
}
void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value)
{
switch (div_name)
{
case kCLOCK_DivXtalClk:
/* F(XTAL) = F(XTAL) / (divided_by_value + 1), occupy 1 bit, take effect only when k32M_to_XTAL_CLK attached */
SYSCON->XTAL_CTRL =
(SYSCON->XTAL_CTRL & ~SYSCON_XTAL_CTRL_XTAL_DIV_MASK) | SYSCON_XTAL_CTRL_XTAL_DIV(divided_by_value);
break;
case kCLOCK_DivOsc32mClk:
/* F(OSC32M) = F(OSC32M) / (divided_by_value + 1), occupy 1 bit */
SYSCON->CLK_CTRL = (SYSCON->CLK_CTRL & ~SYSCON_CLK_CTRL_CLK_OSC32M_DIV_MASK) |
SYSCON_CLK_CTRL_CLK_OSC32M_DIV(divided_by_value);
break;
case kCLOCK_DivAhbClk:
/* F(AHB) = F(SYS) / (divided_by_value + 1), occupy 13 bits
* Note: If ble core's clock is enabled by setting SYSCON_CLK_EN_CLK_BLE_EN to 1, ahb clock can only be 8M,
* 16M or 32M.
*/
SYSCON->CLK_CTRL =
(SYSCON->CLK_CTRL & ~SYSCON_CLK_CTRL_AHB_DIV_MASK) | SYSCON_CLK_CTRL_AHB_DIV(divided_by_value);
break;
case kCLOCK_DivApbClk:
/* F(APB) = F(AHB) / (divided_by_value + 1), occupy 4 bits */
SYSCON->CLK_CTRL =
(SYSCON->CLK_CTRL & ~SYSCON_CLK_CTRL_APB_DIV_MASK) | SYSCON_CLK_CTRL_APB_DIV(divided_by_value);
break;
case kCLOCK_DivFrg0:
/* F(Flexcomm0) = F(AHB) / (1 + MULT/DIV), DIV = 0xFF */
SYSCON->FC_FRG = (SYSCON->FC_FRG & ~SYSCON_FC_FRG_FRG_MULT0_MASK) |
SYSCON_FC_FRG_FRG_MULT0(divided_by_value) | SYSCON_FC_FRG_FRG_DIV0_MASK;
break;
case kCLOCK_DivFrg1:
/* F(Flexcomm1) = F(AHB) / (1 + MULT/DIV), DIV = 0xFF */
SYSCON->FC_FRG = (SYSCON->FC_FRG & ~SYSCON_FC_FRG_FRG_MULT1_MASK) |
SYSCON_FC_FRG_FRG_MULT1(divided_by_value) | SYSCON_FC_FRG_FRG_DIV1_MASK;
break;
case kCLOCK_DivClkOut:
/* F(ClkOut) = F(XTAL) / (2 * divided_by_value), occupy 4bits, take effect only when clock out source is
* XTAL */
SYSCON->CLK_CTRL = (SYSCON->CLK_CTRL & ~SYSCON_CLK_CTRL_XTAL_OUT_DIV_MASK) |
SYSCON_CLK_CTRL_XTAL_OUT_DIV(divided_by_value);
break;
default:
break;
}
}
static uint32_t CLOCK_GetRco32MFreq(void)
{
return (SYSCON->CLK_CTRL & SYSCON_CLK_CTRL_CLK_OSC32M_DIV_MASK) ? CLK_OSC_32MHZ / 2 : CLK_OSC_32MHZ;
}
static uint32_t CLOCK_GetXinFreq(void)
{
return ((SYSCON->CLK_CTRL & SYSCON_CLK_CTRL_CLK_XTAL_SEL_MASK) &&
(!(SYSCON->XTAL_CTRL & SYSCON_XTAL_CTRL_XTAL_DIV_MASK))) ?
CLK_XTAL_32MHZ :
CLK_XTAL_16MHZ;
}
static uint32_t CLOCK_Get32KFreq(void)
{
return (SYSCON->CLK_CTRL & SYSCON_CLK_CTRL_CLK_32K_SEL_MASK) ? CLK_RCO_32KHZ : CLK_XTAL_32KHZ;
}
static uint32_t CLOCK_GetCoreSysClkFreq(void)
{
return (getSysconClkMux() == 0) ? CLOCK_GetRco32MFreq() : (getSysconClkMux() == 1) ?
CLOCK_GetXinFreq() :
(getSysconClkMux() == 2) ? CLOCK_Get32KFreq() : 0;
}
static uint32_t CLOCK_GetAhbClkFreq(void)
{
return CLOCK_GetCoreSysClkFreq() /
(((SYSCON->CLK_CTRL & SYSCON_CLK_CTRL_AHB_DIV_MASK) >> SYSCON_CLK_CTRL_AHB_DIV_SHIFT) + 1);
}
static uint32_t CLOCK_GetApbClkFreq(void)
{
return CLOCK_GetAhbClkFreq() /
(((SYSCON->CLK_CTRL & SYSCON_CLK_CTRL_APB_DIV_MASK) >> SYSCON_CLK_CTRL_APB_DIV_SHIFT) + 1);
}
static uint32_t CLOCK_GetWdtFreq(void)
{
return (SYSCON->CLK_CTRL & SYSCON_CLK_CTRL_CLK_WDT_SEL_MASK) ? CLOCK_GetApbClkFreq() : CLOCK_Get32KFreq();
}
uint32_t CLOCK_GetFreq(clock_name_t clk)
{
uint32_t freq;
switch (clk)
{
case kCLOCK_CoreSysClk:
freq = CLOCK_GetCoreSysClkFreq();
break;
case kCLOCK_BusClk:
freq = CLOCK_GetAhbClkFreq();
break;
case kCLOCK_ApbClk:
freq = CLOCK_GetApbClkFreq();
break;
case kCLOCK_WdtClk:
freq = CLOCK_GetWdtFreq();
break;
case kCLOCK_FroHf:
freq = CLOCK_GetRco32MFreq();
break;
case kCLOCK_Xin:
freq = CLOCK_GetXinFreq();
break;
case kCLOCK_32KClk:
freq = CLOCK_Get32KFreq();
break;
default:
freq = 0;
break;
}
return freq;
}
bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq)
{
CLOCK_EnableClock(kCLOCK_Usbd0);
return true;
}
void CLOCK_EnableClkoutSource(uint32_t mask, bool enable)
{
if (enable)
{
SYSCON->CLK_CTRL |= mask;
}
else
{
SYSCON->CLK_CTRL &= ~mask;
}
}
void CLOCK_EnableClkoutPin(uint32_t mask, bool enable)
{
if (enable)
{
SYSCON->PIO_WAKEUP_EN1 |= mask;
}
else
{
SYSCON->PIO_WAKEUP_EN1 &= ~mask;
}
}
uint32_t CLOCK_GetFRGInputClock(void)
{
return CLOCK_GetFreq(kCLOCK_BusClk);
}
uint32_t CLOCK_SetFRGClock(clock_div_name_t div_name, uint32_t freq)
{
uint32_t input = CLOCK_GetFRGInputClock();
uint32_t mul;
if ((freq > 32000000) || (freq > input) || (input / freq >= 2))
{
/* FRG output frequency should be less than equal to 32MHz */
return 0;
}
else
{
mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq);
if (div_name == kCLOCK_DivFrg0)
{
SYSCON->FC_FRG = (SYSCON->FC_FRG & ~SYSCON_FC_FRG_FRG_MULT0_MASK) | SYSCON_FC_FRG_FRG_MULT0(mul) |
SYSCON_FC_FRG_FRG_DIV0_MASK;
}
else if (div_name == kCLOCK_DivFrg1)
{
SYSCON->FC_FRG = (SYSCON->FC_FRG & ~SYSCON_FC_FRG_FRG_MULT1_MASK) | SYSCON_FC_FRG_FRG_MULT1(mul) |
SYSCON_FC_FRG_FRG_DIV1_MASK;
}
else
{
/* Add for avoid the misra 2004 rule 14.10 */
}
return 1;
}
}