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boards/stm32gx: move Kconfig clock config to cpu

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This commit is contained in:
Alexandre Abadie 2020-10-23 15:38:54 +02:00
parent f8c385240a
commit 7fbfb92f03
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GPG Key ID: 1C919A403CAE1405
10 changed files with 74 additions and 131 deletions
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2
boards/common/nucleo144/Kconfig
View File

@ -8,3 +8,5 @@
config BOARD_COMMON_NUCLEO144
bool
select HAS_ARDUINO
source "$(RIOTBOARD)/common/stm32/Kconfig"

2
boards/common/nucleo32/Kconfig
View File

@ -8,3 +8,5 @@
config BOARD_COMMON_NUCLEO32
bool
select HAS_ARDUINO
source "$(RIOTBOARD)/common/stm32/Kconfig"

2
boards/common/nucleo64/Kconfig
View File

@ -8,3 +8,5 @@
config BOARD_COMMON_NUCLEO64
bool
select HAS_ARDUINO
source "$(RIOTBOARD)/common/stm32/Kconfig"

115
boards/common/stm32/Kconfig.g0
View File

@ -1,115 +0,0 @@
# Copyright (c) 2020 Inria
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
menu "STM32 G0 clock configuration"
depends on CPU_FAM_G0
choice
bool "Clock source selection"
default USE_CLOCK_PLL
config USE_CLOCK_PLL
bool "PLL"
config USE_CLOCK_HSE
bool "Direct High frequency external oscillator (HSE)"
depends on BOARD_HAS_HSE
config USE_CLOCK_HSI
bool "Direct High frequency internal oscillator (HSI16)"
endchoice
config CLOCK_PLL_M
int "M: PLLIN division factor" if USE_CLOCK_PLL
default 1
range 1 8
config CLOCK_PLL_N
int "N: PLLIN multiply factor" if USE_CLOCK_PLL
default 20
range 8 86
config CLOCK_PLL_R
int "Q: VCO division factor" if USE_CLOCK_PLL
default 6 if BOARD_HAS_HSE
default 5
range 2 8
choice
bool "HSISYS division factor" if USE_CLOCK_HSI
default CLOCK_HSISYS_DIV_1
config CLOCK_HSISYS_DIV_1
bool "Divide HSISYS by 1"
config CLOCK_HSISYS_DIV_2
bool "Divide HSISYS by 2"
config CLOCK_HSISYS_DIV_4
bool "Divide HSISYS by 4"
config CLOCK_HSISYS_DIV_8
bool "Divide HSISYS by 8"
config CLOCK_HSISYS_DIV_16
bool "Divide HSISYS by 16"
config CLOCK_HSISYS_DIV_32
bool "Divide HSISYS by 32"
config CLOCK_HSISYS_DIV_64
bool "Divide HSISYS by 64"
config CLOCK_HSISYS_DIV_128
bool "Divide HSISYS by 128"
endchoice
config CLOCK_HSISYS_DIV
int
default 1
default 2 if CLOCK_HSISYS_DIV_2
default 4 if CLOCK_HSISYS_DIV_4
default 8 if CLOCK_HSISYS_DIV_8
default 16 if CLOCK_HSISYS_DIV_16
default 32 if CLOCK_HSISYS_DIV_32
default 64 if CLOCK_HSISYS_DIV_64
default 128 if CLOCK_HSISYS_DIV_128
choice
bool "APB prescaler (division factor of HCLK to produce PCLK)"
default CLOCK_APB1_DIV_1
config CLOCK_APB1_DIV_1
bool "Divide HCLK by 1"
config CLOCK_APB1_DIV_2
bool "Divide HCLK by 2"
config CLOCK_APB1_DIV_4
bool "Divide HCLK by 4"
config CLOCK_APB1_DIV_8
bool "Divide HCLK by 8"
config CLOCK_APB1_DIV_16
bool "Divide HCLK by 16"
endchoice
config CLOCK_APB1_DIV
int
default 1 if CLOCK_APB1_DIV_1
default 2 if CLOCK_APB1_DIV_2
default 4 if CLOCK_APB1_DIV_4
default 8 if CLOCK_APB1_DIV_8
default 16 if CLOCK_APB1_DIV_16
endmenu
source "$(RIOTBOARD)/common/stm32/Kconfig"

1
boards/nucleo-g070rb/Kconfig
View File

@ -26,5 +26,4 @@ config BOARD_NUCLEO_G070RB
# Clock configuration
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig.g0"
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

1
boards/nucleo-g071rb/Kconfig
View File

@ -26,5 +26,4 @@ config BOARD_NUCLEO_G071RB
# Clock configuration
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig.g0"
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

1
boards/nucleo-g431rb/Kconfig
View File

@ -30,5 +30,4 @@ config BOARD_NUCLEO_G431RB
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig.g4"
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

1
boards/nucleo-g474re/Kconfig
View File

@ -30,5 +30,4 @@ config BOARD_NUCLEO_G474RE
select BOARD_HAS_HSE
select BOARD_HAS_LSE
source "$(RIOTBOARD)/common/stm32/Kconfig.g4"
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

1
cpu/stm32/Kconfig
View File

@ -36,6 +36,7 @@ config ERROR_MODULES_CONFLICT
default "On STM32, the RTC and RTT map to the same hardware peripheral." if MODULE_PERIPH_RTC && MODULE_PERIPH_RTT
depends on CPU_STM32
orsource "kconfigs/Kconfig.clk"
orsource "kconfigs/*/Kconfig"
orsource "kconfigs/*/Kconfig.lines"
orsource "kconfigs/*/Kconfig.models"

79
boards/common/stm32/Kconfig.g4 → cpu/stm32/kconfigs/Kconfig.clk
View File

@ -5,8 +5,8 @@
# directory for more details.
#
menu "STM32 G4 clock configuration"
depends on CPU_FAM_G4
menu "STM32 clock configuration"
depends on CPU_FAM_G0 || CPU_FAM_G4
choice
bool "Clock source selection"
@ -25,16 +25,29 @@ config USE_CLOCK_HSI
endchoice
config CLOCK_PLL_M
int "M: Division factor for the main PLL input clock" if USE_CLOCK_PLL
default 6 if BOARD_HAS_HSE
default 4
range 1 16
int "M: PLLIN division factor" if USE_CLOCK_PLL
default 1 if CPU_FAM_G0
default 4 if CPU_FAM_G4
default 6 if CPU_FAM_G4 && BOARD_HAS_HSE
range 1 8 if CPU_FAM_G0
range 1 16 if CPU_FAM_G4
config CLOCK_PLL_N
int "N: Multiply factor for the VCO" if USE_CLOCK_PLL
default 40
range 8 127
int "N: PLLIN multiply factor" if USE_CLOCK_PLL
default 20 if CPU_FAM_G0
default 40 if CPU_FAM_G4
range 8 86 if CPU_FAM_G0
range 8 127 if CPU_FAM_G4
if CPU_FAM_G0
config CLOCK_PLL_R
int "Q: VCO division factor" if USE_CLOCK_PLL
default 6 if BOARD_HAS_HSE
default 5
range 2 8
endif
if CPU_FAM_G4
choice
bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if USE_CLOCK_PLL
default PLL_R_DIV_2
@ -59,6 +72,50 @@ config CLOCK_PLL_R
default 4 if PLL_R_DIV_4
default 6 if PLL_R_DIV_6
default 8 if PLL_R_DIV_8
endif
if CPU_FAM_G0
choice
bool "HSISYS division factor" if USE_CLOCK_HSI
default CLOCK_HSISYS_DIV_1
config CLOCK_HSISYS_DIV_1
bool "Divide HSISYS by 1"
config CLOCK_HSISYS_DIV_2
bool "Divide HSISYS by 2"
config CLOCK_HSISYS_DIV_4
bool "Divide HSISYS by 4"
config CLOCK_HSISYS_DIV_8
bool "Divide HSISYS by 8"
config CLOCK_HSISYS_DIV_16
bool "Divide HSISYS by 16"
config CLOCK_HSISYS_DIV_32
bool "Divide HSISYS by 32"
config CLOCK_HSISYS_DIV_64
bool "Divide HSISYS by 64"
config CLOCK_HSISYS_DIV_128
bool "Divide HSISYS by 128"
endchoice
config CLOCK_HSISYS_DIV
int
default 1 if CLOCK_HSISYS_DIV_1
default 2 if CLOCK_HSISYS_DIV_2
default 4 if CLOCK_HSISYS_DIV_4
default 8 if CLOCK_HSISYS_DIV_8
default 16 if CLOCK_HSISYS_DIV_16
default 32 if CLOCK_HSISYS_DIV_32
default 64 if CLOCK_HSISYS_DIV_64
default 128 if CLOCK_HSISYS_DIV_128
endif
choice
bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
@ -90,7 +147,7 @@ config CLOCK_APB1_DIV
default 16 if CLOCK_APB1_DIV_16
choice
bool "APB2 prescaler (division factor of HCLK to produce PCLK2)"
bool "APB2 prescaler (division factor of HCLK to produce PCLK2)" if CPU_FAM_G4
default CLOCK_APB2_DIV_1
config CLOCK_APB2_DIV_1
@ -119,5 +176,3 @@ config CLOCK_APB2_DIV
default 16 if CLOCK_APB2_DIV_16
endmenu
source "$(RIOTBOARD)/common/stm32/Kconfig"