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cpu: boards: stm32g4: improve clock configuration
This commit is contained in:
parent
a7f9b4d793
commit
a1038aa70e
@ -35,41 +35,100 @@ extern "C" {
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* @{
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*/
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/* Select the desired system clock source between PLL, HSE or HSI */
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#define CLOCK_USE_HSI (0)
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#define CLOCK_USE_HSE (0)
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#define CLOCK_USE_PLL (1)
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#ifndef CONFIG_USE_CLOCK_PLL
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#define CONFIG_USE_CLOCK_PLL (0)
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#else
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#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#ifndef CONFIG_USE_CLOCK_HSE
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#define CONFIG_USE_CLOCK_HSE (0)
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#endif /* CONFIG_USE_CLOCK_HSE */
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#ifndef CONFIG_USE_CLOCK_HSI
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#define CONFIG_USE_CLOCK_HSI (0)
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#endif /* CONFIG_USE_CLOCK_HSI */
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#if CONFIG_USE_CLOCK_PLL && \
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(CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use PLL as clock source with other clock configurations"
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#endif
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#if CONFIG_USE_CLOCK_HSE && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use HSE as clock source with other clock configurations"
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#endif
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#if CONFIG_USE_CLOCK_HSI && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE)
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#error "Cannot use HSI as clock source with other clock configurations"
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#endif
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE (0)
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#endif
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#define CLOCK_HSI (16000000U)
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#ifndef CLOCK_HSE
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#define CLOCK_HSE (0)
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#define CLOCK_HSE MHZ(24)
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#endif
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (1U)
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#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
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#error "HSE clock frequency must be between 4MHz and 48MHz"
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#endif
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#if CLOCK_USE_HSI
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#define CLOCK_CORECLOCK (CLOCK_HSI)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE (0)
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#endif
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#if CONFIG_BOARD_HAS_LSE
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#define CLOCK_LSE (1)
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#else
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#define CLOCK_LSE (0)
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#endif
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#elif CLOCK_USE_HSE
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#define CLOCK_HSI MHZ(16)
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#elif CLOCK_USE_PLL
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#if CONFIG_USE_CLOCK_HSI
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#ifndef CONFIG_CLOCK_HSISYS_DIV
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#define CONFIG_CLOCK_HSISYS_DIV (1)
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#endif
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#define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV)
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#elif CONFIG_USE_CLOCK_HSE
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#if CONFIG_BOARD_HAS_HSE == 0
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#error "The board doesn't provide an HSE oscillator"
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#endif
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#elif CONFIG_USE_CLOCK_PLL
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/* The following parameters configure a 64MHz system clock with HSI as input clock */
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#define CLOCK_PLL_M (1)
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#define CLOCK_PLL_N (20)
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#define CLOCK_PLL_R (5)
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#if CLOCK_HSE
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#else /* CLOCK_HSI */
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#ifndef CONFIG_CLOCK_PLL_M
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#define CONFIG_CLOCK_PLL_M (1)
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#endif
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#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_R
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#endif /* CLOCK_USE_PLL */
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#ifndef CONFIG_CLOCK_PLL_N
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#define CONFIG_CLOCK_PLL_N (20)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (5)
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#endif
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#if CONFIG_BOARD_HAS_HSE
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#else /* CLOCK_HSI */
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#endif
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#define CLOCK_CORECLOCK \
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((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
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#if CLOCK_CORECLOCK > MHZ(64)
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#error "SYSCLK cannot exceed 64MHz"
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_0
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1) /* max: 64MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE_0
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) /* max: 64MHz */
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#define CLOCK_AHB CLOCK_CORECLOCK /* max: 64MHz */
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (1)
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#endif
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#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz */
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/** @} */
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#ifdef __cplusplus
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@ -29,44 +29,100 @@ extern "C" {
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* @name Clock settings
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* @{
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*/
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#define CLOCK_USE_HSI (0)
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#define CLOCK_USE_HSE (0)
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#define CLOCK_USE_PLL (1)
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#ifndef CONFIG_USE_CLOCK_PLL
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#define CONFIG_USE_CLOCK_PLL (0)
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#else
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#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_HSI (16000000U)
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#ifndef CONFIG_USE_CLOCK_HSE
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#define CONFIG_USE_CLOCK_HSE (0)
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#endif /* CONFIG_USE_CLOCK_HSE */
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#ifndef CONFIG_USE_CLOCK_HSI
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#define CONFIG_USE_CLOCK_HSI (0)
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#endif /* CONFIG_USE_CLOCK_HSI */
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#if CONFIG_USE_CLOCK_PLL && \
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(CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use PLL as clock source with other clock configurations"
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#endif
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#if CONFIG_USE_CLOCK_HSE && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use HSE as clock source with other clock configurations"
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#endif
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#if CONFIG_USE_CLOCK_HSI && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE)
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#error "Cannot use HSI as clock source with other clock configurations"
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#endif
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE (0)
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#endif
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#ifndef CLOCK_HSE
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#define CLOCK_HSE (24000000U)
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#define CLOCK_HSE MHZ(24)
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#endif
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (1U)
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#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
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#error "HSE clock frequency must be between 4MHz and 48MHz"
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#endif
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#if CLOCK_USE_HSI
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#define CLOCK_CORECLOCK (CLOCK_HSI)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE (0)
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#endif
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#if CONFIG_BOARD_HAS_LSE
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#define CLOCK_LSE (1)
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#else
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#define CLOCK_LSE (0)
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#endif
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#elif CLOCK_USE_HSE
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#define CLOCK_HSI MHZ(16)
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#elif CLOCK_USE_PLL
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/* The following parameters configure a 170MHz system clock with HSE as input clock */
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (85)
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#define CLOCK_PLL_R (2)
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#if CLOCK_HSE
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#if CONFIG_USE_CLOCK_HSI
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#define CLOCK_CORECLOCK (CLOCK_HSI)
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#elif CONFIG_USE_CLOCK_HSE
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#if CONFIG_BOARD_HAS_HSE == 0
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#error "The board doesn't provide an HSE oscillator"
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#endif
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#elif CONFIG_USE_CLOCK_PLL
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/* The following parameters configure a 170MHz system clock with HSI16 as input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#define CONFIG_CLOCK_PLL_M (4)
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#define CONFIG_CLOCK_PLL_N (85)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (2)
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#endif
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#if CONFIG_BOARD_HAS_HSE
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#else /* CLOCK_HSI */
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#endif
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#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_R
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#define CLOCK_CORECLOCK \
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((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
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#if CLOCK_CORECLOCK > MHZ(170)
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#error "SYSCLK cannot exceed 170MHz"
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1) /* max 170MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) /* max 170MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) /* max 170MHz */
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/** @} */
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#define CLOCK_AHB CLOCK_CORECLOCK /* max: 170MHz */
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (1)
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#endif
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#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 170MHz */
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (1)
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#endif
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#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz */
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#ifdef __cplusplus
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}
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@ -20,6 +20,12 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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/* Add specific clock configuration (HSE, LSE) for this board here */
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE (1)
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#endif
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#include "g0/cfg_clock_default.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_rtt_default.h"
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@ -19,6 +19,19 @@
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* Add specific clock configuration (HSE, LSE) for this board here */
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE (1)
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#endif
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/* This board provides a 24MHz HSE oscillator */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE (1)
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#endif
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/* By default, configure a 80MHz SYSCLK with PLL using HSE as input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#define CONFIG_CLOCK_PLL_M (6)
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#endif
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#include "periph_cpu.h"
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#include "g4/cfg_clock_default.h"
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#include "cfg_i2c1_pb8_pb9.h"
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@ -21,10 +21,6 @@
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#include "stmclk.h"
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#include "periph_conf.h"
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#if CLOCK_USE_HSE && CLOCK_HSE == 0
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#error "HSE is selected as input clock source but CLOCK_HSE is not set"
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#endif
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#if defined(CPU_FAM_STM32G0)
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#define PLL_M_MIN (1)
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#define PLL_M_MAX (8)
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@ -41,28 +37,28 @@
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#define PLL_R_MAX (8)
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#endif
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#if CLOCK_USE_PLL
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#if (CLOCK_PLL_M < PLL_M_MIN || CLOCK_PLL_M > PLL_M_MAX)
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#if CONFIG_USE_CLOCK_PLL
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#if (CONFIG_CLOCK_PLL_M < PLL_M_MIN || CONFIG_CLOCK_PLL_M > PLL_M_MAX)
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#error "PLL configuration: PLL M value is out of range"
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#endif
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#define PLL_M ((CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
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#define PLL_M ((CONFIG_CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
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#if (CLOCK_PLL_N < PLL_N_MIN || CLOCK_PLL_N > PLL_N_MAX)
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#if (CONFIG_CLOCK_PLL_N < PLL_N_MIN || CONFIG_CLOCK_PLL_N > PLL_N_MAX)
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#error "PLL configuration: PLL N value is out of range"
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#endif
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#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#define PLL_N (CONFIG_CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#if (CLOCK_PLL_R < PLL_R_MIN || CLOCK_PLL_R > PLL_R_MAX)
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#if (CONFIG_CLOCK_PLL_R < PLL_R_MIN || CONFIG_CLOCK_PLL_R > PLL_R_MAX)
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#error "PLL configuration: PLL R value is out of range"
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#endif
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#if defined(CPU_FAM_STM32G0)
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#define PLL_R ((CLOCK_PLL_R - 1) << RCC_PLLCFGR_PLLR_Pos)
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#define PLL_R ((CONFIG_CLOCK_PLL_R - 1) << RCC_PLLCFGR_PLLR_Pos)
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#else /* CPU_FAM_STM32G4 */
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#define PLL_R (((CLOCK_PLL_R >> 1) - 1) << RCC_PLLCFGR_PLLR_Pos)
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#define PLL_R (((CONFIG_CLOCK_PLL_R >> 1) - 1) << RCC_PLLCFGR_PLLR_Pos)
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#endif
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#if CLOCK_HSE
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#if CONFIG_BOARD_HAS_HSE
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#define PLL_IN CLOCK_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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@ -70,13 +66,75 @@
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
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#endif
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#endif /* CLOCK_USE_PLL */
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#endif /* CONFIG_USE_CLOCK_PLL */
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#if defined(CPU_FAM_STM32G0)
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#define RCC_CFGR_SW_HSI (0)
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#define RCC_CFGR_SW_HSE (RCC_CFGR_SW_0)
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#define RCC_CFGR_SW_PLL (RCC_CFGR_SW_1)
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#if CONFIG_USE_CLOCK_HSI
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#if CONFIG_CLOCK_HSISYS_DIV == 1
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#define CLOCK_HSI_DIV (0)
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#elif CONFIG_CLOCK_HSISYS_DIV == 2
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_0)
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#elif CONFIG_CLOCK_HSISYS_DIV == 4
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_1)
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#elif CONFIG_CLOCK_HSISYS_DIV == 8
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)
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#elif CONFIG_CLOCK_HSISYS_DIV == 16
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2)
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#elif CONFIG_CLOCK_HSISYS_DIV == 32
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0)
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#elif CONFIG_CLOCK_HSISYS_DIV == 64
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1)
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#elif CONFIG_CLOCK_HSISYS_DIV == 128
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)
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#endif
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#endif /* CONFIG_USE_CLOCK_HSI */
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#define CLOCK_AHB_DIV (0)
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (0)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_2)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0)
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#endif
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#endif /* CPU_FAM_STM32G0 */
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#if defined(CPU_FAM_STM32G4)
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#define CLOCK_AHB_DIV (RCC_CFGR_HPRE_DIV1)
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV2)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV4)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV8)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV16)
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#endif
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#if CONFIG_CLOCK_APB2_DIV == 1
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1)
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#elif CONFIG_CLOCK_APB2_DIV == 2
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV2)
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#elif CONFIG_CLOCK_APB2_DIV == 4
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV4)
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#elif CONFIG_CLOCK_APB2_DIV == 8
|
||||
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV8)
|
||||
#elif CONFIG_CLOCK_APB2_DIV == 16
|
||||
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV16)
|
||||
#endif
|
||||
#endif /* CPU_FAM_STM32G4 */
|
||||
|
||||
/** Determine the required flash wait states from the core clock frequency */
|
||||
#if defined(CPU_FAM_STM32G0)
|
||||
@ -137,15 +195,25 @@ void stmclk_init_sysclk(void)
|
||||
stmclk_enable_lfclk();
|
||||
#endif
|
||||
|
||||
#if CLOCK_USE_HSE
|
||||
#if CONFIG_USE_CLOCK_HSI && defined(CPU_FAM_STM32G0)
|
||||
/* configure HSISYS divider, only available on G0 */
|
||||
RCC->CR |= CLOCK_HSI_DIV;
|
||||
while (!(RCC->CR & RCC_CR_HSIRDY)) {}
|
||||
|
||||
#elif CONFIG_USE_CLOCK_HSE
|
||||
/* if configured, we need to enable the HSE clock now */
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
|
||||
#if defined(CPU_FAM_STM32G0)
|
||||
RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV);
|
||||
#elif defined(CPU_FAM_STM32G4)
|
||||
RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
||||
#endif
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
|
||||
#elif CLOCK_USE_PLL
|
||||
#if CLOCK_HSE
|
||||
|
||||
#elif CONFIG_USE_CLOCK_PLL
|
||||
#if CONFIG_BOARD_HAS_HSE
|
||||
/* if configured, we need to enable the HSE clock now */
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user