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cpu/stm32: move clock configuration headers to cpu

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This commit is contained in:
Alexandre Abadie 2020-10-21 19:20:57 +02:00
parent b14e7544aa
commit f2e2c89424
No known key found for this signature in database
GPG Key ID: 1C919A403CAE1405
14 changed files with 55 additions and 52 deletions
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3
cpu/stm32/Makefile.include
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@ -84,4 +84,7 @@ $(STM32IRQS_INCLUDE_FILE): $(STM32FAM_INCLUDE_FILE)
$(Q)$(RIOTBASE)/cpu/stm32/dist/irqs/gen_irqs.py $(CPU_FAM)
endif
# Include clock configuration directory
INCLUDES += -I$(RIOTCPU)/stm32/include/clk
include $(RIOTMAKE)/arch/cortexm.inc.mk

8
boards/common/stm32/include/f0/cfg_clock_default.h → cpu/stm32/include/clk/f0/cfg_clock_default.h
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@ -7,7 +7,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -18,8 +18,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F0_CFG_CLOCK_DEFAULT_H
#define F0_CFG_CLOCK_DEFAULT_H
#ifndef CLK_F0_CFG_CLOCK_DEFAULT_H
#define CLK_F0_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
@ -134,5 +134,5 @@ extern "C" {
}
#endif
#endif /* F0_CFG_CLOCK_DEFAULT_H */
#endif /* CLK_F0_CFG_CLOCK_DEFAULT_H */
/** @} */

8
boards/common/stm32/include/f1f3/cfg_clock_default.h → cpu/stm32/include/clk/f1f3/cfg_clock_default.h
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -23,8 +23,8 @@
*
*/
#ifndef F1F3_CFG_CLOCK_DEFAULT_H
#define F1F3_CFG_CLOCK_DEFAULT_H
#ifndef CLK_F1F3_CFG_CLOCK_DEFAULT_H
#define CLK_F1F3_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
@ -144,5 +144,5 @@ extern "C" {
}
#endif
#endif /* F1F3_CFG_CLOCK_DEFAULT_H */
#endif /* CLK_F1F3_CFG_CLOCK_DEFAULT_H */
/** @} */

8
boards/common/stm32/include/f2f4f7/cfg_clock_common.h → cpu/stm32/include/clk/f2f4f7/cfg_clock_common.h
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -20,8 +20,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_COMMON_H
#define F2F4F7_CFG_CLOCK_COMMON_H
#ifndef CLK_F2F4F7_CFG_CLOCK_COMMON_H
#define CLK_F2F4F7_CFG_CLOCK_COMMON_H
#ifdef __cplusplus
extern "C" {
@ -81,5 +81,5 @@ extern "C" {
}
#endif
#endif /* F2F4F7_CFG_CLOCK_COMMON_H */
#endif /* CLK_F2F4F7_CFG_CLOCK_COMMON_H */
/** @} */

8
boards/common/stm32/include/f2f4f7/cfg_clock_default_100.h → cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -20,8 +20,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_100_H
#define F2F4F7_CFG_CLOCK_DEFAULT_100_H
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H
#include "f2f4f7/cfg_clock_common.h"
@ -96,5 +96,5 @@ extern "C" {
#error "SYSCLK cannot exceed 100MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_100_H */
#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H */
/** @} */

8
boards/common/stm32/include/f2f4f7/cfg_clock_default_120.h → cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -20,8 +20,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_120_H
#define F2F4F7_CFG_CLOCK_DEFAULT_120_H
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H
#include "f2f4f7/cfg_clock_common.h"
@ -74,5 +74,5 @@ extern "C" {
#error "SYSCLK cannot exceed 120MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_120_H */
#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H */
/** @} */

8
boards/common/stm32/include/f2f4f7/cfg_clock_default_180.h → cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -20,8 +20,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_180_H
#define F2F4F7_CFG_CLOCK_DEFAULT_180_H
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
#include "f2f4f7/cfg_clock_common.h"
@ -108,5 +108,5 @@ extern "C" {
#error "SYSCLK cannot exceed 180MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_180_H */
#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H */
/** @} */

8
boards/common/stm32/include/f2f4f7/cfg_clock_default_216.h → cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -20,8 +20,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_216_H
#define F2F4F7_CFG_CLOCK_DEFAULT_216_H
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
#include "f2f4f7/cfg_clock_common.h"
@ -83,5 +83,5 @@ extern "C" {
#error "SYSCLK cannot exceed 216MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_216_H */
#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H */
/** @} */

8
boards/common/stm32/include/f2f4f7/cfg_clock_default_84.h → cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -20,8 +20,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_84_H
#define F2F4F7_CFG_CLOCK_DEFAULT_84_H
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
#include "f2f4f7/cfg_clock_common.h"
@ -77,5 +77,5 @@ extern "C" {
#error "SYSCLK cannot exceed 84MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_84_H */
#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H */
/** @} */

8
boards/common/stm32/include/f2f4f7/cfg_clock_values.h → cpu/stm32/include/clk/f2f4f7/cfg_clock_values.h
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -20,8 +20,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_VALUES_H
#define F2F4F7_CFG_CLOCK_VALUES_H
#ifndef CLK_F2F4F7_CFG_CLOCK_VALUES_H
#define CLK_F2F4F7_CFG_CLOCK_VALUES_H
#ifdef __cplusplus
extern "C" {
@ -62,5 +62,5 @@ extern "C" {
}
#endif
#endif /* F2F4F7_CFG_CLOCK_VALUES_H */
#endif /* CLK_F2F4F7_CFG_CLOCK_VALUES_H */
/** @} */

8
boards/common/stm32/include/g0/cfg_clock_default.h → cpu/stm32/include/clk/g0/cfg_clock_default.h
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@ -7,7 +7,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -20,8 +20,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef G0_CFG_CLOCK_DEFAULT_H
#define G0_CFG_CLOCK_DEFAULT_H
#ifndef CLK_G0_CFG_CLOCK_DEFAULT_H
#define CLK_G0_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
@ -133,5 +133,5 @@ extern "C" {
}
#endif
#endif /* G0_CFG_CLOCK_DEFAULT_H */
#endif /* CLK_G0_CFG_CLOCK_DEFAULT_H */
/** @} */

8
boards/common/stm32/include/g4/cfg_clock_default.h → cpu/stm32/include/clk/g4/cfg_clock_default.h
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@ -7,7 +7,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -16,8 +16,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef G4_CFG_CLOCK_DEFAULT_H
#define G4_CFG_CLOCK_DEFAULT_H
#ifndef CLK_G4_CFG_CLOCK_DEFAULT_H
#define CLK_G4_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
@ -125,5 +125,5 @@ extern "C" {
}
#endif
#endif /* G4_CFG_CLOCK_DEFAULT_H */
#endif /* CLK_G4_CFG_CLOCK_DEFAULT_H */
/** @} */

8
boards/common/stm32/include/l0l1/cfg_clock_default.h → cpu/stm32/include/clk/l0l1/cfg_clock_default.h
View File

@ -7,7 +7,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -16,8 +16,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef L0L1_CFG_CLOCK_DEFAULT_H
#define L0L1_CFG_CLOCK_DEFAULT_H
#ifndef CLK_L0L1_CFG_CLOCK_DEFAULT_H
#define CLK_L0L1_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
@ -156,5 +156,5 @@ extern "C" {
}
#endif
#endif /* L0L1_CFG_CLOCK_DEFAULT_H */
#endif /* CLK_L0L1_CFG_CLOCK_DEFAULT_H */
/** @} */

8
boards/common/stm32/include/l4/cfg_clock_default.h → cpu/stm32/include/clk/l4/cfg_clock_default.h
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@ -8,7 +8,7 @@
*/
/**
* @ingroup boards_common_stm32
* @ingroup cpu_stm32
* @{
*
* @file
@ -18,8 +18,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef L4_CFG_CLOCK_DEFAULT_H
#define L4_CFG_CLOCK_DEFAULT_H
#ifndef CLK_L4_CFG_CLOCK_DEFAULT_H
#define CLK_L4_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
@ -202,5 +202,5 @@ extern "C" {
}
#endif
#endif /* L4_CFG_CLOCK_DEFAULT_H */
#endif /* CLK_L4_CFG_CLOCK_DEFAULT_H */
/** @} */