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Merge pull request #14923 from aabadie/pr/boards/stm32f0f1f3_clock_kconfig
boards/stm32f1/f3: rework clock initialization and configuration
This commit is contained in:
Francisco
GitHub
commit
109012b194
@ -25,7 +25,14 @@
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#define PERIPH_CONF_H
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/* blxxxpill boards provide an LSE */
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#define CLOCK_LSE (1)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* blxxxpill boards provide an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -21,13 +21,15 @@
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#define PERIPH_CONF_COMMON_H
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/* iotlab boards provide an LSE */
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#define CLOCK_LSE (1)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* HSE is clocked at 16MHz */
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#define CLOCK_HSE MHZ(16)
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/* Adjust PLL predevider to reach 72MHz sysclock */
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#define CLOCK_PLL_PREDIV (2)
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#define CLOCK_HSE MHZ(16)
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -36,40 +36,113 @@ extern "C" {
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* @name Clock settings
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#ifndef CLOCK_HSE
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#define CLOCK_HSE MHZ(8)
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#endif
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 72MHz when input clock is HSE, 64MHz when input clock is HSI */
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#if CLOCK_HSE
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#define CLOCK_CORECLOCK MHZ(72)
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/* Select the desired system clock source between PLL, HSE or HSI */
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#ifndef CONFIG_USE_CLOCK_PLL
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#define CONFIG_USE_CLOCK_PLL 0
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#else
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#define CLOCK_CORECLOCK MHZ(64)
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#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#ifndef CONFIG_USE_CLOCK_HSE
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#define CONFIG_USE_CLOCK_HSE 0
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#endif /* CONFIG_USE_CLOCK_HSE */
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#ifndef CONFIG_USE_CLOCK_HSI
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#define CONFIG_USE_CLOCK_HSI 0
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#endif /* CONFIG_USE_CLOCK_HSI */
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#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
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(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
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#error "Cannot use PLL as clock source with other clock configurations"
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#endif
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (0)
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
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(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
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#error "Cannot use HSE as clock source with other clock configurations"
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#endif
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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/* PLL factors */
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#ifndef CLOCK_PLL_PREDIV
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#define CLOCK_PLL_PREDIV (1)
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
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(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
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#error "Cannot use HSI as clock source with other clock configurations"
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#endif
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#ifndef CLOCK_PLL_MUL
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#define CLOCK_PLL_MUL (9)
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 0
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#endif
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#ifndef CLOCK_HSE
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#define CLOCK_HSE MHZ(8)
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#endif
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(32))
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#error "HSE clock frequency must be between 4MHz and 32MHz"
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#endif
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 0
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#endif
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#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
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#define CLOCK_LSE (1)
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#else
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#define CLOCK_LSE (0)
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#endif
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#define CLOCK_HSI MHZ(8)
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/* The following parameters configure a 72MHz system clock with HSE (8MHz or
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16MHz) and HSI (8MHz) as input clock */
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#ifndef CONFIG_CLOCK_PLL_PREDIV
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(16))
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#define CONFIG_CLOCK_PLL_PREDIV (2)
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#else
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#define CONFIG_CLOCK_PLL_PREDIV (1)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_MUL
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#define CONFIG_CLOCK_PLL_MUL (9)
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#endif
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#define CLOCK_CORECLOCK (CLOCK_HSI)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
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#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#error "The board doesn't provide an HSE oscillator"
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#endif
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#else /* CLOCK_HSI */
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#endif
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL)
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* with:
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* PLL_IN: input clock is HSE if available or HSI otherwise
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* PLL_PREDIV : pre-divider, allowed range: [1:16]
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* PLL_MUL: multiplier, allowed range: [2:16]
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* CORECLOCK -> 72MHz MAX!
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*/
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#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_PREDIV) * CONFIG_CLOCK_PLL_MUL)
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#if CLOCK_CORECLOCK > MHZ(72)
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#error "SYSCLK cannot exceed 72MHz"
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 72MHz */
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (2)
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#endif
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#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 36MHz */
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (1)
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#endif
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#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK2, max: 72MHz */
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/** @} */
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#ifdef __cplusplus
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@ -19,14 +19,16 @@
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* iotlab boards provide an LSE */
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#define CLOCK_LSE (1)
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/* This board provides an LSE */
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* HSE is clocked at 16MHz */
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#define CLOCK_HSE MHZ(16)
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/* Adjust PLL predevider to reach 72MHz sysclock */
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#define CLOCK_PLL_PREDIV (2)
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#define CLOCK_HSE MHZ(16)
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -20,7 +20,14 @@
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#define PERIPH_CONF_H
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/* This board provides an LSE */
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#define CLOCK_LSE (1)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -24,7 +24,14 @@
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#define PERIPH_CONF_H
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/* This board provides an LSE */
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#define CLOCK_LSE (1)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -19,12 +19,14 @@
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* No HSE available for this board */
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#define CLOCK_HSE (0U)
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/* Adjust PLL prescalers to reach 72MHz sysclock */
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#define CLOCK_PLL_PREDIV (2)
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#define CLOCK_PLL_MUL (16)
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/* Adjust PLL factors:
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- On nucleo-f303k8, there's no HSE and PREDIV is hard-wired to 2
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- to reach the maximum possible system clock (64MHz) set PLL_MUL to 16
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so system clock = (HSI8 / 2) * 16 = 64MHz */
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#define CONFIG_CLOCK_PLL_PREDIV (2)
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#ifndef CONFIG_CLOCK_PLL_MUL
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#define CONFIG_CLOCK_PLL_MUL (16)
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#endif
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -22,7 +22,14 @@
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#define PERIPH_CONF_H
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/* This board provides an LSE */
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#define CLOCK_LSE (1)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -20,7 +20,14 @@
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#define PERIPH_CONF_H
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/* This board provides an LSE */
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#define CLOCK_LSE (1)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -21,7 +21,14 @@
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#define PERIPH_CONF_H
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/* This board provides an LSE */
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#define CLOCK_LSE (1)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -20,7 +20,14 @@
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#define PERIPH_CONF_H
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/* This board provides an LSE */
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#define CLOCK_LSE (1)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -19,6 +19,11 @@
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -19,6 +19,11 @@
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "f1f3/cfg_clock_default.h"
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@ -2,10 +2,10 @@ MODULE = stm32_clk
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SRC = stmclk_common.c
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ifneq (,$(filter-out f0,$(filter f%,$(CPU_FAM))))
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SRC += stmclk_fx.c
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else ifneq (,$(filter $(CPU_FAM),f0))
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SRC += stmclk_f0.c
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ifneq (,$(filter $(CPU_FAM),f2 f4 f7))
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SRC += stmclk_f2f4f7.c
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else ifneq (,$(filter $(CPU_FAM),f0 f1 f3))
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SRC += stmclk_f0f1f3.c
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else ifneq (,$(filter $(CPU_FAM),l0 l1))
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SRC += stmclk_l0l1.c
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else ifneq (,$(filter $(CPU_FAM),l4 wb))
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@ -13,7 +13,7 @@
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration for STM32 F0
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* @brief Implementation of STM32 clock configuration for STM32 F0/F1/F3
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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@ -26,17 +26,32 @@
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#include "periph_conf.h"
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/* PLL configuration */
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#if defined(CPU_FAM_STM32F1)
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define PLL_SRC (RCC_CFGR_PLLSRC) /* HSE */
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#else
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#define PLL_SRC (0) /* HSI / 2 */
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#endif
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/* RCC_CR_HSITRIM_4 is not defined on stm32f1 and corresponds to a value of 16.
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Use the same definition used for stm32f0/stm32f3 */
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#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
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#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMULL
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#define PLL_MUL ((CONFIG_CLOCK_PLL_MUL - 2) << RCC_CFGR_PLLMULL_Pos)
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#else /* CPU_FAM_STM32F0 && CPU_FAM_STM32F3 */
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#if CONFIG_BOARD_HAS_HSE
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#define PLL_SRC (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1)
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#else
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#define PLL_SRC (RCC_CFGR_PLLSRC_HSI_DIV2)
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#endif
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#define PLL_MUL ((CONFIG_CLOCK_PLL_MUL - 2) << RCC_CFGR_PLLMUL_Pos)
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#endif /* CPU_FAM_STM32F1 */
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#define PLL_PREDIV (CONFIG_CLOCK_PLL_PREDIV - 1)
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#define CLOCK_AHB_DIV (RCC_CFGR_HPRE_DIV1)
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#if defined(CPU_FAM_STM32F0)
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_DIV1)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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@ -50,7 +65,69 @@
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#else
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#error "Invalid APB prescaler value (only 1, 2, 4, 8 and 16 allowed)"
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#endif
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#else
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV2)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV4)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV8)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV16)
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#else
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#error "Invalid APB1 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
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#endif
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#if CONFIG_CLOCK_APB2_DIV == 1
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1)
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#elif CONFIG_CLOCK_APB2_DIV == 2
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV2)
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#elif CONFIG_CLOCK_APB2_DIV == 4
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV4)
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#elif CONFIG_CLOCK_APB2_DIV == 8
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV8)
|
||||
#elif CONFIG_CLOCK_APB2_DIV == 16
|
||||
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV16)
|
||||
#else
|
||||
#error "Invalid APB2 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Check whether PLL is required */
|
||||
/* Check whether PLL must be enabled:
|
||||
- When PLLCLK is used as SYSCLK
|
||||
*/
|
||||
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
|
||||
#define CLOCK_ENABLE_PLL 1
|
||||
#else
|
||||
#define CLOCK_ENABLE_PLL 0
|
||||
#endif
|
||||
|
||||
/* Check whether HSE is required:
|
||||
- When HSE is used as SYSCLK
|
||||
- When PLL is used as SYSCLK and the board provides HSE (since HSE will be
|
||||
used as PLL input clock)
|
||||
*/
|
||||
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
|
||||
(IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL))
|
||||
#define CLOCK_ENABLE_HSE 1
|
||||
#else
|
||||
#define CLOCK_ENABLE_HSE 0
|
||||
#endif
|
||||
|
||||
/* Check whether HSI is required:
|
||||
- When HSI is used as SYSCLK
|
||||
- When PLL is used as SYSCLK and the board doesn't provide HSE (since HSI will be
|
||||
used as PLL input clock)
|
||||
*/
|
||||
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
|
||||
(!IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL))
|
||||
#define CLOCK_ENABLE_HSI 1
|
||||
#else
|
||||
#define CLOCK_ENABLE_HSI 0
|
||||
#endif
|
||||
|
||||
/* Deduct the needed flash wait states from the core clock frequency */
|
||||
#define FLASH_WAITSTATES ((CLOCK_CORECLOCK - 1) / MHZ(24))
|
||||
@ -71,7 +148,11 @@ void stmclk_init_sysclk(void)
|
||||
|
||||
/* use HSI as system clock while we do any further configuration and
|
||||
* configure the AHB and APB clock dividers as configure by the board */
|
||||
#if defined(CPU_FAM_STM32F0)
|
||||
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV);
|
||||
#else /* CPU_FAM_STM32F1 && CPU_FAM_STM32F3 */
|
||||
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
||||
#endif /* CPU_FAM_STM32F0*/
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
|
||||
|
||||
/* Flash config */
|
||||
@ -80,39 +161,40 @@ void stmclk_init_sysclk(void)
|
||||
/* disable all active clocks except HSI -> resets the clk configuration */
|
||||
RCC->CR = (RCC_CR_HSION | RCC_CR_HSITRIM_4);
|
||||
|
||||
/* HSE is only used if provided by board and core clock input is using HSE
|
||||
or PLL */
|
||||
if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && !IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) {
|
||||
/* Enable HSE if it's used */
|
||||
if (IS_ACTIVE(CLOCK_ENABLE_HSE)) {
|
||||
RCC->CR |= (RCC_CR_HSEON);
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
}
|
||||
|
||||
if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
|
||||
RCC->CFGR |= RCC_CFGR_SW_HSE;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
|
||||
}
|
||||
else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
|
||||
/* now the PLL can safely be configured and started */
|
||||
/* reset PLL configuration bits */
|
||||
/* Enable PLL if it's used */
|
||||
if (IS_ACTIVE(CLOCK_ENABLE_PLL)) {
|
||||
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL);
|
||||
/* set PLL configuration */
|
||||
RCC->CFGR |= (PLL_SRC | PLL_MUL);
|
||||
if (CONFIG_CLOCK_PLL_PREDIV == 2) {
|
||||
RCC->CFGR |= RCC_CFGR_PLLXTPRE; /* PREDIV == 2 */
|
||||
}
|
||||
#if !defined(CPU_FAM_STM32F1)
|
||||
else if (CONFIG_CLOCK_PLL_PREDIV > 2) {
|
||||
RCC->CFGR2 = PLL_PREDIV; /* PREDIV > 2 */
|
||||
}
|
||||
#endif
|
||||
RCC->CR |= (RCC_CR_PLLON);
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
||||
}
|
||||
|
||||
/* now that the PLL is running, use it as system clock */
|
||||
/* Configure SYSCLK */
|
||||
if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
|
||||
RCC->CFGR |= RCC_CFGR_SW_HSE;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
|
||||
}
|
||||
else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
|
||||
}
|
||||
|
||||
if (!IS_ACTIVE(CONFIG_USE_CLOCK_HSI) ||
|
||||
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && IS_ACTIVE(CONFIG_BOARD_HAS_HSE))) {
|
||||
if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
|
||||
/* Disable HSI only if not used */
|
||||
stmclk_disable_hsi();
|
||||
}
|
||||
@ -38,8 +38,6 @@
|
||||
* @name PLL configuration
|
||||
* @{
|
||||
*/
|
||||
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
|
||||
defined(CPU_FAM_STM32F7)
|
||||
/* figure out which input to use */
|
||||
#if (CLOCK_HSE)
|
||||
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
|
||||
@ -111,55 +109,19 @@
|
||||
#else
|
||||
#define PLL_R (0)
|
||||
#endif
|
||||
|
||||
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
|
||||
#if (CLOCK_HSE)
|
||||
#define PLL_SRC (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1)
|
||||
#else
|
||||
#define PLL_SRC (RCC_CFGR_PLLSRC_HSI_DIV2)
|
||||
#endif
|
||||
|
||||
#define PLL_MUL ((CLOCK_PLL_MUL - 2) << 18)
|
||||
#define PLL_PREDIV (CLOCK_PLL_PREDIV - 1)
|
||||
|
||||
#if defined(CPU_FAM_STM32F0)
|
||||
#define CLOCK_APB2_DIV (0)
|
||||
#endif
|
||||
|
||||
#elif defined(CPU_FAM_STM32F1)
|
||||
#if CLOCK_HSE
|
||||
#define PLL_SRC (RCC_CFGR_PLLSRC) /* HSE */
|
||||
#else
|
||||
#define PLL_SRC (0) /* HSI / 2 */
|
||||
#endif
|
||||
|
||||
#define PLL_MUL ((CLOCK_PLL_MUL - 2) << 18)
|
||||
#define PLL_PREDIV (CLOCK_PLL_PREDIV - 1)
|
||||
|
||||
#define RCC_CR_HSITRIM_4 (1 << 7)
|
||||
#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMULL
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Deduct the needed flash wait states from the core clock frequency
|
||||
* @{
|
||||
*/
|
||||
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
|
||||
defined(CPU_FAM_STM32F3)
|
||||
#define FLASH_WAITSTATES ((CLOCK_CORECLOCK - 1) / 24000000U)
|
||||
#else
|
||||
#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
|
||||
#endif
|
||||
/* we enable I+D cashes, pre-fetch, and we set the actual number of
|
||||
* needed flash wait states */
|
||||
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
|
||||
#define FLASH_ACR_CONFIG (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
|
||||
#elif defined(CPU_FAM_STM32F7)
|
||||
#define FLASH_ACR_CONFIG (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
|
||||
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
|
||||
defined(CPU_FAM_STM32F3)
|
||||
#define FLASH_ACR_CONFIG (FLASH_ACR_PRFTBE | FLASH_WAITSTATES)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
@ -208,23 +170,7 @@ void stmclk_init_sysclk(void)
|
||||
RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
|
||||
#endif
|
||||
/* now we can safely configure and start the PLL */
|
||||
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
|
||||
defined(CPU_FAM_STM32F7)
|
||||
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q | PLL_R);
|
||||
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
|
||||
defined(CPU_FAM_STM32F3)
|
||||
/* reset PLL configuration bits */
|
||||
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL);
|
||||
/* set PLL configuration */
|
||||
RCC->CFGR |= PLL_SRC | PLL_MUL;
|
||||
#if CLOCK_PLL_PREDIV == 2
|
||||
RCC->CFGR |= RCC_CFGR_PLLXTPRE; /* PREDIV == 2 */
|
||||
#elif CLOCK_PLL_PREDIV > 2
|
||||
RCC->CFGR2 = PLL_PREDIV; /* PREDIV > 2 */
|
||||
#elif CLOCK_PLL_PREDIV == 0
|
||||
#error "CLOCK_PLL_PREDIV invalid"
|
||||
#endif
|
||||
#endif
|
||||
RCC->CR |= (RCC_CR_PLLON);
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user