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nrf5x: Adapt to flashpage/flashpage_pagewise API

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This commit is contained in:
Koen Zandberg 2020-11-09 16:44:21 +01:00
parent f85594eb55
commit e176649266
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GPG Key ID: 0895A893E6D2985B
5 changed files with 33 additions and 38 deletions
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4
cpu/nrf51/include/cpu_conf.h
View File

@ -52,9 +52,9 @@ extern "C" {
/* The minimum block size which can be written is 4B. However, the erase
* block is always FLASHPAGE_SIZE.
*/
#define FLASHPAGE_RAW_BLOCKSIZE (4U)
#define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
/* Writing should be always 4 bytes aligned */
#define FLASHPAGE_RAW_ALIGNMENT (4U)
#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
/** @} */
/**

4
cpu/nrf52/include/cpu_conf.h
View File

@ -107,9 +107,9 @@ extern "C" {
/* The minimum block size which can be written is 4B. However, the erase
* block is always FLASHPAGE_SIZE.
*/
#define FLASHPAGE_RAW_BLOCKSIZE (4U)
#define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
/* Writing should be always 4 bytes aligned */
#define FLASHPAGE_RAW_ALIGNMENT (4U)
#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
/** @} */
#ifdef CPU_MODEL_NRF52840XXAA

2
cpu/nrf5x_common/Kconfig
View File

@ -8,7 +8,7 @@ config CPU_COMMON_NRF5X
bool
select HAS_PERIPH_CPUID
select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW
select HAS_PERIPH_FLASHPAGE_PAGEWISE
select HAS_PERIPH_GPIO
select HAS_PERIPH_GPIO_IRQ
select HAS_PERIPH_HWRNG

2
cpu/nrf5x_common/Makefile.features
View File

@ -1,7 +1,7 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw
FEATURES_PROVIDED += periph_flashpage_pagewise
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_temperature

59
cpu/nrf5x_common/periph/flashpage.c
View File

@ -23,33 +23,7 @@
#include "assert.h"
#include "periph/flashpage.h"
void flashpage_write_raw(void *target_addr, const void *data, size_t len)
{
/* assert multiples of FLASHPAGE_RAW_BLOCKSIZE are written and no less of
that length. */
assert(!(len % FLASHPAGE_RAW_BLOCKSIZE));
/* ensure writes are aligned */
assert(!(((unsigned)target_addr % FLASHPAGE_RAW_ALIGNMENT) ||
((unsigned)data % FLASHPAGE_RAW_ALIGNMENT)));
/* ensure the length doesn't exceed the actual flash size */
assert(((unsigned)target_addr + len) <
(CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)) + 1);
uint32_t *page_addr = target_addr;
const uint32_t *data_addr = data;
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
for (unsigned i = 0; i < (len / FLASHPAGE_RAW_BLOCKSIZE); i++) {
*page_addr++ = data_addr[i];
}
/* finish up */
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
}
void flashpage_write(int page, const void *data)
void flashpage_erase(unsigned page)
{
assert(page < (int)FLASHPAGE_NUMOF);
@ -59,9 +33,30 @@ void flashpage_write(int page, const void *data)
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
NRF_NVMC->ERASEPAGE = (uint32_t)page_addr;
while (NRF_NVMC->READY == 0) {}
/* write data to page */
if (data != NULL) {
flashpage_write_raw(page_addr, data, FLASHPAGE_SIZE);
}
}
void flashpage_write(void *target_addr, const void *data, size_t len)
{
/* assert multiples of FLASHPAGE_WRITE_BLOCK_SIZE are written and no less of
that length. */
assert(!(len % FLASHPAGE_WRITE_BLOCK_SIZE));
/* ensure writes are aligned */
assert(!(((unsigned)target_addr % FLASHPAGE_WRITE_BLOCK_ALIGNMENT) ||
((unsigned)data % FLASHPAGE_WRITE_BLOCK_ALIGNMENT)));
/* ensure the length doesn't exceed the actual flash size */
assert(((unsigned)target_addr + len) <
(CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)) + 1);
uint32_t *page_addr = target_addr;
const uint32_t *data_addr = data;
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
for (unsigned i = 0; i < (len / FLASHPAGE_WRITE_BLOCK_SIZE); i++) {
*page_addr++ = data_addr[i];
}
/* finish up */
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
}