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cpu/saml21: define CPU_COMMON_SAML21 symbol and use it

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This commit is contained in:
Benjamin Valentin 2020-08-21 12:48:35 +02:00
parent e32b0783c4
commit 5d96151775
5 changed files with 13 additions and 11 deletions
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14
cpu/sam0_common/include/periph_cpu_common.h
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@ -637,11 +637,11 @@ static inline void sercom_clk_en(void *sercom)
if (id < 5) {
MCLK->APBCMASK.reg |= (MCLK_APBCMASK_SERCOM0 << id);
}
#if defined(CPU_FAM_SAML21)
#if defined(CPU_COMMON_SAML21)
else {
MCLK->APBDMASK.reg |= (MCLK_APBDMASK_SERCOM5);
}
#endif /* CPU_FAM_SAML21 */
#endif /* CPU_COMMON_SAML21 */
#endif
}
@ -667,11 +667,11 @@ static inline void sercom_clk_dis(void *sercom)
if (id < 5) {
MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << id);
}
#if defined (CPU_FAM_SAML21)
#if defined (CPU_COMMON_SAML21)
else {
MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_SERCOM5);
}
#endif /* CPU_FAM_SAML21 */
#endif /* CPU_COMMON_SAML21 */
#endif
}
@ -706,11 +706,11 @@ static inline void sercom_set_gen(void *sercom, uint8_t gclk)
if (id < 5) {
GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + id].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
}
#if defined(CPU_FAM_SAML21)
#if defined(CPU_COMMON_SAML21)
else {
GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
}
#endif /* CPU_FAM_SAML21 */
#endif /* CPU_COMMON_SAML21 */
#endif
}
@ -821,7 +821,7 @@ typedef struct {
/**
* @brief Move the DMA descriptors to the LP SRAM. Required on the SAML21
*/
#if defined(CPU_FAM_SAML21) || defined(DOXYGEN)
#if defined(CPU_COMMON_SAML21) || defined(DOXYGEN)
#define DMA_DESCRIPTOR_IN_LPSRAM
#endif

2
cpu/sam0_common/periph/flashpage.c
View File

@ -139,7 +139,7 @@ static void _erase_page(void* page, void (*cmd_erase)(void))
/* ADDR drives the hardware (16-bit) address to the NVM when a command is executed using CMDEX.
* 8-bit addresses must be shifted one bit to the right before writing to this register.
*/
#if defined(CPU_COMMON_SAMD21) || defined(CPU_SAML21)
#if defined(CPU_COMMON_SAMD21) || defined(CPU_COMMON_SAML21)
page_addr >>= 1;
#endif

4
cpu/sam0_common/periph/gpio.c
View File

@ -219,7 +219,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
| GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN(CONFIG_SAM0_GCLK_GPIO);
while (GCLK->STATUS.bit.SYNCBUSY) {}
#else /* CPU_FAM_SAML21 */
#else /* CPU_COMMON_SAML21 */
/* enable clocks for the EIC module */
MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(CONFIG_SAM0_GCLK_GPIO);
@ -247,7 +247,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
/* enable the EIC module*/
_EIC->CTRL.reg = EIC_CTRL_ENABLE;
EIC_SYNC();
#else /* CPU_FAM_SAML21 */
#else /* CPU_COMMON_SAML21 */
/* enable the EIC module*/
_EIC->CTRLA.reg = EIC_CTRLA_ENABLE;
EIC_SYNC();

2
cpu/sam0_common/periph/i2c.c
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@ -45,7 +45,7 @@
#define BUSSTATE_OWNER SERCOM_I2CM_STATUS_BUSSTATE(2)
#define BUSSTATE_BUSY SERCOM_I2CM_STATUS_BUSSTATE(3)
#if defined(CPU_SAML21) || defined(CPU_SAML1X) || defined(CPU_SAMD5X)
#if defined(CPU_COMMON_SAML21) || defined(CPU_SAML1X) || defined(CPU_SAMD5X)
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER SERCOM_I2CM_CTRLA_MODE(5)
#endif

2
cpu/saml21/Makefile.include
View File

@ -11,6 +11,8 @@ ifneq (,$(filter samr34%,$(CPU_MODEL)))
CFLAGS += -DCPU_SAMR34
endif
CFLAGS += -DCPU_COMMON_SAML21
ifneq (,$(filter saml21j18b saml21j18a samr30g18a samr34j18b,$(CPU_MODEL)))
BACKUP_RAM_ADDR = 0x30000000
BACKUP_RAM_LEN = 0x2000