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cpu/stm32/rtt: adapt for stm32g0

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This commit is contained in:
Alexandre Abadie 2020-07-21 20:30:51 +02:00
parent 25e1fec90c
commit 84f1a70b7f
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GPG Key ID: 1C919A403CAE1405
1 changed files with 16 additions and 1 deletions
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17
cpu/stm32/periph/rtt_all.c
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@ -77,10 +77,13 @@ register. */
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#define IMR_REG IMR2
#define EXTI_IMR_BIT EXTI_IMR2_IM32
#elif defined(CPU_FAM_STM32G0)
#define IMR_REG IMR1
#define EXTI_IMR_BIT EXTI_IMR1_IM29
#elif defined(CPU_FAM_STM32G4)
#define IMR_REG IMR2
#define EXTI_IMR_BIT EXTI_IMR2_IM37
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
#elif defined(CPU_FAM_STM32L0)
#define IMR_REG IMR
#define EXTI_IMR_BIT EXTI_IMR_IM29
#else
@ -128,7 +131,11 @@ void rtt_init(void)
EXTI->RTSR_REG |= EXTI_RTSR_BIT;
EXTI->PR_REG = EXTI_PR_BIT;
#endif
#if defined(CPU_FAM_STM32G0)
NVIC_EnableIRQ(TIM6_DAC_LPTIM1_IRQn);
#else
NVIC_EnableIRQ(LPTIM1_IRQn);
#endif
/* enable timer */
LPTIM1->CR = LPTIM_CR_ENABLE;
/* set auto-reload value (timer needs to be enabled for this) */
@ -185,6 +192,8 @@ void rtt_poweron(void)
{
#ifdef RCC_APB1ENR1_LPTIM1EN
periph_clk_en(APB1, RCC_APB1ENR1_LPTIM1EN);
#elif defined(RCC_APBENR1_LPTIM1EN)
periph_clk_en(APB1, RCC_APBENR1_LPTIM1EN);
#else
periph_clk_en(APB1, RCC_APB1ENR_LPTIM1EN);
#endif
@ -194,12 +203,18 @@ void rtt_poweroff(void)
{
#ifdef RCC_APB1ENR1_LPTIM1EN
periph_clk_dis(APB1, RCC_APB1ENR1_LPTIM1EN);
#elif defined(RCC_APBENR1_LPTIM1EN)
periph_clk_dis(APB1, RCC_APBENR1_LPTIM1EN);
#else
periph_clk_dis(APB1, RCC_APB1ENR_LPTIM1EN);
#endif
}
#if defined(CPU_FAM_STM32G0)
void isr_tim6_dac_lptim1(void)
#else
void isr_lptim1(void)
#endif
{
if (LPTIM1->ISR & LPTIM_ISR_CMPM) {
if (to_cb) {