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boards: cpu: stm32l0: rework clock configuration
This commit is contained in:
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4a5d9a30b1
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23117a844e
@ -29,27 +29,122 @@ extern "C" {
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSI (16000000U) /* internal oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (1) /* enable low speed external oscillator */
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/* Select the desired system clock source between PLL, HSE or HSI */
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#ifndef CONFIG_USE_CLOCK_PLL
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
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IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
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#define CONFIG_USE_CLOCK_PLL (0)
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#else
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#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#ifndef CONFIG_USE_CLOCK_MSI
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#define CONFIG_USE_CLOCK_MSI (0)
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#endif /* CONFIG_USE_CLOCK_MSI */
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#ifndef CONFIG_USE_CLOCK_HSE
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#define CONFIG_USE_CLOCK_HSE (0)
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#endif /* CONFIG_USE_CLOCK_HSE */
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#ifndef CONFIG_USE_CLOCK_HSI
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#define CONFIG_USE_CLOCK_HSI (0)
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#endif /* CONFIG_USE_CLOCK_HSI */
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#if CONFIG_USE_CLOCK_PLL && \
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(CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use PLL as clock source with other clock configurations"
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#endif
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
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#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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#if CONFIG_USE_CLOCK_MSI && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use MSI as clock source with other clock configurations"
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#endif
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
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#if CONFIG_USE_CLOCK_HSE && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use HSE as clock source with other clock configurations"
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#endif
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#if CONFIG_USE_CLOCK_HSI && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE)
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#error "Cannot use HSI as clock source with other clock configurations"
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#endif
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE (0)
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#endif
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#ifndef CLOCK_HSE
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#define CLOCK_HSE MHZ(24)
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#endif
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#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24))
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#error "HSE clock frequency must be between 1MHz and 24MHz"
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#endif
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#ifndef CONFIG_CLOCK_HSI_USE_DIV4
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#define CONFIG_CLOCK_HSI_USE_DIV4 (0)
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#endif
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE (1)
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#endif
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#if CONFIG_BOARD_HAS_LSE
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#define CLOCK_LSE (1)
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#else
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#define CLOCK_LSE (0)
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#endif
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#define CLOCK_HSI MHZ(16)
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#if CONFIG_USE_CLOCK_HSI
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#define CLOCK_CORECLOCK (CLOCK_HSI)
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#elif CONFIG_USE_CLOCK_HSE
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#if CONFIG_BOARD_HAS_HSE == 0
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#error "The board doesn't provide an HSE oscillator"
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#endif
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#elif CONFIG_USE_CLOCK_MSI
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#ifndef CONFIG_CLOCK_MSI
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#define CONFIG_CLOCK_MSI KHZ(4194)
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#endif
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
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#elif CONFIG_USE_CLOCK_PLL
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/* The following parameters configure a 64MHz system clock with HSI as input clock */
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#ifndef CONFIG_CLOCK_PLL_DIV
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#define CONFIG_CLOCK_PLL_DIV (2)
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#endif
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#ifndef CONFIG_CLOCK_PLL_MUL
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#define CONFIG_CLOCK_PLL_MUL (4)
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#endif
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#if CONFIG_BOARD_HAS_HSE
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#if CLOCK_HSE < MHZ(2)
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#error "HSE must be greater than 2MHz when used as PLL input clock"
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#endif
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#else /* CLOCK_HSI */
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#endif
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#endif /* CONFIG_BOARD_HAS_HSE */
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#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL)
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#if CLOCK_CORECLOCK > MHZ(32)
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#error "SYSCLK cannot exceed 32MHz"
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB CLOCK_CORECLOCK /* max: 32MHz */
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (1)
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#endif
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#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 32MHz */
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (1)
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#endif
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#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */
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/** @} */
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#ifdef __cplusplus
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@ -29,28 +29,121 @@ extern "C" {
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSI (16000000U) /* internal oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
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/* Select the desired system clock source between PLL, HSE or HSI */
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#ifndef CONFIG_USE_CLOCK_PLL
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
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IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
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#define CONFIG_USE_CLOCK_PLL (0)
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#else
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#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (0) /* disable low speed external oscillator */
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#ifndef CONFIG_USE_CLOCK_MSI
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#define CONFIG_USE_CLOCK_MSI (0)
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#endif /* CONFIG_USE_CLOCK_MSI */
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#ifndef CONFIG_USE_CLOCK_HSE
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#define CONFIG_USE_CLOCK_HSE (0)
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#endif /* CONFIG_USE_CLOCK_HSE */
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#ifndef CONFIG_USE_CLOCK_HSI
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#define CONFIG_USE_CLOCK_HSI (0)
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#endif /* CONFIG_USE_CLOCK_HSI */
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#if CONFIG_USE_CLOCK_PLL && \
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(CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use PLL as clock source with other clock configurations"
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#endif
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
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#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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#if CONFIG_USE_CLOCK_MSI && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use MSI as clock source with other clock configurations"
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#endif
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
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#if CONFIG_USE_CLOCK_HSE && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use HSE as clock source with other clock configurations"
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#endif
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#if CONFIG_USE_CLOCK_HSI && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE)
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#error "Cannot use HSI as clock source with other clock configurations"
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#endif
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE (0)
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#endif
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#ifndef CLOCK_HSE
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#define CLOCK_HSE MHZ(24)
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#endif
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#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24))
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#error "HSE clock frequency must be between 1MHz and 24MHz"
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#endif
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#ifndef CONFIG_CLOCK_HSI_USE_DIV4
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#define CONFIG_CLOCK_HSI_USE_DIV4 (0)
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#endif
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE (0)
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#endif
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#if CONFIG_BOARD_HAS_LSE
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#define CLOCK_LSE (1)
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#else
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#define CLOCK_LSE (0)
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#endif
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#define CLOCK_HSI MHZ(16)
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#if CONFIG_USE_CLOCK_HSI
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#define CLOCK_CORECLOCK (CLOCK_HSI)
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#elif CONFIG_USE_CLOCK_HSE
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#if CONFIG_BOARD_HAS_HSE == 0
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#error "The board doesn't provide an HSE oscillator"
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#endif
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#elif CONFIG_USE_CLOCK_MSI
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#ifndef CONFIG_CLOCK_MSI
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#define CONFIG_CLOCK_MSI KHZ(4194)
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#endif
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
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#elif CONFIG_USE_CLOCK_PLL
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/* The following parameters configure a 64MHz system clock with HSI as input clock */
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#ifndef CONFIG_CLOCK_PLL_DIV
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#define CONFIG_CLOCK_PLL_DIV (2)
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#endif
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#ifndef CONFIG_CLOCK_PLL_MUL
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#define CONFIG_CLOCK_PLL_MUL (4)
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#endif
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#if CONFIG_BOARD_HAS_HSE
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#if CLOCK_HSE < MHZ(2)
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#error "HSE must be greater than 2MHz when used as PLL input clock"
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#endif
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#else /* CLOCK_HSI */
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#endif /* CONFIG_BOARD_HAS_HSE */
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#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL)
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#if CLOCK_CORECLOCK > MHZ(32)
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#error "SYSCLK cannot exceed 32MHz"
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB CLOCK_CORECLOCK /* max: 32MHz */
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (1)
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#endif
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#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 32MHz */
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (1)
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#endif
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#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */
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/** @} */
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#ifdef __cplusplus
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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* 2017 Inria
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* 2017-2020 Inria
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* 2018 Kaspar Schleiser <kaspar@schleiser.de>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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@ -22,67 +22,127 @@
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*/
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#include "cpu.h"
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#include "board.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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#if defined(CPU_FAM_STM32L1)
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#define REG_CIR (RCC->CIR)
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#else /* CPU_FAM_STM32L0 */
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#define REG_CIR (RCC->CICR)
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#endif
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY (FLASH_ACR_LATENCY)
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/* Configure the prescalers */
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#define CLOCK_AHB_DIV (RCC_CFGR_HPRE_DIV1) /* HCLK = SYSCLK */
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV2)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV4)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV8)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV16)
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#endif
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#if CONFIG_CLOCK_APB2_DIV == 1
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1)
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#elif CONFIG_CLOCK_APB2_DIV == 2
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV2)
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#elif CONFIG_CLOCK_APB2_DIV == 4
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV4)
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#elif CONFIG_CLOCK_APB2_DIV == 8
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV8)
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#elif CONFIG_CLOCK_APB2_DIV == 16
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV16)
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#endif
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/* Check the source to be used for the PLL */
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#if defined(CLOCK_HSI) && defined(CLOCK_HSE)
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#error "Only provide one of two CLOCK_HSI/CLOCK_HSE"
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#elif CLOCK_HSI
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#define CLOCK_CR_SOURCE RCC_CR_HSION
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#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY
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#define CLOCK_PLL_SOURCE RCC_CFGR_PLLSRC_HSI
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#elif CLOCK_HSE
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#define CLOCK_CR_SOURCE RCC_CR_HSEON
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#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY
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#define CLOCK_PLL_SOURCE RCC_CFGR_PLLSRC_HSE
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#if CONFIG_BOARD_HAS_HSE
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#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSE)
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#else /* Use HSI as PLL input */
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#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI)
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#endif
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#if CONFIG_CLOCK_PLL_DIV == 2
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#define CLOCK_PLL_DIV (RCC_CFGR_PLLDIV2)
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#elif CONFIG_CLOCK_PLL_DIV == 3
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#define CLOCK_PLL_DIV (RCC_CFGR_PLLDIV3)
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#elif CONFIG_CLOCK_PLL_DIV == 4
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#define CLOCK_PLL_DIV (RCC_CFGR_PLLDIV4)
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#else
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#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h"
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#error "Invalid PLL DIV value, only 2, 3, and 4 values are allowed."
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#endif
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#if CONFIG_CLOCK_PLL_MUL == 3
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#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL3)
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#elif CONFIG_CLOCK_PLL_MUL == 4
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#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL4)
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#elif CONFIG_CLOCK_PLL_MUL == 6
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#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL6)
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#elif CONFIG_CLOCK_PLL_MUL == 8
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#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL8)
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#elif CONFIG_CLOCK_PLL_MUL == 12
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#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL12)
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#elif CONFIG_CLOCK_PLL_MUL == 16
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#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL16)
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#elif CONFIG_CLOCK_PLL_MUL == 24
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#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL24)
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#elif CONFIG_CLOCK_PLL_MUL == 32
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#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL32)
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#elif CONFIG_CLOCK_PLL_MUL == 48
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#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL48)
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#else
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#error "Invalid PLL MUL value, only 3, 4, 6, 8, 12, 16, 24, 32 and 48 values are allowed."
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#endif
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#if CONFIG_CLOCK_MSI == 65536UL
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#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_0)
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#elif CONFIG_CLOCK_MSI == 131072UL
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#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_1)
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#elif CONFIG_CLOCK_MSI == 262144UL
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#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_2)
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#elif CONFIG_CLOCK_MSI == 524288UL
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#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_3)
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#elif CONFIG_CLOCK_MSI == KHZ(1048)
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#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_4)
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#elif CONFIG_CLOCK_MSI == KHZ(2097)
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#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_5)
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#elif CONFIG_CLOCK_MSI == KHZ(4194)
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#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_6)
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#else
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#error "Invalid MSI clock value"
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#endif
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/**
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* @brief Configure the controllers clock system
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*
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* The clock initialization make the following assumptions:
|
||||
* - the external HSE clock from an external oscillator is used as base clock
|
||||
* - the internal PLL circuit is used for clock refinement
|
||||
*
|
||||
* Use the following formulas to calculate the needed values:
|
||||
*
|
||||
* SYSCLK = ((HSE_VALUE / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_P
|
||||
* USB, SDIO and RNG Clock = ((HSE_VALUE / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_Q
|
||||
*
|
||||
* The actual used values are specified in the board's `periph_conf.h` file.
|
||||
*
|
||||
* NOTE: currently there is not timeout for initialization of PLL and other locks
|
||||
* NOTE: currently there is no timeout for initialization of PLL and other locks
|
||||
* -> when wrong values are chosen, the initialization could stall
|
||||
*/
|
||||
void stmclk_init_sysclk(void)
|
||||
{
|
||||
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
/* Reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE bits */
|
||||
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL);
|
||||
/* Reset HSION, HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON);
|
||||
/* disable any interrupts. Global interrupts could be enabled if this is
|
||||
* called from some kind of bootloader... */
|
||||
unsigned is = irq_disable();
|
||||
/* Disable all interrupts */
|
||||
REG_CIR = 0x0;
|
||||
|
||||
#if defined(CPU_FAM_STM32L0)
|
||||
RCC->CICR = 0x0;
|
||||
#elif defined(CPU_FAM_STM32L1)
|
||||
RCC->CIR = 0x0;
|
||||
#else
|
||||
#error unexpected MCU
|
||||
#endif
|
||||
/* enable HSI clock for the duration of initialization */
|
||||
stmclk_enable_hsi();
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
|
||||
/* Reset MSION, HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= ~(RCC_CR_MSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON);
|
||||
|
||||
/* use HSI as system clock while we do any further configuration and
|
||||
* configure the AHB and APB clock dividers as configured by the board */
|
||||
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
||||
|
||||
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
|
||||
/* Enable high speed clock source */
|
||||
RCC->CR |= CLOCK_CR_SOURCE;
|
||||
/* Wait till the high speed clock source is ready
|
||||
* NOTE: the MCU will stay here forever if you use an external clock source and it's not connected */
|
||||
while (!(RCC->CR & CLOCK_CR_SOURCE_RDY)) {}
|
||||
#if defined(CPU_FAM_STM32L1)
|
||||
FLASH->ACR |= FLASH_ACR_ACC64;
|
||||
#endif
|
||||
@ -94,22 +154,53 @@ void stmclk_init_sysclk(void)
|
||||
PWR->CR = PWR_CR_VOS_0;
|
||||
/* Wait Until the Voltage Regulator is ready */
|
||||
while((PWR->CSR & PWR_CSR_VOSF) != 0) {}
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV;
|
||||
/* PLL configuration: PLLCLK = CLOCK_SOURCE / PLL_DIV * PLL_MUL */
|
||||
RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL));
|
||||
RCC->CFGR |= (uint32_t)(CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | CLOCK_PLL_MUL);
|
||||
/* Enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while ((RCC->CR & RCC_CR_PLLRDY) == 0) {}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
|
||||
|
||||
if (CONFIG_USE_CLOCK_HSE) {
|
||||
/* Enable the HSE clock now */
|
||||
RCC->CR |= (RCC_CR_HSEON);
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
|
||||
/* Select HSE as system clock and configure the different prescalers */
|
||||
RCC->CFGR &= ~(RCC_CFGR_SW);
|
||||
RCC->CFGR |= RCC_CFGR_SW_HSE;
|
||||
}
|
||||
else if (CONFIG_USE_CLOCK_MSI) {
|
||||
/* Configure MSI range and enable it */
|
||||
RCC->ICSCR |= CLOCK_MSIRANGE;
|
||||
RCC->CR |= (RCC_CR_MSION);
|
||||
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
|
||||
|
||||
/* Select MSI as system clock and configure the different prescalers */
|
||||
RCC->CFGR &= ~(RCC_CFGR_SW);
|
||||
RCC->CFGR |= RCC_CFGR_SW_MSI;
|
||||
}
|
||||
else if (CONFIG_USE_CLOCK_PLL) {
|
||||
if (CONFIG_BOARD_HAS_HSE) {
|
||||
/* if configured, we need to enable the HSE clock now */
|
||||
RCC->CR |= (RCC_CR_HSEON);
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
}
|
||||
|
||||
/* Configure PLL clock source and configure the different prescalers */
|
||||
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL);
|
||||
RCC->CFGR |= (CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | CLOCK_PLL_MUL);
|
||||
/* Enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW));
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
|
||||
}
|
||||
|
||||
if (!IS_ACTIVE(CONFIG_USE_CLOCK_HSI) ||
|
||||
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && IS_ACTIVE(CONFIG_BOARD_HAS_HSE))) {
|
||||
/* Disable HSI only if not used */
|
||||
stmclk_disable_hsi();
|
||||
}
|
||||
|
||||
irq_restore(is);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user