mirror of
https://github.com/RIOT-OS/RIOT.git
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cpu/cc2538: cleanup init, add cc2538_rf_obs_sig module
This commit is contained in:
Francisco Molina
parent
145d24499d
commit
e2c57cde95
@ -77,6 +77,15 @@
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#define RF24_SWITCH_AT86RF215_TOGGLE (RF_SWITCH_PORT->DATA ^= RF24_SWITCH_AT86RF215_MASK)
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/** @} */
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/**
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* @name RF CORE observable signals settings
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* @{
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*/
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#define CONFIG_CC2538_RF_OBS_SIG_0_PCX 5 /* PC5 */
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#define CONFIG_CC2538_RF_OBS_SIG_1_PCX 6 /* PC6 */
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#define CONFIG_CC2538_RF_OBS_SIG_2_PCX 7 /* PC7 */
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/** @} */
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/**
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* @name AT86RF215 configuration
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* @{
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@ -81,6 +81,15 @@
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#define CCA_BACKDOOR_ACTIVE_LEVEL (0) /**< Active low */
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/** @} */
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/**
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* @name RF CORE observable signals settings
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* @{
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*/
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#define CONFIG_CC2538_RF_OBS_SIG_0_PCX 5 /* PC5 */
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#define CONFIG_CC2538_RF_OBS_SIG_1_PCX 6 /* PC6 */
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#define CONFIG_CC2538_RF_OBS_SIG_2_PCX 7 /* PC7 */
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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@ -24,6 +24,8 @@
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#include <stdbool.h>
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#include "board.h"
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#include "net/ieee802154.h"
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#include "kernel_defines.h"
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@ -153,6 +155,15 @@ enum {
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/*
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* @brief RFCORE_XREG_FRMCTRL0 bits
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*/
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enum {
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SET_RXENMASK_ON_TX = BIT(0),
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IGNORE_TX_UNDERF = BIT(1),
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PENDING_OR = BIT(2),
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};
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/*
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* @brief RFCORE_XREG_FRMCTRL1 bits
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*/
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enum {
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ENERGY_SCAN = BIT(4),
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AUTOACK = BIT(5),
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@ -187,7 +198,6 @@ enum {
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};
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/* Values for use with CCTEST_OBSSELx registers: */
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#define OBSSEL_EN BIT(7)
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enum {
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rfc_obs_sig0 = 0,
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rfc_obs_sig1 = 1,
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@ -196,27 +206,83 @@ enum {
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/* Values for RFCORE_XREG_RFC_OBS_CTRLx registers: */
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enum {
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constant_value_0 = 0x00,
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constant_value_1 = 0x01,
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rfc_sniff_data = 0x08,
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rfc_sniff_clk = 0x09,
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rssi_valid = 0x0c,
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demod_cca = 0x0d,
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sampled_cca = 0x0e,
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sfd_sync = 0x0f,
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tx_active = 0x10,
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rx_active = 0x11,
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ffctrl_fifo = 0x12,
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ffctrl_fifop = 0x13,
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packet_done = 0x14,
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rfc_xor_rand_i_q = 0x16,
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rfc_rand_q = 0x17,
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rfc_rand_i = 0x18,
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lock_status = 0x19,
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pa_pd = 0x20,
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lna_pd = 0x2a,
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constant_value_0 = 0x00, /**< Constant value 0 */
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constant_value_1 = 0x01, /**< Constant value 1*/
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rfc_sniff_data = 0x08, /**< Data from packet sniffer. Sample data
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on rising edges of sniff_clk.*/
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rfc_sniff_clk = 0x09, /**< 250kHz clock for packet sniffer data.*/
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rssi_valid = 0x0c, /**< Pin is high when the RSSI value has
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been updated at least once since RX was
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started. Cleared when leaving RX.*/
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demod_cca = 0x0d, /**< Clear channel assessment. See FSMSTAT1
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register for details on how to configure
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the behavior of this signal. */
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sampled_cca = 0x0e, /**< A sampled version of the CCA bit from
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demodulator. The value is updated whenever
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a SSAMPLECCA or STXONCCA strobe is issued.*/
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sfd_sync = 0x0f, /**< Pin is high when a SFD has been received
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or transmitted. Cleared when leaving
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RX/TX respectively. Not to be confused
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with the SFD exception.*/
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tx_active = 0x10, /**< Indicates that FFCTRL is in one of the TX
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states. Active-high.*/
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rx_active = 0x11, /**< Indicates that FFCTRL is in one of the
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RX states. Active-high. */
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ffctrl_fifo = 0x12, /**< Pin is high when one or more bytes are
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in the RXFIFO. Low during RXFIFO overflow. */
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ffctrl_fifop = 0x13, /**< Pin is high when the number of bytes
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in the RXFIFO exceeds the programmable
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threshold or at least one complete
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frame is in the RXFIFO. Also highduring
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RXFIFO overflow. Not to be confused with
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the FIFOP exception.*/
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packet_done = 0x14, /**< A complete frame has been received.
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I.e., the number of bytes set by the
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frame-length field has been received.*/
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rfc_xor_rand_i_q = 0x16, /**< XOR between I and Q random outputs.
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Updated at 8 MHz.*/
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rfc_rand_q = 0x17, /**< Random data output from the Q channel
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of the receiver. Updated at 8 MHz.*/
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rfc_rand_i = 0x18, /**< Random data output from the I channel
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of the receiver. Updated at 8 MHz */
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lock_status = 0x19, /**< 1 when PLL is in lock, otherwise 0 */
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pa_pd = 0x20, /**< Power amplifier power-down signal */
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lna_pd = 0x2a, /**< LNA power-down signal*/
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disabled = 0xff, /**< disabled */
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};
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/** @} */
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/**
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* @name RF CORE observable signals settings
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*/
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#ifndef CONFIG_CC2538_RF_OBS_0
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#define CONFIG_CC2538_RF_OBS_0 tx_active
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#endif
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#ifndef CONFIG_CC2538_RF_OBS_1
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#define CONFIG_CC2538_RF_OBS_1 rx_active
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#endif
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#ifndef CONFIG_CC2538_RF_OBS_2
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#define CONFIG_CC2538_RF_OBS_2 rssi_valid
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#endif
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/* Default configration for cc2538dk or similar */
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#ifndef CONFIG_CC2538_RF_OBS_SIG_0_PCX
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#define CONFIG_CC2538_RF_OBS_SIG_0_PCX 0 /* PC0 = LED_1 (red) */
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#endif
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#ifndef CONFIG_CC2538_RF_OBS_SIG_1_PCX
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#define CONFIG_CC2538_RF_OBS_SIG_1_PCX 1 /* PC0 = LED_2 (red) */
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#endif
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#ifndef CONFIG_CC2538_RF_OBS_SIG_2_PCX
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#define CONFIG_CC2538_RF_OBS_SIG_2_PCX 2 /* PC0 = LED_3 (red) */
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#endif
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#if ((CONFIG_CC2538_RF_OBS_SIG_2_PCX > 7) || \
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(CONFIG_CC2538_RF_OBS_SIG_1_PCX > 7) || \
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(CONFIG_CC2538_RF_OBS_SIG_0_PCX > 7))
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#error "CONFIG_CC2538_RF_OBS_SIG_X_PCX must be between 0-7 (PC0-PC7)"
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#endif
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/** @} */
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/**
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* @brief Device descriptor for CC2538 transceiver
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*
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@ -28,7 +28,7 @@
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/*
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/**
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* @brief MAC timer period
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*
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* The period is set to the CSMA-CA Backoff Period Unit (20 symbols, 320 us).
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@ -38,42 +38,53 @@
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#define TIMER_PERIOD_LSB (0xF2)
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#define TIMER_PERIOD_MSB (0x29)
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typedef struct {
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cc2538_reg_t *reg_addr;
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uint32_t value;
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} init_pair_t;
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/**
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* @brief MAC timer period
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*
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* The period is set to the CSMA-CA Backoff Period Unit (20 symbols, 320 us).
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* The system clock runs at 32 MHz. Thus, the timeout period is
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* 320us * 32MHz = ~10738 (0x29F2)
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*/
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#define CCTEST_OBSSELX_EN (BIT(7))
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static void _cc2538_setup_mac_timer(void)
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{
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RFCORE_SFR_MTMSEL &= ~CC2538_SFR_MTMSEL_MASK;
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/* Select timer period */
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RFCORE_SFR_MTMSEL |= CC2538_SFR_MTMSEL_TIMER_P;
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/* Fix timer to Backoff period */
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RFCORE_SFR_MTM0 |= TIMER_PERIOD_LSB;
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RFCORE_SFR_MTM1 |= TIMER_PERIOD_MSB;
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RFCORE_SFR_MTMSEL &= ~CC2538_SFR_MTMSEL_MASK;
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RFCORE_SFR_MTCTRL |= CC2538_MCTRL_SYNC_MASK | CC2538_MCTRL_RUN_MASK;
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}
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static void _cc2538_observable_signals(void)
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{
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/* Select on which pin PC0:7 should the selected observable signals
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be wired through, the signal is selected in CONFIG_CC2538_RF_OBS_%
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and the pin in CONFIG_CC2538_RF_OBS_SIG_%_PCX */
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if (IS_USED(MODULE_CC2538_RF_OBS_SIG)) {
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if (CONFIG_CC2538_RF_OBS_0 != disabled) {
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RFCORE_XREG_RFC_OBS_CTRL0 = CONFIG_CC2538_RF_OBS_0;
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*(&CCTEST_OBSSEL0 + CONFIG_CC2538_RF_OBS_SIG_0_PCX) = \
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CCTEST_OBSSELX_EN | rfc_obs_sig0;
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}
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if (CONFIG_CC2538_RF_OBS_1 != disabled) {
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RFCORE_XREG_RFC_OBS_CTRL1 = CONFIG_CC2538_RF_OBS_1;
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*(&CCTEST_OBSSEL0 + CONFIG_CC2538_RF_OBS_SIG_1_PCX) = \
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CCTEST_OBSSELX_EN | rfc_obs_sig1;
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}
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if (CONFIG_CC2538_RF_OBS_2 != disabled) {
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RFCORE_XREG_RFC_OBS_CTRL2 = CONFIG_CC2538_RF_OBS_2;
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*(&CCTEST_OBSSEL0 + CONFIG_CC2538_RF_OBS_SIG_2_PCX) = \
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CCTEST_OBSSELX_EN | rfc_obs_sig2;
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}
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}
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}
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static const init_pair_t init_table[] = {
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{&SYS_CTRL_RCGCRFC, 0x01 },
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{&SYS_CTRL_SCGCRFC, 0x01 },
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{&SYS_CTRL_DCGCRFC, 0x01 },
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{&RFCORE_XREG_CCACTRL0, 0xf8 },
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{&RFCORE_XREG_TXFILTCFG, 0x09 },
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{&RFCORE_XREG_AGCCTRL1, 0x15 },
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{&ANA_REGS_IVCTRL, 0x0b },
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{&RFCORE_XREG_MDMTEST1, 0x08 },
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{&RFCORE_XREG_FSCAL1, 0x01 },
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{&RFCORE_XREG_RXCTRL, 0x3f },
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{&RFCORE_XREG_MDMCTRL1, 0x14 },
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{&RFCORE_XREG_ADCTEST0, 0x10 },
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{&RFCORE_XREG_ADCTEST1, 0x0e },
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{&RFCORE_XREG_ADCTEST2, 0x03 },
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{&RFCORE_XREG_CSPT, 0xff },
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{&RFCORE_XREG_MDMCTRL0, 0x85 },
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{&RFCORE_XREG_FSCTRL, 0x55 },
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{&RFCORE_XREG_FRMCTRL0, AUTOCRC | AUTOACK },
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{&RFCORE_XREG_FRMCTRL1, 0x00 },
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{&RFCORE_XREG_SRCMATCH, 0x00 },
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{&RFCORE_XREG_FIFOPCTRL, CC2538_RF_MAX_DATA_LEN },
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#if IS_USED(MODULE_IEEE802154_RADIO_HAL)
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{&RFCORE_XREG_RFIRQM0, FIFOP | RXPKTDONE | SFD },
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{&RFCORE_XREG_RFIRQM1, TXDONE | CSP_STOP | TXACKDONE },
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#else
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{&RFCORE_XREG_RFIRQM0, FIFOP | RXPKTDONE },
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#endif
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{&RFCORE_XREG_RFERRM, STROBE_ERR | TXUNDERF | TXOVERF | RXUNDERF | RXOVERF | NLOCK},
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{NULL, 0},
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};
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bool cc2538_channel_clear(void)
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{
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@ -93,41 +104,54 @@ bool cc2538_channel_clear(void)
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void cc2538_init(void)
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{
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const init_pair_t *pair;
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/* Enable RF CORE clock in active mode */
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SYS_CTRL_RCGCRFC = 1UL;
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/* Enable RF CORE clock in sleep mode */
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SYS_CTRL_SCGCRFC = 1UL;
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/* Enable RF CORE clock in PM0 (system clock always powered down
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in PM1-3) */
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SYS_CTRL_DCGCRFC = 1UL;
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/* Wait for the clock enabling to take effect */
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while (!(SYS_CTRL_RCGCRFC & 1UL) || \
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!(SYS_CTRL_SCGCRFC & 1UL) || \
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!(SYS_CTRL_DCGCRFC & 1UL)
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) {}
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for (pair = init_table; pair->reg_addr != NULL; pair++) {
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*pair->reg_addr = pair->value;
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/* Register Setting updates for optimal performance, RM section 23.15 */
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RFCORE_XREG_TXFILTCFG = 0x09;
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RFCORE_XREG_AGCCTRL1 = 0x15;
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RFCORE_XREG_FSCAL1 = 0x01;
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ANA_REGS_IVCTRL = 0x0B;
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/* Enable AUTOCRC and AUTOACK by default*/
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RFCORE_XREG_FRMCTRL0 = AUTOCRC | AUTOACK;
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/* Disable RX after TX, let upper layer change the state */
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RFCORE_XREG_FRMCTRL1 = 0x00;
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/* Disable source address matching and pending bits */
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RFCORE_XREG_SRCMATCH = 0x00;
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/* Set FIFOP_THR to its max value*/
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RFCORE_XREG_FIFOPCTRL = CC2538_RF_MAX_DATA_LEN;
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/* Set default IRQ */
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if (IS_USED(MODULE_IEEE802154_RADIO_HAL)) {
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RFCORE_XREG_RFIRQM1 = TXDONE | CSP_STOP | TXACKDONE;
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RFCORE_XREG_RFIRQM0 = RXPKTDONE | FIFOP | SFD;
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} else {
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RFCORE_XREG_RFIRQM0 = RXPKTDONE | FIFOP;
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}
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/* Select the observable signals (maximum of three) */
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RFCORE_XREG_RFC_OBS_CTRL0 = tx_active;
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RFCORE_XREG_RFC_OBS_CTRL1 = rx_active;
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RFCORE_XREG_RFC_OBS_CTRL2 = ffctrl_fifo;
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/* Enable all RF CORE error interrupts */
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RFCORE_XREG_RFERRM = STROBE_ERR | TXUNDERF | TXOVERF | \
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RXUNDERF | RXOVERF | NLOCK;
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/* Select output pins for the three observable signals */
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#ifdef BOARD_OPENMOTE_CC2538
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CCTEST_OBSSEL0 = 0; /* PC0 = USB_SEL */
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CCTEST_OBSSEL1 = 0; /* PC1 = N/C */
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CCTEST_OBSSEL2 = 0; /* PC2 = N/C */
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CCTEST_OBSSEL3 = 0; /* PC3 = USER_BUTTON */
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CCTEST_OBSSEL4 = OBSSEL_EN | rfc_obs_sig0; /* PC4 = RED_LED */
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CCTEST_OBSSEL5 = 0; /* PC5 = ORANGE_LED */
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CCTEST_OBSSEL6 = OBSSEL_EN | rfc_obs_sig1; /* PC6 = YELLOW_LED */
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CCTEST_OBSSEL7 = OBSSEL_EN | rfc_obs_sig2; /* PC7 = GREEN_LED */
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#else
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/* Assume BOARD_CC2538DK (or similar). */
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CCTEST_OBSSEL0 = OBSSEL_EN | rfc_obs_sig0; /* PC0 = LED_1 (red) */
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CCTEST_OBSSEL1 = OBSSEL_EN | rfc_obs_sig1; /* PC1 = LED_2 (yellow) */
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CCTEST_OBSSEL2 = OBSSEL_EN | rfc_obs_sig2; /* PC2 = LED_3 (green) */
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CCTEST_OBSSEL3 = 0; /* PC3 = LED_4 (red) */
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CCTEST_OBSSEL4 = 0; /* PC4 = BTN_L */
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CCTEST_OBSSEL5 = 0; /* PC5 = BTN_R */
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CCTEST_OBSSEL6 = 0; /* PC6 = BTN_UP */
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CCTEST_OBSSEL7 = 0; /* PC7 = BTN_DN */
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#endif /* BOARD_OPENMOTE_CC2538 */
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_cc2538_observable_signals();
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if (SYS_CTRL->I_MAP) {
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NVIC_SetPriority(RF_RXTX_ALT_IRQn, RADIO_IRQ_PRIO);
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/* Enable IRQs */
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if (SYS_CTRL_I_MAP) {
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NVIC_SetPriority(RF_RXTX_ALT_IRQn, CPU_DEFAULT_IRQ_PRIO);
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NVIC_EnableIRQ(RF_RXTX_ALT_IRQn);
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NVIC_SetPriority(RF_ERR_ALT_IRQn, CPU_DEFAULT_IRQ_PRIO);
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@ -147,16 +171,8 @@ void cc2538_init(void)
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NVIC_EnableIRQ(MACTIMER_IRQn);
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}
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RFCORE_SFR_MTMSEL &= ~CC2538_SFR_MTMSEL_MASK;
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/* Select timer period */
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RFCORE_SFR_MTMSEL |= CC2538_SFR_MTMSEL_TIMER_P;
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/* Fix timer to Backoff period */
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RFCORE_SFR_MTM0 |= TIMER_PERIOD_LSB;
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RFCORE_SFR_MTM1 |= TIMER_PERIOD_MSB;
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RFCORE_SFR_MTMSEL &= ~CC2538_SFR_MTMSEL_MASK;
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RFCORE_SFR_MTCTRL |= CC2538_MCTRL_SYNC_MASK | CC2538_MCTRL_RUN_MASK;
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/* setup mac timer */
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_cc2538_setup_mac_timer();
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/* Flush the receive and transmit FIFOs */
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RFCORE_SFR_RFST = ISFLUSHTX;
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@ -165,7 +181,8 @@ void cc2538_init(void)
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bool cc2538_is_on(void)
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{
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return RFCORE->XREG_FSMSTAT1bits.RX_ACTIVE || RFCORE->XREG_FSMSTAT1bits.TX_ACTIVE;
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return RFCORE->XREG_FSMSTAT1bits.RX_ACTIVE || \
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RFCORE->XREG_FSMSTAT1bits.TX_ACTIVE;
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}
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void cc2538_off(void)
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@ -64,7 +64,7 @@ void isr_rfcoreerr(void)
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void isr_rfcorerxtx(void)
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{
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cc2538_irq_handler();
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cc2538_irq_handler();
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cortexm_isr_end();
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}
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|
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@ -9,6 +9,7 @@ PSEUDOMODULES += can_mbox
|
||||
PSEUDOMODULES += can_pm
|
||||
PSEUDOMODULES += can_raw
|
||||
PSEUDOMODULES += ccn-lite-utils
|
||||
PSEUDOMODULES += cc2538_rf_obs_sig
|
||||
PSEUDOMODULES += conn_can_isotp_multi
|
||||
PSEUDOMODULES += cord_ep_standalone
|
||||
PSEUDOMODULES += core_%
|
||||
|
||||
Loading…
Reference in New Issue
Block a user