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Merge pull request #14749 from bergzand/pr/stm32/dynamic_spi_freqs

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stm32: Add support for arbitrary SPI clock rates
This commit is contained in:
benpicco 2020-08-18 17:57:30 +02:00 committed by GitHub
commit 4a2d867339
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GPG Key ID: 4AEE18F83AFDEB23
68 changed files with 76 additions and 1376 deletions
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4
.github/workflows/tools-buildtest.yml vendored
View File

@ -55,10 +55,6 @@ jobs:
uses: aabadie/riot-action@v1
with:
cmd: make -C dist/tools/uhcpd
- name: Build stm32 spi_divtable
uses: aabadie/riot-action@v1
with:
cmd: make -C cpu/stm32/dist/spi_divtable
- name: Build stm32 clk_conf
uses: aabadie/riot-action@v1
with:

20
boards/b-l072z-lrwan1/include/periph_conf.h
View File

@ -96,28 +96,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI2,

1
boards/b-l475e-iot01a/include/periph_conf.h
View File

@ -21,7 +21,6 @@
#include "periph_cpu.h"
#include "l4/cfg_clock_80_1.h"
#include "cfg_spi_divtable.h"
#include "cfg_rtt_default.h"
#ifdef __cplusplus

20
boards/common/blxxxpill/include/periph_conf.h
View File

@ -257,28 +257,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

23
boards/common/iotlab/include/periph_conf_common.h
View File

@ -178,29 +178,6 @@ static const i2c_conf_t i2c_config[] = {
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
/** @} */
/**
* @brief Shared SPI clock div table
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
#ifdef __cplusplus
}
#endif

292
boards/common/stm32/include/cfg_spi_divtable.h
View File

@ -1,292 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Collection of pre-computed bus pre-scalers for SPI configuration
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef CFG_SPI_DIVTABLE_H
#define CFG_SPI_DIVTABLE_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name SPI bus divider values for pre-defined peripheral bus clock speeds
*
* @note These spi_divtables are generated using
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define CFG_SPIDIV_20 \
{ /* for 20000000Hz */ \
7, /* -> 78125Hz */ \
5, /* -> 312500Hz */ \
3, /* -> 1250000Hz */ \
1, /* -> 5000000Hz */ \
0 /* -> 10000000Hz */ \
},
#define CFG_SPIDIV_30 \
{ /* for 30000000Hz */ \
7, /* -> 117187Hz */ \
5, /* -> 468750Hz */ \
4, /* -> 937500Hz */ \
2, /* -> 3750000Hz */ \
1 /* -> 7500000Hz */ \
},
#define CFG_SPIDIV_32 \
{ /* for 32000000Hz */ \
7, /* -> 125000Hz */ \
5, /* -> 500000Hz */ \
4, /* -> 1000000Hz */ \
2, /* -> 4000000Hz */ \
1 /* -> 8000000Hz */ \
},
#define CFG_SPIDIV_36 \
{ /* for 36000000Hz */ \
7, /* -> 140625Hz */ \
6, /* -> 281250Hz */ \
4, /* -> 1125000Hz */ \
2, /* -> 4500000Hz */ \
1 /* -> 9000000Hz */ \
},
#define CFG_SPIDIV_40 \
{ /* for 40000000Hz */ \
7, /* -> 156250Hz */ \
6, /* -> 312500Hz */ \
4, /* -> 1250000Hz */ \
2, /* -> 5000000Hz */ \
1 /* -> 10000000Hz */ \
},
#define CFG_SPIDIV_42 \
{ /* for 42000000Hz */ \
7, /* -> 164062Hz */ \
6, /* -> 328125Hz */ \
4, /* -> 1312500Hz */ \
2, /* -> 5250000Hz */ \
1 /* -> 10500000Hz */ \
},
#define CFG_SPIDIV_45 \
{ /* for 45000000Hz */ \
7, /* -> 175781Hz */ \
6, /* -> 351562Hz */ \
5, /* -> 703125Hz */ \
2, /* -> 5625000Hz */ \
1 /* -> 11250000Hz */ \
},
#define CFG_SPIDIV_48 \
{ /* for 48000000Hz */ \
7, /* -> 187500Hz */ \
6, /* -> 375000Hz */ \
5, /* -> 750000Hz */ \
2, /* -> 6000000Hz */ \
1 /* -> 12000000Hz */ \
},
#define CFG_SPIDIV_50 \
{ /* for 50000000Hz */ \
7, /* -> 195312Hz */ \
6, /* -> 390625Hz */ \
5, /* -> 781250Hz */ \
2, /* -> 6250000Hz */ \
1 /* -> 12500000Hz */ \
},
#define CFG_SPIDIV_54 \
{ /* for 54000000Hz */ \
7, /* -> 210937Hz */ \
6, /* -> 421875Hz */ \
5, /* -> 843750Hz */ \
3, /* -> 3375000Hz */ \
2 /* -> 6750000Hz */ \
},
#define CFG_SPIDIV_60 \
{ /* for 60000000Hz */ \
7, /* -> 234375Hz */ \
6, /* -> 468750Hz */ \
5, /* -> 937500Hz */ \
3, /* -> 3750000Hz */ \
2 /* -> 7500000Hz */ \
},
#define CFG_SPIDIV_64 \
{ /* for 64000000Hz */ \
7, /* -> 250000Hz */ \
6, /* -> 500000Hz */ \
5, /* -> 1000000Hz */ \
3, /* -> 4000000Hz */ \
2 /* -> 8000000Hz */ \
},
#define CFG_SPIDIV_72 \
{ /* for 72000000Hz */ \
7, /* -> 281250Hz */ \
7, /* -> 281250Hz */ \
5, /* -> 1125000Hz */ \
3, /* -> 4500000Hz */ \
2 /* -> 9000000Hz */ \
},
#define CFG_SPIDIV_84 \
{ /* for 84000000Hz */ \
7, /* -> 328125Hz */ \
7, /* -> 328125Hz */ \
5, /* -> 1312500Hz */ \
3, /* -> 5250000Hz */ \
2 /* -> 10500000Hz */ \
},
#define CFG_SPIDIV_90 \
{ /* for 90000000Hz */ \
7, /* -> 351562Hz */ \
7, /* -> 351562Hz */ \
6, /* -> 703125Hz */ \
3, /* -> 5625000Hz */ \
2 /* -> 11250000Hz */ \
},
#define CFG_SPIDIV_96 \
{ /* for 96000000Hz */ \
7, /* -> 375000Hz */ \
7, /* -> 375000Hz */ \
6, /* -> 750000Hz */ \
3, /* -> 6000000Hz */ \
2 /* -> 12000000Hz */ \
},
#define CFG_SPIDIV_100 \
{ /* for 100000000Hz */ \
7, /* -> 390625Hz */ \
7, /* -> 390625Hz */ \
6, /* -> 781250Hz */ \
3, /* -> 6250000Hz */ \
2 /* -> 12500000Hz */ \
},
#define CFG_SPIDIV_108 \
{ /* for 108000000Hz */ \
7, /* -> 421875Hz */ \
7, /* -> 421875Hz */ \
6, /* -> 843750Hz */ \
4, /* -> 3375000Hz */ \
3 /* -> 6750000Hz */ \
},
/** @} */
/**
* @name SPI clock divisors
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
*
* @{
*/
static const uint8_t spi_divtable[2][5] = {
#if (CLOCK_APB1 == 20000000)
CFG_SPIDIV_20
#elif (CLOCK_APB1 == 30000000)
CFG_SPIDIV_30
#elif (CLOCK_APB1 == 32000000)
CFG_SPIDIV_32
#elif (CLOCK_APB1 == 36000000)
CFG_SPIDIV_36
#elif (CLOCK_APB1 == 40000000)
CFG_SPIDIV_40
#elif (CLOCK_APB1 == 42000000)
CFG_SPIDIV_42
#elif (CLOCK_APB1 == 45000000)
CFG_SPIDIV_45
#elif (CLOCK_APB1 == 48000000)
CFG_SPIDIV_48
#elif (CLOCK_APB1 == 50000000)
CFG_SPIDIV_50
#elif (CLOCK_APB1 == 54000000)
CFG_SPIDIV_54
#elif (CLOCK_APB1 == 72000000)
CFG_SPIDIV_72
#elif (CLOCK_APB1 == 60000000)
CFG_SPIDIV_60
#elif (CLOCK_APB1 == 64000000)
CFG_SPIDIV_64
#elif (CLOCK_APB1 == 84000000)
CFG_SPIDIV_84
#elif (CLOCK_APB1 == 90000000)
CFG_SPIDIV_90
#elif (CLOCK_APB1 == 96000000)
CFG_SPIDIV_96
#elif (CLOCK_APB1 == 100000000)
CFG_SPIDIV_100
#elif (CLOCK_APB1 == 108000000)
CFG_SPIDIV_108
#else
#error "CFG_SPI_DIVTABLE: no prescalers for selected APB1 bus clock defined"
#endif
#if (CLOCK_APB2 == 20000000)
CFG_SPIDIV_20
#elif (CLOCK_APB2 == 30000000)
CFG_SPIDIV_30
#elif (CLOCK_APB2 == 32000000)
CFG_SPIDIV_32
#elif (CLOCK_APB2 == 36000000)
CFG_SPIDIV_36
#elif (CLOCK_APB2 == 40000000)
CFG_SPIDIV_40
#elif (CLOCK_APB2 == 42000000)
CFG_SPIDIV_42
#elif (CLOCK_APB2 == 45000000)
CFG_SPIDIV_45
#elif (CLOCK_APB2 == 48000000)
CFG_SPIDIV_48
#elif (CLOCK_APB2 == 50000000)
CFG_SPIDIV_50
#elif (CLOCK_APB2 == 54000000)
CFG_SPIDIV_54
#elif (CLOCK_APB2 == 72000000)
CFG_SPIDIV_72
#elif (CLOCK_APB2 == 60000000)
CFG_SPIDIV_60
#elif (CLOCK_APB2 == 64000000)
CFG_SPIDIV_64
#elif (CLOCK_APB2 == 84000000)
CFG_SPIDIV_84
#elif (CLOCK_APB2 == 90000000)
CFG_SPIDIV_90
#elif (CLOCK_APB2 == 96000000)
CFG_SPIDIV_96
#elif (CLOCK_APB2 == 100000000)
CFG_SPIDIV_100
#elif (CLOCK_APB2 == 108000000)
CFG_SPIDIV_108
#else
#error "CFG_SPI_DIVTABLE: no prescalers for selected APB2 bus clock defined"
#endif
};
#ifdef __cplusplus
}
#endif
#endif /* CFG_SPI_DIVTABLE_H */
/** @} */

20
boards/fox/include/periph_conf.h
View File

@ -112,28 +112,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI2,

20
boards/i-nucleo-lrwan1/include/periph_conf.h
View File

@ -54,28 +54,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1, /* connected to SX1272 */

20
boards/im880b/include/periph_conf.h
View File

@ -99,28 +99,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/limifrog-v1/include/periph_conf.h
View File

@ -103,28 +103,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/lobaro-lorabox/include/periph_conf.h
View File

@ -113,28 +113,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/lsn50/include/periph_conf.h
View File

@ -95,28 +95,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1, /* connected to SX1276 */

23
boards/maple-mini/include/periph_conf.h
View File

@ -152,29 +152,6 @@ static const i2c_conf_t i2c_config[] = {
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
/** @} */
/**
* @brief Shared SPI clock div table
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
/**
* @name SPI configuration
* @{

1
boards/msbiot/include/periph_conf.h
View File

@ -21,7 +21,6 @@
#include "periph_cpu.h"
#include "f4/cfg_clock_168_16_0.h"
#include "cfg_spi_divtable.h"
#ifdef __cplusplus
extern "C" {

20
boards/nucleo-f030r8/include/periph_conf.h
View File

@ -139,28 +139,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f031k6/include/periph_conf.h
View File

@ -119,28 +119,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f042k6/include/periph_conf.h
View File

@ -129,28 +129,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f072rb/include/periph_conf.h
View File

@ -160,28 +160,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f091rc/include/periph_conf.h
View File

@ -147,28 +147,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f103rb/include/periph_conf.h
View File

@ -164,28 +164,8 @@ static const i2c_conf_t i2c_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f207zg/include/periph_conf.h
View File

@ -170,28 +170,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 30000000Hz */
7, /* -> 117187Hz */
5, /* -> 468750Hz */
4, /* -> 937500Hz */
2, /* -> 3750000Hz */
1 /* -> 7500000Hz */
},
{ /* for APB2 @ 60000000Hz */
7, /* -> 234375Hz */
6, /* -> 468750Hz */
5, /* -> 937500Hz */
3, /* -> 3750000Hz */
2 /* -> 7500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f302r8/include/periph_conf.h
View File

@ -125,28 +125,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI2,

20
boards/nucleo-f303k8/include/periph_conf.h
View File

@ -120,28 +120,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 64000000Hz */
7, /* -> 250000Hz */
6, /* -> 500000Hz */
5, /* -> 1000000Hz */
3, /* -> 4000000Hz */
2 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f303re/include/periph_conf.h
View File

@ -123,28 +123,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f303ze/include/periph_conf.h
View File

@ -146,28 +146,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f334r8/include/periph_conf.h
View File

@ -122,28 +122,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f401re/include/periph_conf.h
View File

@ -162,28 +162,8 @@ static const qdec_conf_t qdec_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f410rb/include/periph_conf.h
View File

@ -103,28 +103,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 96000000Hz */
7, /* -> 375000Hz */
7, /* -> 375000Hz */
6, /* -> 750000Hz */
3, /* -> 6000000Hz */
2 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f411re/include/periph_conf.h
View File

@ -132,28 +132,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 96000000Hz */
7, /* -> 375000Hz */
7, /* -> 375000Hz */
6, /* -> 750000Hz */
3, /* -> 6000000Hz */
2 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f412zg/include/periph_conf.h
View File

@ -134,28 +134,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 50000000Hz */
7, /* -> 195312Hz */
6, /* -> 390625Hz */
5, /* -> 781250Hz */
2, /* -> 6250000Hz */
1 /* -> 12500000Hz */
},
{ /* for APB2 @ 100000000Hz */
7, /* -> 390625Hz */
7, /* -> 390625Hz */
6, /* -> 781250Hz */
3, /* -> 6250000Hz */
2 /* -> 12500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-f413zh/include/periph_conf.h
View File

@ -135,28 +135,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 50000000Hz */
7, /* -> 195312Hz */
6, /* -> 390625Hz */
5, /* -> 781250Hz */
2, /* -> 6250000Hz */
1 /* -> 12500000Hz */
},
{ /* for APB2 @ 100000000Hz */
7, /* -> 390625Hz */
7, /* -> 390625Hz */
6, /* -> 781250Hz */
3, /* -> 6250000Hz */
2 /* -> 12500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

1
boards/nucleo-f429zi/include/periph_conf.h
View File

@ -22,7 +22,6 @@
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_1.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_spi_divtable.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"

4
boards/nucleo-f446re/include/periph_conf.h
View File

@ -22,7 +22,6 @@
#include "periph_cpu.h"
#include "f4/cfg_clock_180_8_1.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_spi_divtable.h"
#include "cfg_timer_tim5.h"
#ifdef __cplusplus
@ -173,9 +172,6 @@ static const qdec_conf_t qdec_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const spi_conf_t spi_config[] = {

1
boards/nucleo-f446ze/include/periph_conf.h
View File

@ -22,7 +22,6 @@
#include "periph_cpu.h"
#include "f4/cfg_clock_180_8_1.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_spi_divtable.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"

4
boards/nucleo-f767zi/include/periph_conf.h
View File

@ -22,7 +22,6 @@
#include "periph_cpu.h"
#include "f7/cfg_clock_216_8_1.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_spi_divtable.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
#include "cfg_usb_otg_fs.h"
@ -108,9 +107,6 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const spi_conf_t spi_config[] = {

20
boards/nucleo-g070rb/include/periph_conf.h
View File

@ -82,28 +82,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for 64000000Hz */
7, /* -> 250000Hz */
6, /* -> 500000Hz */
5, /* -> 1000000Hz */
3, /* -> 4000000Hz */
2 /* -> 8000000Hz */
},
{ /* for 64000000Hz */
7, /* -> 250000Hz */
6, /* -> 500000Hz */
5, /* -> 1000000Hz */
3, /* -> 4000000Hz */
2 /* -> 8000000Hz */
},
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-g474re/include/periph_conf.h
View File

@ -68,28 +68,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 80000000Hz */
7, /* -> 312500Hz */
7, /* -> 312500Hz */
5, /* -> 1250000Hz */
3, /* -> 5000000Hz */
2 /* -> 10000000Hz */
},
{ /* for APB2 @ 80000000Hz */
7, /* -> 312500Hz */
7, /* -> 312500Hz */
5, /* -> 1250000Hz */
3, /* -> 5000000Hz */
2 /* -> 10000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

17
boards/nucleo-l031k6/include/periph_conf.h
View File

@ -79,23 +79,6 @@ static const pwm_conf_t pwm_config[] = {
* @name SPI configuration
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-l053r8/include/periph_conf.h
View File

@ -89,28 +89,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-l073rz/include/periph_conf.h
View File

@ -107,28 +107,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nucleo-l152re/include/periph_conf.h
View File

@ -168,28 +168,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

1
boards/nucleo-l412kb/include/periph_conf.h
View File

@ -25,7 +25,6 @@
#include "periph_cpu.h"
#include "l4/cfg_clock_80_1.h"
#include "cfg_spi_divtable.h"
#include "cfg_i2c1_pb6_pb7.h"
#include "cfg_timer_tim2.h"
#include "cfg_rtt_default.h"

1
boards/nucleo-l432kc/include/periph_conf.h
View File

@ -23,7 +23,6 @@
#include "periph_cpu.h"
#include "l4/cfg_clock_80_1.h"
#include "cfg_spi_divtable.h"
#include "cfg_i2c1_pb6_pb7.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

1
boards/nucleo-l433rc/include/periph_conf.h
View File

@ -21,7 +21,6 @@
#include "periph_cpu.h"
#include "l4/cfg_clock_80_1.h"
#include "cfg_spi_divtable.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

20
boards/nucleo-l452re/include/periph_conf.h
View File

@ -146,28 +146,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 20000000Hz */
7, /* -> 78125Hz */
5, /* -> 312500Hz */
3, /* -> 1250000Hz */
1, /* -> 5000000Hz */
0 /* -> 10000000Hz */
},
{ /* for APB2 @ 40000000Hz */
7, /* -> 156250Hz */
6, /* -> 312500Hz */
4, /* -> 1250000Hz */
2, /* -> 5000000Hz */
1 /* -> 10000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

1
boards/nucleo-l476rg/include/periph_conf.h
View File

@ -25,7 +25,6 @@
#include "periph_cpu.h"
#include "l4/cfg_clock_80_1.h"
#include "cfg_spi_divtable.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"

1
boards/nucleo-l496zg/include/periph_conf.h
View File

@ -21,7 +21,6 @@
#include "periph_cpu.h"
#include "l4/cfg_clock_80_1.h"
#include "cfg_spi_divtable.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"

20
boards/nucleo-l4r5zi/include/periph_conf.h
View File

@ -130,28 +130,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 30000000Hz */
7, /* -> 117187Hz */
5, /* -> 468750Hz */
4, /* -> 937500Hz */
2, /* -> 3750000Hz */
1 /* -> 7500000Hz */
},
{ /* for APB2 @ 60000000Hz */
7, /* -> 234375Hz */
6, /* -> 468750Hz */
5, /* -> 937500Hz */
3, /* -> 3750000Hz */
2 /* -> 7500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/nz32-sc151/include/periph_conf.h
View File

@ -116,28 +116,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/olimexino-stm32/include/periph_conf.h
View File

@ -239,28 +239,8 @@ static const i2c_conf_t i2c_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

1
boards/p-l496g-cell02/include/periph_conf.h
View File

@ -21,7 +21,6 @@
#include "periph_cpu.h"
#include "l4/cfg_clock_80_1.h"
#include "cfg_spi_divtable.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

20
boards/p-nucleo-wb55/include/periph_conf.h
View File

@ -126,28 +126,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 20000000Hz */
7, /* -> 78125Hz */
5, /* -> 312500Hz */
3, /* -> 1250000Hz */
1, /* -> 5000000Hz */
0 /* -> 10000000Hz */
},
{ /* for APB2 @ 40000000Hz */
7, /* -> 156250Hz */
6, /* -> 312500Hz */
4, /* -> 1250000Hz */
2, /* -> 5000000Hz */
1 /* -> 10000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/pyboard/include/periph_conf.h
View File

@ -121,28 +121,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/spark-core/include/periph_conf.h
View File

@ -103,28 +103,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/stm32f030f4-demo/include/periph_conf.h
View File

@ -127,28 +127,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

17
boards/stm32f0discovery/include/periph_conf.h
View File

@ -128,23 +128,6 @@ static const uart_conf_t uart_config[] = {
* @name SPI configuration
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

17
boards/stm32f3discovery/include/periph_conf.h
View File

@ -162,23 +162,6 @@ static const pwm_conf_t pwm_config[] = {
* @name SPI configuration
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

4
boards/stm32f429i-disc1/include/periph_conf.h
View File

@ -21,7 +21,6 @@
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_1.h"
#include "cfg_spi_divtable.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_hs_fs.h"
@ -72,9 +71,6 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const spi_conf_t spi_config[] = {

1
boards/stm32f4discovery/include/periph_conf.h
View File

@ -22,7 +22,6 @@
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_0.h"
#include "cfg_spi_divtable.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus

20
boards/stm32f723e-disco/include/periph_conf.h
View File

@ -182,28 +182,8 @@ static const i2c_conf_t i2c_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 54000000Hz */
7, /* -> 210937Hz */
6, /* -> 421875Hz */
5, /* -> 843750Hz */
3, /* -> 3375000Hz */
2 /* -> 6750000Hz */
},
{ /* for APB2 @ 108000000Hz */
7, /* -> 421875Hz */
7, /* -> 421875Hz */
6, /* -> 843750Hz */
4, /* -> 3375000Hz */
3 /* -> 6750000Hz */
}
};
static const spi_conf_t spi_config[] = {
{ /* Arduino connector */
.dev = SPI1,

20
boards/stm32l0538-disco/include/periph_conf.h
View File

@ -95,28 +95,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

20
boards/ublox-c030-u201/include/periph_conf.h
View File

@ -169,28 +169,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI4,

20
boards/weact-f411ce/include/periph_conf.h
View File

@ -106,28 +106,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 96000000Hz */
7, /* -> 375000Hz */
7, /* -> 375000Hz */
6, /* -> 750000Hz */
3, /* -> 6000000Hz */
2 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{ /* U3 - SPI flash */
.dev = SPI1,

1
cpu/stm32/dist/.gitignore vendored
View File

@ -1,2 +1 @@
clk_conf/clk_conf
spi_divtable/spi_divtable

12
cpu/stm32/dist/spi_divtable/Makefile vendored
View File

@ -1,12 +0,0 @@
NAME = spi_divtable
CC = gcc
CFLAGS = -std=c99 -Wall
SRC = $(wildcard *.c)
.PHONY: all clean
all:
$(CC) $(CFLAGS) -o $(NAME) $(SRC)
clean:
rm -f $(NAME)

106
cpu/stm32/dist/spi_divtable/spi_divtable.c vendored
View File

@ -1,106 +0,0 @@
/*
* Copyright (C) 2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @brief Compute SPI clock scaler values for STM32x CPUs
*
* This helper tool calculates the needed SPI scaler values for the APBx buses.
* It outputs the values for the possible SPI clock speeds based on the clock
* speeds of the APB1 and the APB2 bus.
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#define ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0]))
static int targets[] = { 100000, 400000, 1000000, 5000000, 10000000 };
/**
* @brief Find the best fitting divisor value base on target and APB clock
*
* The SPI bus clock speed is calculated as follows:
*
* clk_bus = clk_apb / 2 ^ (x + 1)
*
* In this function we will try to find the x-value, that brings clk_bus as
* close as possible to the value given in @p target.
*
* @param[in] bus clock speed of the given APB bus
* @param[in] target targeted SPI clock speed
*
* @return the closes divisor value to be used in the clock config register
*/
static int find_best(int bus, int target)
{
int br = -1;
int tmp = bus;
do {
// printf("b: x: %i - tmp: %i\n", br, tmp);
++br;
tmp /= 2;
if (tmp == target) {
return br;
}
// printf("a: x: %i - tmp: %i\n", br, tmp);
// printf(" (tmp - target):%i\n", (tmp - target));
} while ((tmp - target > 0) && (br < 7));
int old = tmp * 2;
// printf("(target - tmp):%i, (old - target): %i\n", (target - tmp), (old - target));
if ((target - tmp) > (old - target)) {
return (br - 1);
}
return br;
}
static int real_clk(int bus, int br)
{
return bus / (2 << br);
}
int main(int argc, char **argv)
{
int tnum = ARRAY_SIZE(targets);
int apb[2];
if (argc != 3) {
printf("usage: %s <APB1 clk> <APB2 clk> (in Hz)\n", argv[0]);
return 1;
}
apb[0] = atoi(argv[1]); /* APB1 */
apb[1] = atoi(argv[2]); /* APB2 */
if ((apb[0] <= 0) || (apb[1] <= 0)) {
puts("error: invalid APB clock speed values");
return 1;
}
printf("static const uint8_t spi_divtable[2][%i] = {\n", tnum);
for (int bus = 0; bus < ARRAY_SIZE(apb); bus ++) {
printf(" { /* for APB%i @ %iHz */\n", (bus + 1), apb[bus]);
for (int t = 0; t < tnum; t++) {
int br = find_best(apb[bus], targets[t]);
printf(" %i%c /* -> %iHz */\n",
br, ((t < (tnum - 1)) ? ',' : ' '), real_clk(apb[bus], br));
}
printf(" }%s\n", ((bus == 0) ? "," : ""));
}
puts("};");
return 0;
}

20
cpu/stm32/include/periph_cpu.h
View File

@ -22,6 +22,7 @@
#define PERIPH_CPU_H
#include "cpu.h"
#include "macros/units.h"
#if defined(CPU_FAM_STM32F0)
#include "periph/f0/periph_cpu.h"
@ -620,6 +621,25 @@ typedef enum {
/** @} */
#endif /* ndef DOXYGEN */
/**
* @brief Override SPI clock speed values
* @{
*/
#define HAVE_SPI_CLK_T
enum {
SPI_CLK_100KHZ = KHZ(100), /**< drive the SPI bus with 100KHz */
SPI_CLK_400KHZ = KHZ(400), /**< drive the SPI bus with 400KHz */
SPI_CLK_1MHZ = MHZ(1), /**< drive the SPI bus with 1MHz */
SPI_CLK_5MHZ = MHZ(5), /**< drive the SPI bus with 5MHz */
SPI_CLK_10MHZ = MHZ(10), /**< drive the SPI bus with 10MHz */
};
/**
* @brief SPI clock type
*/
typedef uint32_t spi_clk_t;
/** @} */
/**
* @brief Structure for UART configuration data
*/

57
cpu/stm32/periph/spi.c
View File

@ -26,16 +26,21 @@
* @}
*/
#include "bitarithm.h"
#include "cpu.h"
#include "mutex.h"
#include "assert.h"
#include "periph/spi.h"
#include "pm_layered.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
/**
* @brief Number of bits to shift the BR value in the CR1 register
*/
#define BR_SHIFT (3U)
#define BR_MAX (7U)
#ifdef SPI_CR2_FRXTH
/* configure SPI for 8-bit data width */
@ -52,6 +57,16 @@
*/
static mutex_t locks[SPI_NUMOF];
/**
* @brief Clock configuration cache
*/
static uint32_t clocks[SPI_NUMOF];
/**
* @brief Clock divider cache
*/
static uint8_t dividers[SPI_NUMOF];
static inline SPI_TypeDef *dev(spi_t bus)
{
return spi_config[bus].dev;
@ -64,6 +79,35 @@ static inline bool _use_dma(const spi_conf_t *conf)
}
#endif
/**
* @brief Multiplier for clock divider calculations
*
* Makes the divider calculation fixed point
*/
#define SPI_APB_CLOCK_SHIFT (4U)
#define SPI_APB_CLOCK_MULT (1U << SPI_APB_CLOCK_SHIFT)
static uint8_t _get_clkdiv(const spi_conf_t *conf, uint32_t clock)
{
uint32_t bus_clock = periph_apb_clk(conf->apbbus);
/* Shift bus_clock with SPI_APB_CLOCK_SHIFT to create a fixed point int */
uint32_t div = (bus_clock << SPI_APB_CLOCK_SHIFT) / (2 * clock);
DEBUG("[spi] clock: divider: %"PRIu32"\n", div);
/* Test if the divider is 2 or smaller, keeping the fixed point in mind */
if (div <= SPI_APB_CLOCK_MULT) {
return 0;
}
/* determine MSB and compensate back for the fixed point int shift */
uint8_t rounded_div = bitarithm_msb(div) - SPI_APB_CLOCK_SHIFT;
/* Determine if rounded_div is not a power of 2 */
if ((div & (div - 1)) != 0) {
/* increment by 1 to ensure that the clock speed at most the
* requested clock speed */
rounded_div++;
}
return rounded_div > BR_MAX ? BR_MAX : rounded_div;
}
void spi_init(spi_t bus)
{
assert(bus < SPI_NUMOF);
@ -162,7 +206,18 @@ int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
/* enable SPI device clock */
periph_clk_en(spi_config[bus].apbbus, spi_config[bus].rccmask);
/* enable device */
uint8_t br = spi_divtable[spi_config[bus].apbbus][clk];
if (clk != clocks[bus]) {
dividers[bus] = _get_clkdiv(&spi_config[bus], clk);
clocks[bus] = clk;
}
uint8_t br = dividers[bus];
DEBUG("[spi] acquire: requested clock: %"PRIu32", resulting clock: %"PRIu32
" BR divider: %u\n",
clk,
periph_apb_clk(spi_config[bus].apbbus)/(1 << (br + 1)),
br);
uint16_t cr1_settings = ((br << BR_SHIFT) | mode | SPI_CR1_MSTR);
/* Settings to add to CR2 in addition to SPI_CR2_SETTINGS */
uint16_t cr2_extra_settings = 0;