Merge pull request #15273 from aabadie/pr/cpu/stm32_clk_cfg_in_cpu

boards/stm32: cpu/stm32: move clock configuration from boards to cpu

boards/b-l072z-lrwan1/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_rtt_default.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_timer_tim2.h"

boards/b-l475e-iot01a/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_rtt_default.h"
 
 #ifdef __cplusplus

boards/common/blxxxpill/include/periph_conf.h

@@ -35,7 +35,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/common/iotlab/include/periph_conf_common.h

@@ -32,7 +32,7 @@
 #define CLOCK_HSE               MHZ(16)
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/f4vi1/include/periph_conf.h

@@ -30,7 +30,7 @@
 #define CLOCK_HSE               MHZ(16)
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_180.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/fox/include/periph_conf.h

@@ -31,7 +31,7 @@
 #define CLOCK_HSE               MHZ(16)
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/i-nucleo-lrwan1/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"
 

boards/im880b/include/periph_conf.h

@@ -27,7 +27,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/limifrog-v1/include/periph_conf.h

@@ -20,7 +20,7 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/lobaro-lorabox/include/periph_conf.h

@@ -32,7 +32,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_timer_tim2.h"
 
 #ifdef __cplusplus

boards/lsn50/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"
 

boards/maple-mini/include/periph_conf.h

@@ -20,7 +20,7 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/msbiot/include/periph_conf.h

@@ -28,7 +28,7 @@
 #define CLOCK_HSE               MHZ(16)
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_180.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/nucleo-f103rb/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/nucleo-f207zg/include/periph_conf.h

@@ -32,7 +32,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_120.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_usb_otg_fs.h"
 #include "mii.h"

boards/nucleo-f302r8/include/periph_conf.h

@@ -34,7 +34,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_timer_tim2.h"
 
 #ifdef __cplusplus

boards/nucleo-f303k8/include/periph_conf.h

@@ -29,7 +29,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_timer_tim2.h"
 
 #ifdef __cplusplus

boards/nucleo-f303re/include/periph_conf.h

@@ -32,7 +32,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_timer_tim2.h"
 
 #ifdef __cplusplus

boards/nucleo-f303ze/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_timer_tim2.h"
 
 #ifdef __cplusplus

boards/nucleo-f334r8/include/periph_conf.h

@@ -31,7 +31,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_timer_tim2.h"
 
 #ifdef __cplusplus

boards/nucleo-f401re/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_84.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_timer_tim5.h"
 

boards/nucleo-f410rb/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_100.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_timer_tim5.h"
 

boards/nucleo-f411re/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_100.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_timer_tim5.h"
 

boards/nucleo-f412zg/include/periph_conf.h

@@ -32,7 +32,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_100.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_timer_tim5.h"
 #include "cfg_usb_otg_fs.h"

boards/nucleo-f413zh/include/periph_conf.h

@@ -32,7 +32,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_100.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim5.h"

boards/nucleo-f429zi/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_180.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_timer_tim5.h"
 #include "cfg_usb_otg_fs.h"

boards/nucleo-f446re/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_180.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_timer_tim5.h"
 

boards/nucleo-f446ze/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_180.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_timer_tim5.h"
 #include "cfg_usb_otg_fs.h"

boards/nucleo-f767zi/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_216.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"

boards/nucleo-g070rb/include/periph_conf.h

@@ -26,7 +26,7 @@
 #define CONFIG_BOARD_HAS_LSE            1
 #endif
 
-#include "g0/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 

boards/nucleo-g071rb/include/periph_conf.h

@@ -24,7 +24,7 @@
 #define CONFIG_BOARD_HAS_LSE            1
 #endif
 
-#include "g0/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 

boards/nucleo-g431rb/include/periph_conf.h

@@ -33,7 +33,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "g4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"

boards/nucleo-g474re/include/periph_conf.h

@@ -33,7 +33,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "g4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim5.h"

boards/nucleo-l011k4/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb6_pb7.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"

boards/nucleo-l031k6/include/periph_conf.h

@@ -27,7 +27,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb6_pb7.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"

boards/nucleo-l053r8/include/periph_conf.h

@@ -27,7 +27,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"
 

boards/nucleo-l073rz/include/periph_conf.h

@@ -27,7 +27,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"
 

boards/nucleo-l152re/include/periph_conf.h

@@ -21,7 +21,7 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_timer_tim5.h"
 
 #ifdef __cplusplus

boards/nucleo-l412kb/include/periph_conf.h

@@ -29,7 +29,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb6_pb7.h"
 #include "cfg_timer_tim2.h"
 #include "cfg_rtt_default.h"

boards/nucleo-l432kc/include/periph_conf.h

@@ -27,7 +27,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb6_pb7.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"

boards/nucleo-l433rc/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"
 

boards/nucleo-l452re/include/periph_conf.h

@@ -31,7 +31,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"

boards/nucleo-l476rg/include/periph_conf.h

@@ -29,7 +29,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 

boards/nucleo-l496zg/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 

boards/nucleo-l4r5zi/include/periph_conf.h

@@ -19,11 +19,7 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
-#include "periph_cpu.h"
-
 /* Add specific clock configuration (HSE, LSE) for this board here */
-#define CLOCK_CORECLOCK_MAX             MHZ(120)
-
 #ifndef CONFIG_BOARD_HAS_LSE
 #define CONFIG_BOARD_HAS_LSE            1
 #endif
@@ -32,7 +28,8 @@
 #define CONFIG_CLOCK_PLL_N              (30)
 #endif
 
-#include "l4/cfg_clock_default.h"
+#include "periph_cpu.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 

boards/nucleo-l552ze-q/include/periph_conf.h

@@ -20,9 +20,7 @@
 #define PERIPH_CONF_H
 
 /* Add specific clock configuration (HSE, LSE) for this board here */
-#define CLOCK_CORECLOCK_MAX             MHZ(110)
-
-/* Reach 108MHz by by default setting custom PLL_N factor */
+/* Reach 108MHz by default by setting custom PLL_N factor */
 #ifndef CONFIG_CLOCK_PLL_N
 #define CONFIG_CLOCK_PLL_N              27
 #endif
@@ -33,7 +31,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim5.h"

boards/nz32-sc151/include/periph_conf.h

@@ -20,7 +20,7 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_timer_tim5.h"
 
 #ifdef __cplusplus

boards/olimexino-stm32/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/opencm904/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/p-l496g-cell02/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"
 

boards/p-nucleo-wb55/include/periph_conf.h

@@ -20,11 +20,7 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
-#include "periph_cpu.h"
-
 /* Add specific clock configuration (HSE, LSE) for this board here */
-#define CLOCK_CORECLOCK_MAX             MHZ(64)
-
 #ifndef CONFIG_BOARD_HAS_LSE
 #define CONFIG_BOARD_HAS_LSE            1
 #endif
@@ -39,8 +35,8 @@
 #define CLOCK_EXTAHB_DIV    RCC_EXTCFGR_C2HPRE_3
 #define CLOCK_EXTAHB        (CLOCK_CORECLOCK / 2)
 
-#include "l4/cfg_clock_default.h"
-
+#include "periph_cpu.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"

boards/pyboard/include/periph_conf.h

@@ -35,7 +35,7 @@
 #define CLOCK_HSE               MHZ(12)
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_180.h"
+#include "clk_conf.h"
 #include "cfg_usb_otg_fs.h"
 
 #ifdef __cplusplus

boards/spark-core/include/periph_conf.h

@@ -20,7 +20,7 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/stm32f3discovery/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f1f3/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/stm32f429i-disc1/include/periph_conf.h

@@ -30,7 +30,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_180.h"
+#include "clk_conf.h"
 #include "cfg_timer_tim5.h"
 #include "cfg_usb_otg_hs_fs.h"
 

boards/stm32f4discovery/include/periph_conf.h

@@ -26,7 +26,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_180.h"
+#include "clk_conf.h"
 #include "cfg_usb_otg_fs.h"
 
 #ifdef __cplusplus

boards/stm32l0538-disco/include/periph_conf.h

@@ -20,7 +20,7 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
-#include "l0l1/cfg_clock_default.h"
+#include "clk_conf.h"
 
 #ifdef __cplusplus
 extern "C" {

boards/stm32l476g-disco/include/periph_conf.h

@@ -25,7 +25,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_rtt_default.h"
 
 #ifdef __cplusplus

boards/ublox-c030-u201/include/periph_conf.h

@@ -33,7 +33,7 @@
 #define CLOCK_HSE               MHZ(12)
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_180.h"
+#include "clk_conf.h"
 #include "cfg_timer_tim5.h"
 
 #ifdef __cplusplus

boards/weact-f411ce/include/periph_conf.h

@@ -36,7 +36,7 @@
 #define CLOCK_HSE               MHZ(25)
 
 #include "periph_cpu.h"
-#include "f2f4f7/cfg_clock_default_100.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_timer_tim5.h"
 #include "cfg_usb_otg_fs.h"

cpu/stm32/Makefile.include

@@ -84,4 +84,7 @@ $(STM32IRQS_INCLUDE_FILE): $(STM32FAM_INCLUDE_FILE)
 	$(Q)$(RIOTBASE)/cpu/stm32/dist/irqs/gen_irqs.py $(CPU_FAM)
 endif
 
+# Include clock configuration directory
+INCLUDES += -I$(RIOTCPU)/stm32/include/clk
+
 include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/stm32/include/clk/clk_conf.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2020 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup         cpu_stm32
+ * @{
+ *
+ * @file
+ * @brief           Main header for STM32 clock configuration
+ *
+ * @author          Alexandre Abadie <alexandre.abadie@inria.fr>
+*/
+
+#ifndef CLK_CLK_CONF_H
+#define CLK_CLK_CONF_H
+
+#include "kernel_defines.h"
+#include "macros/units.h"
+
+#if defined(CPU_FAM_STM32F0)
+#include "f0/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3)
+#include "f1f3/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
+      defined(CPU_FAM_STM32F7)
+#include "f2f4f7/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32G0)
+#include "g0/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32G4)
+#include "g4/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
+#include "l0l1/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
+      defined(CPU_FAM_STM32WB)
+#include "l4l5wb/cfg_clock_default.h"
+#else
+#error "No clock configuration available"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CLK_CLK_CONF_H */
+/** @} */

cpu/stm32/include/clk/f0/cfg_clock_default.h

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -18,10 +18,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef F0_CFG_CLOCK_DEFAULT_H
-#define F0_CFG_CLOCK_DEFAULT_H
-
-#include "periph_cpu.h"
+#ifndef CLK_F0_CFG_CLOCK_DEFAULT_H
+#define CLK_F0_CFG_CLOCK_DEFAULT_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -134,5 +132,5 @@ extern "C" {
 }
 #endif
 
-#endif /* F0_CFG_CLOCK_DEFAULT_H */
+#endif /* CLK_F0_CFG_CLOCK_DEFAULT_H */
 /** @} */

cpu/stm32/include/clk/f1f3/cfg_clock_default.h

@@ -9,7 +9,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -23,10 +23,8 @@
  *
  */
 
-#ifndef F1F3_CFG_CLOCK_DEFAULT_H
-#define F1F3_CFG_CLOCK_DEFAULT_H
-
-#include "periph_cpu.h"
+#ifndef CLK_F1F3_CFG_CLOCK_DEFAULT_H
+#define CLK_F1F3_CFG_CLOCK_DEFAULT_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -144,5 +142,5 @@ extern "C" {
 }
 #endif
 
-#endif /* F1F3_CFG_CLOCK_DEFAULT_H */
+#endif /* CLK_F1F3_CFG_CLOCK_DEFAULT_H */
 /** @} */

cpu/stm32/include/clk/f2f4f7/cfg_clock_common.h

@@ -9,7 +9,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -20,8 +20,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef F2F4F7_CFG_CLOCK_COMMON_H
-#define F2F4F7_CFG_CLOCK_COMMON_H
+#ifndef CLK_F2F4F7_CFG_CLOCK_COMMON_H
+#define CLK_F2F4F7_CFG_CLOCK_COMMON_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -81,5 +81,5 @@ extern "C" {
 }
 #endif
 
-#endif /* F2F4F7_CFG_CLOCK_COMMON_H */
+#endif /* CLK_F2F4F7_CFG_CLOCK_COMMON_H */
 /** @} */

cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2020 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup         cpu_stm32
+ * @{
+ *
+ * @file
+ * @brief           Main header for STM32F2/F4/F7 clock configuration
+ *
+ * @author          Alexandre Abadie <alexandre.abadie@inria.fr>
+*/
+
+#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_H
+#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_H
+
+#if defined(CPU_FAM_STM32F2)
+#include "f2f4f7/cfg_clock_default_120.h"
+#elif defined(CPU_FAM_STM32F4)
+#if defined(CPU_LINE_STM32F401xC) || defined(CPU_LINE_STM32F401xE)
+#include "f2f4f7/cfg_clock_default_84.h"
+#elif defined(CPU_LINE_STM32F410Cx) || defined(CPU_LINE_STM32F410Rx) || \
+      defined(CPU_LINE_STM32F410Tx) || defined(CPU_LINE_STM32F411xE) || \
+      defined(CPU_LINE_STM32F412Cx) || defined(CPU_LINE_STM32F412Rx) || \
+      defined(CPU_LINE_STM32F412Vx) || defined(CPU_LINE_STM32F412Zx) || \
+      defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)
+#include "f2f4f7/cfg_clock_default_100.h"
+#elif defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
+      defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
+      defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F437xx) || \
+      defined(CPU_LINE_STM32F429xx) || defined(CPU_LINE_STM32F439xx) || \
+      defined(CPU_LINE_STM32F446xx) || defined(CPU_LINE_STM32F469xx) || \
+      defined(CPU_LINE_STM32F479xx)
+#include "f2f4f7/cfg_clock_default_180.h"
+#else
+#error "No clock configuration available for this F4 line"
+#endif
+#elif defined(CPU_FAM_STM32F7)
+#include "f2f4f7/cfg_clock_default_216.h"
+#else
+#error "No clock configuration available for this family"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_H */
+/** @} */

cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h

@@ -9,7 +9,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -20,8 +20,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef F2F4F7_CFG_CLOCK_DEFAULT_100_H
-#define F2F4F7_CFG_CLOCK_DEFAULT_100_H
+#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H
+#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H
 
 #include "f2f4f7/cfg_clock_common.h"
 
@@ -96,5 +96,5 @@ extern "C" {
 #error "SYSCLK cannot exceed 100MHz"
 #endif
 
-#endif /* F2F4F7_CFG_CLOCK_DEFAULT_100_H */
+#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H */
 /** @} */

cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h

@@ -9,7 +9,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -20,8 +20,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef F2F4F7_CFG_CLOCK_DEFAULT_120_H
-#define F2F4F7_CFG_CLOCK_DEFAULT_120_H
+#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H
+#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H
 
 #include "f2f4f7/cfg_clock_common.h"
 
@@ -74,5 +74,5 @@ extern "C" {
 #error "SYSCLK cannot exceed 120MHz"
 #endif
 
-#endif /* F2F4F7_CFG_CLOCK_DEFAULT_120_H */
+#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H */
 /** @} */

cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h

@@ -9,7 +9,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -20,8 +20,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef F2F4F7_CFG_CLOCK_DEFAULT_180_H
-#define F2F4F7_CFG_CLOCK_DEFAULT_180_H
+#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
+#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
 
 #include "f2f4f7/cfg_clock_common.h"
 
@@ -108,5 +108,5 @@ extern "C" {
 #error "SYSCLK cannot exceed 180MHz"
 #endif
 
-#endif /* F2F4F7_CFG_CLOCK_DEFAULT_180_H */
+#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H */
 /** @} */

cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h

@@ -9,7 +9,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -20,8 +20,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef F2F4F7_CFG_CLOCK_DEFAULT_216_H
-#define F2F4F7_CFG_CLOCK_DEFAULT_216_H
+#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
+#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
 
 #include "f2f4f7/cfg_clock_common.h"
 
@@ -83,5 +83,5 @@ extern "C" {
 #error "SYSCLK cannot exceed 216MHz"
 #endif
 
-#endif /* F2F4F7_CFG_CLOCK_DEFAULT_216_H */
+#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H */
 /** @} */

cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h

@@ -9,7 +9,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -20,8 +20,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef F2F4F7_CFG_CLOCK_DEFAULT_84_H
-#define F2F4F7_CFG_CLOCK_DEFAULT_84_H
+#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
+#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
 
 #include "f2f4f7/cfg_clock_common.h"
 
@@ -77,5 +77,5 @@ extern "C" {
 #error "SYSCLK cannot exceed 84MHz"
 #endif
 
-#endif /* F2F4F7_CFG_CLOCK_DEFAULT_84_H */
+#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H */
 /** @} */

cpu/stm32/include/clk/f2f4f7/cfg_clock_values.h

@@ -9,7 +9,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -20,8 +20,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef F2F4F7_CFG_CLOCK_VALUES_H
-#define F2F4F7_CFG_CLOCK_VALUES_H
+#ifndef CLK_F2F4F7_CFG_CLOCK_VALUES_H
+#define CLK_F2F4F7_CFG_CLOCK_VALUES_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -62,5 +62,5 @@ extern "C" {
 }
 #endif
 
-#endif /* F2F4F7_CFG_CLOCK_VALUES_H */
+#endif /* CLK_F2F4F7_CFG_CLOCK_VALUES_H */
 /** @} */

cpu/stm32/include/clk/g0/cfg_clock_default.h

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -20,10 +20,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef G0_CFG_CLOCK_DEFAULT_H
-#define G0_CFG_CLOCK_DEFAULT_H
-
-#include "periph_cpu.h"
+#ifndef CLK_G0_CFG_CLOCK_DEFAULT_H
+#define CLK_G0_CFG_CLOCK_DEFAULT_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -133,5 +131,5 @@ extern "C" {
 }
 #endif
 
-#endif /* G0_CFG_CLOCK_DEFAULT_H */
+#endif /* CLK_G0_CFG_CLOCK_DEFAULT_H */
 /** @} */

cpu/stm32/include/clk/g4/cfg_clock_default.h

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -16,10 +16,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef G4_CFG_CLOCK_DEFAULT_H
-#define G4_CFG_CLOCK_DEFAULT_H
-
-#include "periph_cpu.h"
+#ifndef CLK_G4_CFG_CLOCK_DEFAULT_H
+#define CLK_G4_CFG_CLOCK_DEFAULT_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -125,5 +123,5 @@ extern "C" {
 }
 #endif
 
-#endif /* G4_CFG_CLOCK_DEFAULT_H */
+#endif /* CLK_G4_CFG_CLOCK_DEFAULT_H */
 /** @} */

cpu/stm32/include/clk/l0l1/cfg_clock_default.h

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -16,8 +16,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef L0L1_CFG_CLOCK_DEFAULT_H
-#define L0L1_CFG_CLOCK_DEFAULT_H
+#ifndef CLK_L0L1_CFG_CLOCK_DEFAULT_H
+#define CLK_L0L1_CFG_CLOCK_DEFAULT_H
 
 #include "periph_cpu.h"
 
@@ -156,5 +156,5 @@ extern "C" {
 }
 #endif
 
-#endif /* L0L1_CFG_CLOCK_DEFAULT_H */
+#endif /* CLK_L0L1_CFG_CLOCK_DEFAULT_H */
 /** @} */

cpu/stm32/include/clk/l4l5wb/cfg_clock_default.h

@@ -8,7 +8,7 @@
  */
 
 /**
- * @ingroup     boards_common_stm32
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -18,10 +18,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef L4_CFG_CLOCK_DEFAULT_H
-#define L4_CFG_CLOCK_DEFAULT_H
-
-#include "periph_cpu.h"
+#ifndef CLK_L4L5WB_CFG_CLOCK_DEFAULT_H
+#define CLK_L4L5WB_CFG_CLOCK_DEFAULT_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -169,9 +167,22 @@ extern "C" {
  */
 #define CLOCK_CORECLOCK                 \
         ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
-#ifndef CLOCK_CORECLOCK_MAX
+
+/* Set max allowed sysclk */
+#if defined(CPU_FAM_STM32WB)
+#define CLOCK_CORECLOCK_MAX             MHZ(64)
+#elif defined(CPU_FAM_STM32L5)
+#define CLOCK_CORECLOCK_MAX             MHZ(110)
+#elif defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \
+      defined(CPU_LINE_STM32L4Q5xx) || defined(CPU_LINE_STM32L4R5xx) || \
+      defined(CPU_LINE_STM32L4R7xx) || defined(CPU_LINE_STM32L4R9xx) || \
+      defined(CPU_LINE_STM32L4S5xx) || defined(CPU_LINE_STM32L4S7xx) || \
+      defined(CPU_LINE_STM32L4S9xx)
+#define CLOCK_CORECLOCK_MAX             MHZ(120)
+#else /* all the other L4 */
 #define CLOCK_CORECLOCK_MAX             MHZ(80)
 #endif
+
 #if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
 #if CLOCK_CORECLOCK_MAX == MHZ(64)
 #error "SYSCLK cannot exceed 64MHz"
@@ -202,5 +213,5 @@ extern "C" {
 }
 #endif
 
-#endif /* L4_CFG_CLOCK_DEFAULT_H */
+#endif /* CLK_L4L5WB_CFG_CLOCK_DEFAULT_H */
 /** @} */