mirror of
https://github.com/RIOT-OS/RIOT.git
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cpu/lm4f120: Update timer macros to timer_config_t
This commit is contained in:
MrKevinWeiss
parent
db6355fb13
commit
7c3082a7a3
@ -40,35 +40,32 @@ extern "C" {
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/** @} */
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/**
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* @name Timer configuration
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* @name Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (2U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 1
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#define TIMER_IRQ_PRIO 1
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static const timer_conf_t timer_config[] = {
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{
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.dev = WTIMER0_BASE,
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.max = 0xffffffff,
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.irqn = Timer0A_IRQn,
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.sysctl = SYSCTL_PERIPH_WTIMER0,
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.intbase = INT_WTIMER0A,
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.channels = 1
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},
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{
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.dev = WTIMER1_BASE,
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.max = 0xffffffff,
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.irqn = Timer1A_IRQn,
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.sysctl = SYSCTL_PERIPH_WTIMER1,
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.intbase = INT_WTIMER1A,
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.channels = 1
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},
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};
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/* Timer 0 configuration
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*
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* WTIMER0 is a 32/64bits timer.
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* We use timer_a as TIMER_0
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*/
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#define TIMER_0_CHANNELS 1
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#define TIMER_0_MAX_VALUE (0xffffffff)
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#define TIMER_0_ISR isr_wtimer0a
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#define TIMER_0_IRQ_CHAN Timer0A_IRQn
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/* Timer 1 configuration
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*
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* WTIMER1 is a 32/64bits timer.
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* We use timer_a as TIMER_1
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*/
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#define TIMER_1_CHANNELS 1
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#define TIMER_1_MAX_VALUE (0xffffffff)
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#define TIMER_1_ISR isr_wtimer1a
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#define TIMER_1_IRQ_CHAN Timer1A_IRQn
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/** @} */
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/**
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* @name UART configuration
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@ -21,7 +21,6 @@
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include "cpu.h"
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#ifdef __cplusplus
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@ -34,7 +33,7 @@ extern "C" {
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*/
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#define HAVE_GPIO_T
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typedef uint32_t gpio_t;
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#define GPIO_PIN(x,y) ((gpio_t)((x<<4) | y))
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#define GPIO_PIN(x, y) ((gpio_t)((x<<4) | y))
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/** @} */
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#ifndef DOXYGEN
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@ -106,6 +105,18 @@ typedef enum {
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} adc_res_t;
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#endif /* ndef DOXYGEN */
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/**
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* @brief Define timer configuration values
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*/
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typedef struct {
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uint32_t dev; /**< Address of timer base */
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uint32_t max; /**< Max tick value of timer */
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int irqn; /**< Number of the higher timer IRQ channel */
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uint32_t sysctl; /**< Address of timer system control */
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uint32_t intbase; /**< Interrupt base of timer */
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int channels; /**< Number of channels for the timer */
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} timer_conf_t;
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/**
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* @brief Override SPI hardware chip select macro
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*
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@ -30,315 +30,190 @@
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#include "debug.h"
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/**
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* @brief Struct holding the configuration data
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* @brief Interrupt context for each configured timer
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* @{
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*/
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typedef struct {
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timer_cb_t cb; /**< timeout callback */
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void *arg; /**< argument to the callback */
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unsigned int divisor; /**< software clock divisor */
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} timer_conf_t;
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static timer_conf_t config[TIMER_NUMOF];
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static timer_isr_ctx_t isr_ctx[TIMER_NUMOF];
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static uint32_t isr_divisor[TIMER_NUMOF];
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/**@}*/
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#include "hw_timer.h"
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/* enable timer interrupts */
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static inline void _irq_enable(tim_t dev);
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static inline void _irq_enable(tim_t tim);
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/* Missing from driverlib */
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static inline unsigned long
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PRIV_TimerPrescaleSnapshotGet(unsigned long ulbase, unsigned long ultimer) {
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return((ultimer == TIMER_A) ? HWREG(ulbase + TIMER_O_TAPS) :
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HWREG(ulbase + TIMER_O_TBPS));
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return ((ultimer == TIMER_A) ? HWREG(ulbase + TIMER_O_TAPS) :
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HWREG(ulbase + TIMER_O_TBPS));
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}
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static inline unsigned long long _scaled_to_ll_value(unsigned int uncorrected, unsigned int divisor)
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static inline uint64_t _scaled_to_ll_value(uint32_t uncorrected,
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uint32_t divisor)
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{
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const unsigned long long scaledv = (unsigned long long) uncorrected * divisor;
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const uint64_t scaledv = (uint64_t) uncorrected * divisor;
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return scaledv;
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}
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static inline unsigned int _llvalue_to_scaled_value(unsigned long long corrected, unsigned int divisor)
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static inline uint32_t _llvalue_to_scaled_value(uint64_t corrected,
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uint32_t divisor)
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{
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const unsigned long long scaledv = corrected / divisor;
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const uint64_t scaledv = corrected / divisor;
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return scaledv;
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}
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int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
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int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
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{
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if (dev >= TIMER_NUMOF){
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if (tim >= TIMER_NUMOF){
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return -1;
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}
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const timer_conf_t *cfg = &timer_config[tim];
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config[dev].cb = cb;
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config[dev].arg = arg;
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config[dev].divisor = ROM_SysCtlClockGet() / freq;
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isr_ctx[tim].cb = cb;
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isr_ctx[tim].arg = arg;
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isr_divisor[tim] = ROM_SysCtlClockGet() / freq;
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unsigned int sysctl_timer;
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unsigned int timer_base;
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unsigned int timer_side = TIMER_A;
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unsigned int timer_cfg = TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC_UP | TIMER_TAMR_TAMIE;
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unsigned int timer_max_val = 0;
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unsigned int timer_cfg = TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC_UP |
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TIMER_TAMR_TAMIE;
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unsigned int timer_intbit = TIMER_TIMA_TIMEOUT | TIMER_TIMA_MATCH;
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switch(dev){
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#if TIMER_0_EN
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case TIMER_0:
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sysctl_timer = SYSCTL_PERIPH_WTIMER0;
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timer_base = WTIMER0_BASE;
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timer_max_val = TIMER_0_MAX_VALUE;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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sysctl_timer = SYSCTL_PERIPH_WTIMER1;
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timer_base = WTIMER1_BASE;
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timer_max_val = TIMER_1_MAX_VALUE;
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break;
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#endif
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default:
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return -1; /* unreachable */
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}
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ROM_SysCtlPeripheralEnable(cfg->sysctl);
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ROM_TimerDisable(cfg->dev, timer_side);
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ROM_TimerConfigure(cfg->dev, timer_cfg);
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ROM_SysCtlPeripheralEnable(sysctl_timer);
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uint64_t val_max = _scaled_to_ll_value(cfg->max, isr_divisor[tim]);
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ROM_TimerDisable(timer_base, timer_side);
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ROM_TimerConfigure(timer_base, timer_cfg);
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ROM_TimerPrescaleSet(cfg->dev, timer_side, val_max >> 32);
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ROM_TimerLoadSet(cfg->dev, timer_side, val_max & 0xFFFFFFFF);
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ROM_TimerIntClear(cfg->dev, timer_intbit);
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unsigned long long lltimer_val_max = _scaled_to_ll_value(timer_max_val, config[dev].divisor);
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ROM_TimerIntEnable(cfg->dev, timer_intbit);
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ROM_TimerPrescaleSet(timer_base, timer_side, lltimer_val_max >> 32);
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ROM_TimerLoadSet(timer_base, timer_side, lltimer_val_max & 0xFFFFFFFF);
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ROM_TimerIntClear(timer_base, timer_intbit);
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ROM_TimerIntEnable(timer_base, timer_intbit);
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_irq_enable(dev);
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timer_start(dev);
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_irq_enable(tim);
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timer_start(tim);
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return 0;
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}
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int timer_set_absolute(tim_t dev, int channel, unsigned int value)
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int timer_set_absolute(tim_t tim, int channel, unsigned int value)
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{
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(void) channel;
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if (tim >= TIMER_NUMOF || channel >= timer_config[tim].channels) {
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return -1;
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}
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const timer_conf_t *cfg = &timer_config[tim];
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unsigned int timer_base;
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unsigned int timer_side = TIMER_A;
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unsigned long long scaledv;
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if (dev >= TIMER_NUMOF){
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return -1;
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}
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ROM_TimerDisable(cfg->dev, timer_side);
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switch(dev){
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#if TIMER_0_EN
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case TIMER_0:
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timer_base = WTIMER0_BASE;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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timer_base = WTIMER1_BASE;
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break;
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#endif
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default:
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return -1; /* unreachable */
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break;
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}
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ROM_TimerDisable(timer_base, timer_side);
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scaledv = _scaled_to_ll_value(value, config[dev].divisor);
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scaledv = _scaled_to_ll_value(value, isr_divisor[tim]);
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if (scaledv>>32){
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ROM_TimerPrescaleMatchSet(timer_base, timer_side, scaledv >> 32);
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ROM_TimerPrescaleMatchSet(cfg->dev, timer_side, scaledv >> 32);
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}
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else {
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ROM_TimerPrescaleMatchSet(timer_base, timer_side, 0);
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ROM_TimerPrescaleMatchSet(cfg->dev, timer_side, 0);
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}
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ROM_TimerMatchSet(timer_base, timer_side, (unsigned long) (scaledv & 0xFFFFFFFF));
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ROM_TimerEnable(timer_base, timer_side);
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ROM_TimerMatchSet(cfg->dev, timer_side, (uint32_t) (scaledv & 0xFFFFFFFF));
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ROM_TimerEnable(cfg->dev, timer_side);
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return 0;
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}
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int timer_clear(tim_t dev, int channel)
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int timer_clear(tim_t tim, int channel)
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{
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(void) channel;
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unsigned int timer_intbit = TIMER_TIMA_TIMEOUT;
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unsigned int timer_base;
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if (dev >= TIMER_NUMOF){
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if (tim >= TIMER_NUMOF || channel >= timer_config[tim].channels) {
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return -1;
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}
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switch(dev){
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#if TIMER_0_EN
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case TIMER_0:
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timer_base = WTIMER0_BASE;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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timer_base = WTIMER1_BASE;
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break;
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#endif
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default:
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return -1; /* unreachable */
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break;
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}
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ROM_TimerIntClear(timer_base, timer_intbit);
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ROM_TimerIntClear(timer_config[tim].dev, TIMER_TIMA_TIMEOUT);
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return 0;
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}
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unsigned int timer_read(tim_t dev)
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unsigned int timer_read(tim_t tim)
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{
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unsigned int timer_base;
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unsigned int timer_side = TIMER_A;
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unsigned long long high_bits, high_bits_dup;
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unsigned long long low_bits;
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unsigned long long total;
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unsigned int scaled_value;
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if (dev >= TIMER_NUMOF){
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if (tim >= TIMER_NUMOF){
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return -1;
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}
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switch(dev){
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#if TIMER_0_EN
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case TIMER_0:
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timer_base = WTIMER0_BASE;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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timer_base = WTIMER1_BASE;
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break;
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#endif
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default:
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return -1; /* unreachable */
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break;
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}
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const timer_conf_t *cfg = &timer_config[tim];
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/* handle overflow happening between the 2 register reads */
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do {
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high_bits = ((unsigned long long)PRIV_TimerPrescaleSnapshotGet(timer_base, timer_side)) << 32;
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low_bits = (unsigned long long)ROM_TimerValueGet(timer_base, timer_side);
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high_bits_dup = ((unsigned long long)PRIV_TimerPrescaleSnapshotGet(timer_base, timer_side)) << 32;
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high_bits = ((uint64_t)PRIV_TimerPrescaleSnapshotGet(cfg->dev,
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timer_side)) << 32;
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low_bits = (uint64_t)ROM_TimerValueGet(cfg->dev, timer_side);
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high_bits_dup = ((uint64_t)PRIV_TimerPrescaleSnapshotGet(cfg->dev,
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timer_side)) << 32;
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} while (high_bits != high_bits_dup);
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total = high_bits + low_bits;
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DEBUG("Combined %lx:%lx\n", (unsigned long) (total>>32), (unsigned long) (total & 0xFFFFFFFF));
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DEBUG("Combined %lx:%lx\n", (uint32_t)(total>>32),
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(uint32_t)(total & 0xFFFFFFFF));
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scaled_value = _llvalue_to_scaled_value(total, config[dev].divisor);
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scaled_value = _llvalue_to_scaled_value(total, isr_divisor[tim]);
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return scaled_value;
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}
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void timer_start(tim_t dev)
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void timer_start(tim_t tim)
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{
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unsigned int timer_base;
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unsigned int timer_side = TIMER_A;
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if (dev >= TIMER_NUMOF){
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return ;
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}
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switch(dev){
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#if TIMER_0_EN
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case TIMER_0:
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timer_base = WTIMER0_BASE;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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timer_base = WTIMER1_BASE;
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break;
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#endif
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default:
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return; /* unreachable */
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}
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ROM_TimerEnable(timer_base, timer_side);
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}
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void timer_stop(tim_t dev)
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{
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unsigned int timer_base;
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unsigned int timer_side = TIMER_A;
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if (dev >= TIMER_NUMOF){
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if (tim >= TIMER_NUMOF){
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return;
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}
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switch(dev){
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#if TIMER_0_EN
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case TIMER_0:
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timer_base = WTIMER0_BASE;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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timer_base = WTIMER1_BASE;
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break;
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#endif
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default:
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return; /* unreachable */
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}
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ROM_TimerDisable(timer_base, timer_side);
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ROM_TimerEnable(timer_config[tim].dev, TIMER_A);
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}
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static inline void _irq_enable(tim_t dev)
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void timer_stop(tim_t tim)
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{
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unsigned int timer_intbase;
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if (dev >= TIMER_NUMOF){
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if (tim >= TIMER_NUMOF){
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return;
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}
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switch(dev){
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#if TIMER_0_EN
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case TIMER_0:
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timer_intbase = INT_WTIMER0A;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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timer_intbase = INT_WTIMER1A;
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break;
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#endif
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default:
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return; /* unreachable */
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}
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ROM_IntPrioritySet(timer_intbase, 32);
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ROM_IntEnable(timer_intbase);
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ROM_TimerDisable(timer_config[tim].dev, TIMER_A);
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}
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#if TIMER_0_EN
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void isr_wtimer0a(void)
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static inline void _irq_enable(tim_t tim)
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{
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if (tim >= TIMER_NUMOF){
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return;
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}
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ROM_IntPrioritySet(timer_config[tim].intbase, 32);
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ROM_IntEnable(timer_config[tim].intbase);
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}
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void _isr_timer(tim_t tim)
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{
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/* Clears both IT */
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ROM_TimerIntClear(WTIMER0_BASE, TIMER_TIMA_TIMEOUT | TIMER_TIMA_MATCH);
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config[TIMER_0].cb(config[TIMER_0].arg, 0);
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ROM_TimerIntClear(timer_config[tim].dev,
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TIMER_TIMA_TIMEOUT | TIMER_TIMA_MATCH);
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isr_ctx[tim].cb(isr_ctx[tim].arg, 0);
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cortexm_isr_end();
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}
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#endif /* TIMER_0_EN */
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#if TIMER_1_EN
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void isr_wtimer1a(void)
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#ifdef TIMER_0_ISR
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void TIMER_0_ISR(void)
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{
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ROM_TimerIntClear(WTIMER1_BASE, TIMER_TIMA_TIMEOUT | TIMER_TIMA_MATCH);
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config[TIMER_1].cb(config[TIMER_0].arg, 0);
|
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cortexm_isr_end();
|
||||
_isr_timer(0);
|
||||
}
|
||||
#endif /* TIMER_1_EN */
|
||||
#endif /* TIMER_0_ISR */
|
||||
|
||||
#ifdef TIMER_1_ISR
|
||||
void TIMER_1_ISR(void)
|
||||
{
|
||||
_isr_timer(1);
|
||||
}
|
||||
#endif /* TIMER_1_ISR */
|
||||
/** @} */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user