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cpu: boards: stm32l4/wb: use IS_USED for clock where possible

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This commit is contained in:
Alexandre Abadie 2020-09-01 16:04:40 +02:00
parent 79e6d9df85
commit 9dd20c0ccb
No known key found for this signature in database
GPG Key ID: 1C919A403CAE1405
12 changed files with 85 additions and 61 deletions
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2
boards/b-l475e-iot01a/include/periph_conf.h
View File

@ -21,7 +21,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "periph_cpu.h"

86
boards/common/stm32/include/l4/cfg_clock_default.h
View File

@ -34,58 +34,62 @@ extern "C" {
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
#define CONFIG_USE_CLOCK_PLL (0)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_MSI
#define CONFIG_USE_CLOCK_MSI (0)
#define CONFIG_USE_CLOCK_MSI 0
#endif /* CONFIG_USE_CLOCK_MSI */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE (0)
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI (0)
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if CONFIG_USE_CLOCK_PLL && \
(CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if CONFIG_USE_CLOCK_MSI && \
(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSI || CONFIG_USE_CLOCK_HSE)
#if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use MSI as clock source with other clock configurations"
#endif
#if CONFIG_USE_CLOCK_HSE && \
(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSI)
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if CONFIG_USE_CLOCK_HSI && \
(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE)
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE (0)
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(8)
#endif
#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#error "HSE clock frequency must be between 4MHz and 48MHz"
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (0)
#define CONFIG_BOARD_HAS_LSE 0
#endif
#if CONFIG_BOARD_HAS_LSE
#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
#define CLOCK_LSE (1)
#else
#define CLOCK_LSE (0)
@ -100,21 +104,21 @@ extern "C" {
/* The following parameters configure a 80MHz system clock with PLL as input clock */
#ifndef CONFIG_CLOCK_PLL_SRC_MSI
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
CONFIG_BOARD_HAS_HSE
#define CONFIG_CLOCK_PLL_SRC_MSI (0)
IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CONFIG_CLOCK_PLL_SRC_MSI 0
#else
#define CONFIG_CLOCK_PLL_SRC_MSI (1) /* Use MSI an input clock by default */
#define CONFIG_CLOCK_PLL_SRC_MSI 1 /* Use MSI an input clock by default */
#endif
#endif /* CONFIG_CLOCK_PLL_SRC_MSI */
#ifndef CONFIG_CLOCK_PLL_SRC_HSE
#if CONFIG_BOARD_HAS_HSE
#define CONFIG_CLOCK_PLL_SRC_HSE (1)
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CONFIG_CLOCK_PLL_SRC_HSE 1
#else
#define CONFIG_CLOCK_PLL_SRC_HSE (0)
#define CONFIG_CLOCK_PLL_SRC_HSE 0
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_SRC_HSI
#define CONFIG_CLOCK_PLL_SRC_HSI (0)
#define CONFIG_CLOCK_PLL_SRC_HSI 0
#endif
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (6)
@ -126,26 +130,40 @@ extern "C" {
#define CONFIG_CLOCK_PLL_R (2)
#endif
#if CONFIG_USE_CLOCK_HSI
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif CONFIG_USE_CLOCK_HSE
#if CONFIG_BOARD_HAS_HSE == 0
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif CONFIG_USE_CLOCK_MSI
#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
#elif CONFIG_USE_CLOCK_PLL
#if CONFIG_CLOCK_PLL_SRC_MSI
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI)
#elif CONFIG_CLOCK_PLL_SRC_HSE
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CONFIG_CLOCK_PLL_SRC_ */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
/* PLL configuration: make sure your values are legit!
*
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
* with:
* PLL_IN: input clock, HSE or MSI
* M: pre-divider, allowed range: [1:8]
* N: multiplier, allowed range: [8:86]
* R: post-divider, allowed range: [2:8]
*
* Also the following constraints need to be met:
* (PLL_IN / M) -> [4MHz:16MHz]
* (PLL_IN / M) * N -> [64MHz:344MHz]
* CORECLOCK -> 64MHz, 80MHZ or 120MHz MAX!
*/
#define CLOCK_CORECLOCK \
((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
#ifndef CLOCK_CORECLOCK_MAX
@ -164,16 +182,16 @@ extern "C" {
#endif /* CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX */
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_AHB CLOCK_CORECLOCK /* max: 80MHz */
#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 64/80/120MHz */
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4)
#endif
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 80MHz */
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 64/80/120MHz */
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (2)
#endif
#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 80MHz */
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 64/80/120MHz */
#ifdef __cplusplus
}

2
boards/nucleo-l412kb/include/periph_conf.h
View File

@ -25,7 +25,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "periph_cpu.h"

2
boards/nucleo-l432kc/include/periph_conf.h
View File

@ -23,7 +23,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "periph_cpu.h"

2
boards/nucleo-l433rc/include/periph_conf.h
View File

@ -21,7 +21,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "periph_cpu.h"

2
boards/nucleo-l452re/include/periph_conf.h
View File

@ -27,7 +27,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "periph_cpu.h"

2
boards/nucleo-l476rg/include/periph_conf.h
View File

@ -25,7 +25,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "periph_cpu.h"

2
boards/nucleo-l496zg/include/periph_conf.h
View File

@ -21,7 +21,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "periph_cpu.h"

2
boards/p-l496g-cell02/include/periph_conf.h
View File

@ -21,7 +21,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "periph_cpu.h"

4
boards/p-nucleo-wb55/include/periph_conf.h
View File

@ -26,11 +26,11 @@
#define CLOCK_CORECLOCK_MAX MHZ(64)
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE (1)
#define CONFIG_BOARD_HAS_HSE 1
#endif
#define CLOCK_HSE MHZ(32)

2
boards/stm32l476g-disco/include/periph_conf.h
View File

@ -21,7 +21,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "periph_cpu.h"

38
cpu/stm32/stmclk/stmclk_l4wb.c
View File

@ -46,9 +46,9 @@
* @{
*/
/* figure out which input to use */
#if CONFIG_CLOCK_PLL_SRC_MSI
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
#define PLL_SRC RCC_PLLCFGR_PLLSRC_MSI
#elif CONFIG_CLOCK_PLL_SRC_HSE && CONFIG_BOARD_HAS_HSE
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
#else
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
@ -222,15 +222,22 @@ void stmclk_init_sysclk(void)
(instead of MSIRANGE in the RCC_CR) */
RCC->CR = (RCC_CR_HSION);
if (CONFIG_USE_CLOCK_HSE) {
/* Enable the HSE clock only when it's provided by the board and required:
- Use HSE as system clock
- Use HSE as PLL input clock
*/
if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) &&
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE))) {
RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) {}
}
if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
/* Select HSE as system clock and configure the different prescalers */
RCC->CFGR &= ~RCC_CFGR_SW;
RCC->CFGR |= RCC_CFGR_SW_HSE;
}
else if (CONFIG_USE_CLOCK_MSI) {
else if (IS_ACTIVE(CONFIG_USE_CLOCK_MSI)) {
#if defined(CPU_FAM_STM32WB)
RCC->CR |= (CLOCK_MSIRANGE | RCC_CR_MSION);
#else
@ -245,14 +252,8 @@ void stmclk_init_sysclk(void)
/* Select MSI as system clock and configure the different prescalers */
RCC->CFGR = (RCC_CFGR_SW_MSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
}
else if (CONFIG_USE_CLOCK_PLL) {
if (CONFIG_BOARD_HAS_HSE && CONFIG_CLOCK_PLL_SRC_HSE) {
/* if configured, we need to enable the HSE clock now */
RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) {}
}
if (CONFIG_CLOCK_PLL_SRC_MSI) {
else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
if (IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)) {
/* reset clock to MSI with 48MHz, disables all other clocks */
#if defined(CPU_FAM_STM32WB)
RCC->CR |= (CLOCK_MSIRANGE | RCC_CR_MSION);
@ -261,7 +262,7 @@ void stmclk_init_sysclk(void)
#endif
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
if (CONFIG_BOARD_HAS_LSE) {
if (IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
/* configure the low speed clock domain */
stmclk_enable_lfclk();
/* now we can enable the MSI PLL mode to enhance accuracy of the MSI */
@ -285,17 +286,22 @@ void stmclk_init_sysclk(void)
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
}
stmclk_disable_hsi();
irq_restore(is);
if (!IS_ACTIVE(CONFIG_USE_CLOCK_HSI) ||
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI))) {
/* Disable HSI only if not used */
stmclk_disable_hsi();
}
if (IS_USED(MODULE_PERIPH_RTT)) {
/* Ensure LPTIM1 clock source (LSI or LSE) is correctly reset when initializing
the clock, this is particularly useful after waking up from deep sleep */
if (CONFIG_BOARD_HAS_LSE) {
if (IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1;
}
else {
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0;
}
}
irq_restore(is);
}