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cpu/saml1x: add NVM User Page Mapping

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This commit is contained in:
Benjamin Valentin 2020-07-12 16:42:34 +02:00
parent fecc5bdcff
commit 360c0b27fc
1 changed files with 49 additions and 0 deletions
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49
cpu/saml1x/include/periph_cpu.h
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@ -91,6 +91,55 @@ static const gpio_t rtc_tamper_pins[RTC_NUM_OF_TAMPERS] = {
GPIO_PIN(PA, 17)
};
/**
* @brief NVM User Row Mapping - Dedicated Entries
* Config values will be applied at power-on.
* @{
*/
struct sam0_aux_cfg_mapping {
/* config word 0 */
uint32_t secure_region_unlock : 3; /**< NVM Secure Region UnLock Bits */
uint32_t non_secure_region_unlock : 3; /**< NVM Non-Secure Region UnLock Bits */
uint32_t reserved_0 : 1; /**< Reserved */
uint32_t bod33_level : 6; /**< BOD33 threshold level at power-on. */
uint32_t bod33_disable : 1; /**< BOD33 Disable at power-on. */
uint32_t bod33_action : 2; /**< BOD33 Action at power-on. */
const uint32_t bod12_calibration : 9; /**< Factory settings - do not change. */
uint32_t wdt_run_standby : 1; /**< WDT Runstdby at power-on */
uint32_t wdt_enable : 1; /**< WDT Enable at power-on. */
uint32_t wdt_always_on : 1; /**< WDT Always-On at power-on. */
uint32_t wdt_period : 4; /**< WDT Period at power-on. */
/* config word 1 */
uint32_t wdt_window : 4; /**< WDT Window at power-on. */
uint32_t wdt_ewoffset : 4; /**< WDT Early Warning Interrupt Offset */
uint32_t wdt_window_enable : 1; /**< WDT Window mode enabled on power-on */
uint32_t bod33_hysteresis : 1; /**< BOD33 Hysteresis configuration */
uint32_t reserved_1 : 1; /**< Reserved */
uint32_t ram_execute_never : 1; /**< RAM is eXecute Never */
uint32_t data_execute_never : 1; /**< Data Flash is eXecute Never */
uint32_t reserved_2 : 19; /**< Reserved */
/* config word 2 */
uint32_t secure_flash_as_size : 8; /**< Secure Flash (AS region) Size = AS*0x100 */
uint32_t nsc_size : 6; /**< Non-Secure Callable Flash (APPLICATION region) Size = ANSC*0x20 */
uint32_t reserved_3 : 2; /**< Reserved */
uint32_t secure_flash_data_size : 4; /**< Secure Data Flash Size = DS*0x100 */
uint32_t reserved_4 : 4; /**< Reserved */
uint32_t secure_ram_size : 7; /**< Secure SRAM Size = RS*0x80 */
uint32_t reserved_5 : 1; /**< Reserved */
/* config word 3 */
uint32_t user_row_write_enable : 1; /**< User Row Write Enable */
uint32_t reserved_6 : 31; /**< Reserved */
/* config word 4 */
uint32_t nonsec_a; /**< Peripherals Non-Secure Status Fuses for Bridge A */
/* config word 5 */
uint32_t nonsec_b; /**< Peripherals Non-Secure Status Fuses for Bridge B */
/* config word 6 */
uint32_t nonsec_c; /**< Peripherals Non-Secure Status Fuses for Bridge C */
/* config word 7 */
uint32_t user_crc; /**< CRC of NVM User Row bits 223:64 (words 2…6) */
};
/** @} */
#ifdef __cplusplus
}
#endif