RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity

cpu/lm4f120: Remove dev_enums dependency

Browse Source
This commit is contained in:
MrKevinWeiss 2020-08-31 13:34:15 +02:00
parent adb0bcab47
commit 11465c941d
2 changed files with 29 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
boards/ek-lm4f120xl/include/periph_conf.h
View File

@ -73,10 +73,9 @@ extern "C" {
* @{
*/
#define UART_NUMOF (1U)
#define UART_0_EN 1
#define UART_1_EN 0
#define UART_IRQ_PRIO 1
#define UART_CLK ROM_SysCtlClockGet() /* UART clock runs with 40MHz */
/* UART clock runs with 40MHz */
#define UART_CLK ROM_SysCtlClockGet()
/* UART 0 device configuration */
#define UART_0_DEV UART0_BASE
#define UART_0_CLK (40000000)
@ -86,12 +85,6 @@ extern "C" {
#define UART_0_PORT GPIOA
#define UART_0_TX_PIN UART_PA1_U0TX
#define UART_0_RX_PIN UART_PA0_U0RX
/* UART 1 device configuration */
#define UART_1_DEV UART1_BASE
#define UART_1_CLK (40000000)
#define UART_1_IRQ_CHAN UART1_IRQn
#define UART_1_ISR isr_uart1
/** @} */
/**

64
cpu/lm4f120/periph/uart.c
View File

@ -26,6 +26,9 @@
#include "periph/uart.h"
#include "periph_conf.h"
/* The only implemented UART device number for this cpu. */
#define _UART_DEV_NUM 0
/**
* @brief UART device configurations
*/
@ -39,14 +42,16 @@ static int init_base(uart_t uart, uint32_t baudrate);
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
/* Check the arguments */
assert(uart == 0);
/* Only one UART is supported, assert that is what is used. */
assert(uart == _UART_DEV_NUM);
(void) uart;
/* Check to make sure the UART peripheral is present */
if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_UART0)){
if (!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_UART0)) {
return UART_NODEV;
}
int res = init_base(uart, baudrate);
if(res != UART_OK){
if (res != UART_OK) {
return res;
}
@ -54,35 +59,21 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
config[uart].rx_cb = rx_cb;
config[uart].arg = arg;
/* ulBase = g_ulUARTBase[uart]; */
switch (uart){
#if UART_0_EN
case UART_0:
ROM_UARTTxIntModeSet(UART0_BASE, UART_TXINT_MODE_EOT);
ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
ROM_UARTFIFOEnable(UART0_BASE);
ROM_UARTTxIntModeSet(UART0_BASE, UART_TXINT_MODE_EOT);
ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
ROM_UARTFIFOEnable(UART0_BASE);
/* Enable the UART interrupt */
NVIC_EnableIRQ(UART_0_IRQ_CHAN);
/* Enable RX interrupt */
UART0_IM_R = UART_IM_RXIM | UART_IM_RTIM;
break;
#endif
#if UART_1_EN
case UART_1:
/* Enable the UART interrupt */
NVIC_EnableIRQ(UART_1_IRQ_CHAN);
break;
#endif
}
/* Enable the UART interrupt */
NVIC_EnableIRQ(UART_0_IRQ_CHAN);
/* Enable RX interrupt */
UART0_IM_R = UART_IM_RXIM | UART_IM_RTIM;
return UART_OK;
}
static int init_base(uart_t uart, uint32_t baudrate)
{
switch(uart){
#if UART_0_EN
case UART_0:
switch (uart) {
case _UART_DEV_NUM:
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
@ -93,11 +84,8 @@ static int init_base(uart_t uart, uint32_t baudrate)
ROM_UARTConfigSetExpClk(UART0_BASE,ROM_SysCtlClockGet(), baudrate,
(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
UART_CONFIG_WLEN_8));
ROM_UARTEnable(UART0_BASE);
break;
#endif
default:
return UART_NODEV;
}
@ -106,8 +94,9 @@ static int init_base(uart_t uart, uint32_t baudrate)
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
/* Only one UART is supported, assert that is what is used. */
assert(uart == _UART_DEV_NUM);
(void) uart;
for (size_t i = 0; i < len; i++) {
ROM_UARTCharPut(UART0_BASE, (char)data[i]);
}
@ -115,15 +104,17 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
void uart_poweron(uart_t uart)
{
/* Only one UART is supported, assert that is what is used. */
assert(uart == _UART_DEV_NUM);
(void) uart;
ROM_UARTEnable(UART0_BASE);
}
void uart_poweroff(uart_t uart)
{
/* Only one UART is supported, assert that is what is used. */
assert(uart == _UART_DEV_NUM);
(void) uart;
ROM_UARTDisable(UART0_BASE);
}
@ -138,12 +129,11 @@ void isr_uart0(void)
ROM_UARTIntClear(UART0_BASE, ulStatus);
/* Are we interrupted due to a received character */
if(ulStatus & (UART_INT_RX | UART_INT_RT))
{
while(ROM_UARTCharsAvail(UART0_BASE))
{
if (ulStatus & (UART_INT_RX | UART_INT_RT)) {
while (ROM_UARTCharsAvail(UART0_BASE)) {
long lchar = ROM_UARTCharGetNonBlocking(UART0_BASE);
config[UART_0].rx_cb(config[UART_0].arg, (uint8_t)lchar);
config[_UART_DEV_NUM].rx_cb(config[_UART_DEV_NUM].arg,
(uint8_t)lchar);
}
}
cortexm_isr_end();