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cpu/cortexm_common: split isr_pendsv()
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f74cb053b2
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977f0dfd70
@ -306,6 +306,7 @@ void thread_yield_higher(void)
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__ISB();
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}
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#if CPU_CORE_CORTEXM_FULL_THUMB
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void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
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__asm__ volatile (
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/* PendSV handler entry point */
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@ -316,19 +317,13 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
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/* skip context saving if sched_active_thread == NULL */
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"ldr r1, =sched_active_thread \n" /* r1 = &sched_active_thread */
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#if CPU_CORE_CORTEXM_FULL_THUMB
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"ldr r12, [r1] \n" /* r12 = sched_active_thread */
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#else
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"ldr r1, [r1] \n"
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"mov r12, r1 \n" /* r12 = sched_active_thread */
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#endif
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"push {lr} \n" /* push exception return code */
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"cpsid i \n" /* Disable IRQs during sched_run */
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"bl sched_run \n" /* perform scheduling */
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"cpsie i \n" /* Re-enable interrupts */
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#if CPU_CORE_CORTEXM_FULL_THUMB
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"cmp r0, r12 \n" /* if r0 == 0: (no switch required) */
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"it eq \n"
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"popeq {pc} \n" /* Pop exception to pc to return */
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@ -361,7 +356,34 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
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"msr psp, r0 \n" /* restore user mode SP to PSP reg */
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"bx lr \n" /* load exception return value to PC,
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* causes end of exception*/
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/* return from exception mode to application mode */
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/* {r0-r3,r12,LR,PC,xPSR,s0-s15,FPSCR} are restored automatically on exception return */
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".ltorg \n" /* literal pool needed to access
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* sched_active_thread */
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:
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:
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:
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);
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}
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#else /* CPU_CORE_CORTEXM_FULL_THUMB */
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void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
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__asm__ volatile (
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/* PendSV handler entry point */
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/* save context by pushing unsaved registers to the stack */
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/* {r0-r3,r12,LR,PC,xPSR,s0-s15,FPSCR} are saved automatically on exception entry */
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".thumb_func \n"
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".syntax unified \n"
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/* skip context saving if sched_active_thread == NULL */
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"ldr r1, =sched_active_thread \n" /* r1 = &sched_active_thread */
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"ldr r1, [r1] \n"
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"mov r12, r1 \n" /* r12 = sched_active_thread */
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"push {lr} \n" /* push exception return code */
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"cpsid i \n" /* Disable IRQs during sched_run */
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"bl sched_run \n" /* perform scheduling */
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"cpsie i \n" /* Re-enable interrupts */
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/* Cortex-M0, Cortex-M0+ and Cortex-M23 */
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"cmp r0, r12 \n" /* if r0 == previous_thread: */
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@ -414,7 +436,6 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
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"mov sp, r12 \n" /* and get the parked MSR SP back */
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"bx r0 \n" /* load exception return value to PC,
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* causes end of exception*/
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#endif
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/* return from exception mode to application mode */
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/* {r0-r3,r12,LR,PC,xPSR,s0-s15,FPSCR} are restored automatically on exception return */
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@ -425,6 +446,7 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
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:
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);
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}
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#endif
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#ifdef MODULE_CORTEXM_SVC
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void __attribute__((naked)) __attribute__((used)) isr_svc(void)
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