- Added ADI instruction offsets
- Added register banks and address bases for masked access (writes).
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
- Changed "meh" to "Reserved".
- Renamed CTL to CFG to match SDK/TRM name.
- Added constants for VIMS and FLASH necessary to trim registers.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
- Fixes padding.
- Updates documentation.
- Removes documentation longer than 80-chars for the registers values.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
This function is needed to setup the AUX operational mode at startup,
also used for managing low-power states.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
Rename the variable to make it clearer that it refers to the last Makefile
included.
Usually this is the current file, but when another Makefile is included this
changes.
stm32f1 periph_rtc implementation gets a 1s resolution by dividing
CLOCK_LSx by 32768. This only make sense if CLOCK_LSE is set,
otherwise CLOCK_LSI=~40000, which will lead to an imprecise rtc.
lpc23xx has 3 sleep modes and one idle mode.
`PM_NUM_MODES` must only count the idle modes.
In practise, this makes no difference since `mode 3` (IDLE) is
the `default` case in `pm_set()` anyway.
GPIO32 and GPIO33 are used during boot to start an 32.768 kHz XTAL if it is connected to these GPIOs. If the 32.768 kHz XTAL is not connected, these pins can be used digital IO. However, the 32.678 kHz XTAL has to be disabled explicitly in this case. Furthermore, the handling of GPIOs greater than GPIO31 had to be fixed in I2C software implementation.
The calculation of `_state_index` is broken for `port = 2`
_gpio_isr_map[n + (port<<1)];
Will not yield the right result. As a consequence, IRQs on Port 2
are not working.
The right thing here would be
_gpio_isr_map[n + (port ? 32 : 0)];
But we might just re-using the `_isr_map_entry()` function.
Also only iterate as many times as there are set interrupt bits.
The ARM CortexM vector table has some reserved fields which are used by
some manufacturers to store their custom image information. In
particular, NXP QN908X stores the checksum, Code Read Protection, image
type and boot block pointer in this region.
This patch allows the cpu and board modules to define the value of these
fields at build time by defining a macro.
GCLK_ID and APBCMASK entries are not always uniform.
The previous hack would already break for TCC3.
Just explosively write down the cases, there are only 5 at most.
The CPU has 4 hardware timers.
Configuration for all 4 timers exists, but the compile-time range
check has an off-by-one error, causing the last timer to remain
inaccessible.
This commit enables Cortex-M CPU interrupt sub-priorities
and allows the PendSV interrupt to have a priority different
from the default one. Together these two preprocessor
defines can be used to have PendSV always run as the last interrupt
before returning from the interrupt stack back to the user space.
Running PendSV as the last interrupt before returning to the
user space is recommended by ARM, as it increases efficiency.
Furthermore, that change enhances stability a lot with the
new nRF52 SoftDevice support, currently being worked in
PR #9473.
This commit merely enables sub-priorities and a separate
PendSV priority to be used without changing the default
RIOT behaviour.
The DFLL on samd5x has a hardware bug that requires a special
re-enabling sequence when it is disabled and then re-enabled again.
When running the clock on-demand, the hardware handles the disabling
and re-enabling so that sequence does not get executed.
To reproduce, run `tests/periph_uart` on `same54-xpro`.
Without this patch the test will get seemingly stuck on `sleep_test()`.
(In fact it keeps running, but the DFLL has the wrong frequency so the
UART baudrate is wrong).
In this test, on `same54-xpro` only UART0 is sourced from DFLL.
So if the UART is disabled the DFLL will be turned off as well.
Switch from the on-chip LDO to the on-chip buck voltage regulator
when not fast internal oscillators are used.
On `saml21-xpro` with `examples/default` this gives
**before:** 750 µA
** after:** 385 µA
Also adapt the defines to the documentation
- CPUs define up to 4 power modes (from zero, the lowest power mode,
to PM_NUM_MODES-1, the highest)
- >> there is an implicit extra idle mode (which has the number PM_NUM_MODES) <<
Previously on saml21 this would always generate pm_set(3) which is an illegal state.
Now pm_layered will correctly generate pm_set(2) for IDLE modes.
Idle power consumption dropped from 750µA to 368µA and wake-up from standby is also
possible. (Before it would just enter STANDBY again as the mode register was never
written with the illegal value.)
When a previously disabled DFLL gets enabled again, the frequency will
be incorrect. Follow the procedure outlined in the errata sheet, section 2.8.3
to work around the issue.
This fixes wake from standby.
This adds cortexm_fpu to the DEFAULT_MODULE list when the feature
cortexm_fpu is provided by the architecture. It also moves the
dependency resolution of this module to the architecture-specific
Makefile.dep file.
This moves the following modules to a architecture-specific Makefile.dep
file:
- cortexm_common
- cortexm_common_periph
- newlib
- newlib_nano
- periph
Add a fucntion to switch between LDO and Buck concerter to provide the
internal CPU voltage.
The Buck Converter is not compatible with internal fast oscillators (DFLL, DPLL)
and requires an inductivity to be present on the board.
When changing the clock configuration while the RTC is running, the
RTC may end up in an undefined state that leaves it unresponsive.
The RTC is not reset to stay persistent across reboots/hibernate, so
it will not be reset on init.
Instead, disable the RTC while configuring the clocks, rtc_init() will
take care of re-enabling it.
@dylad introduced this workaround for saml21, samd5x needs it too.
To reproduce, set the CLOCK_CORECLOCK of a samd5x board (e.g. same54-xpro)
to 48 MHz.
Run any RTC application. The CPU will be stuck in _wait_syncbusy() after
a reboot.
This patch will fix this. (You will need to power-cycle the board if the
RTC has entered the stuck state as it will never be reset.)
Due to stability reasons, the SoftAP interface of the WiFi module was always enabled in former versions even if only the station interface was used. Therefore the WiFi modem had to be always active and the SoC could not enter the modem sleep mode. Therefore, the SoftAP interface is only enabled when ESP-NOW is used.
When entering a sleep mode, all wake-up sources should first be disabled before the wake-up sources required for the sleep mode are then stepwise enabled again. Otherwise, an wake-up configuration of one sleep mode may affect the wake-up within another sleep mode.
This file used to be part of the toolchain (at least in 2016.05-03
version) but is not part of the current MIPS toolchain (2018-09-03).
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
The ROM size is encoded in the part number of the Atmel SAM chips.
RAM size is not encoded directly, so get it by parsing the chip's vendor file.
The file remains in the page cache for the compiler to use, so the overhead
should be minimal:
on master:
Benchmark #1: make BOARD=samr21-xpro -j
Time (mean ± σ): 527.9 ms ± 4.9 ms [User: 503.1 ms, System: 69.6 ms]
Range (min … max): 519.7 ms … 537.2 ms 10 runs
with this patch:
Benchmark #1: make BOARD=samr21-xpro -j
Time (mean ± σ): 535.6 ms ± 4.0 ms [User: 507.6 ms, System: 75.1 ms]
Range (min … max): 530.6 ms … 542.0 ms 10 runs
- Since flash access is shared with CPU2 we resize ROM_LEN
according to CPU2 secure flash memmory area.
- Add assert to prevent unauthorized reads from CPU2 secure
flash area
The WiFi interface should be stopped before reboot or sleep. But stopping the WiFi interface disconnects an existing connection. Usually, esp_wifi_netdev tries to reconnect on an disconnect event. However, trying reconnect with a stopped WiFi interface may lead to a crash. Therefore, the stop event has to be handled.
Now, where the vendor files for light/deep sleep mode are added, function `pm_off` does not need to implement this mode by itself. Instead the existing deep sleep with disabled wakeup sources is used for pm_off.
If only one it is set in state (one GPIO pin caused an interrupt),
don't loop over all 8 bits.
Use clz to get the position of the first interrupt bit and clear it,
looping only as many times as there are actual interrupts.
`rtc_init` is used after light sleep to update the system time from RTC timer. The fix corrects a small difference of about 230 ms which would sum up with each wakeup from light sleep.
This definition is compatible with `cc26x0` and `cc26x2_cc13x2`.
The only difference is (cc26x0 -> cc26x2_cc13x2):
- IRQ13 -> FG_COMMAND_STARTED
- IRQ12 -> COMMAND_STARTED
Those IRQs aren't used on cc26x0 radio so it shouldn't affect anything.
From the ARMv7-M ARM section B3.5.3:
Where there is an overlap between two regions, the register with
the highest region number takes priority.
We want to make sure the mpu_noexec_ram region has the lowest
priority to allow the mpu_stack_guard region to overwrite the first N
bytes of it.
This change fixes using mpu_noexec_ram and mpu_stack_guard together.
cc2538 implements 4 sleep modes.
In the lightest mode (3) any interrupt source can wake up the CPU.
In mode 2, only RTT, GPIO or USB may wake the CPU.
In mode 1 only RTT and GPIO can wake the CPU.
In mode 0 only GPIO can wake the CPU.
In mode 0 and 1 the lower 16k RAM are lost. This is a problem since those
are usually used by RIOT.
The linkerscripts in cc2538/ldscripts take different approaches towards that.
Some only use the upper 16k and leave the other half to be managed by the
application.
`cc2538sf53.ld` which is used by `openmote-b` uses the entire RAM starting
at the lower half, so it will not be able to wake up from those modes.
A quick fix to test those modes with `tests/periph_pm` would be
--- a/cpu/cc2538/ldscripts/cc2538sf53.ld
+++ b/cpu/cc2538/ldscripts/cc2538sf53.ld
@@ -21,7 +21,7 @@ MEMORY
{
rom (rx) : ORIGIN = 0x00200000, LENGTH = 512K - 44
cca : ORIGIN = 0x0027ffd4, LENGTH = 44
- ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 32K
+ ram (w!rx) : ORIGIN = 0x20004000, LENGTH = 16K
}
We have to read the DR for every byte that we write.
Just reading DR while SPI is busy in a loop can lead to bytes being
left in the fifo, corrupting subsequent reads.
- cpu/stm32f1: Removed previous code in gpio_init() to provide PB4 on the
Nucleo-F103RB only
- cpu/stm32_common: Introduced STM32F1_DISABLE_JTAG which, if defined in
board.h, exposes the JTAG only pins as GPIOs. This keeps the SWD pins, so that
SWD debugging remains possible
The internal DC/DC converter is more efficient compared to the LDO
regulator. The downside of the DC/DC converter is that it requires an
external inductor to be present on the board. Enabling the DC/DC
converter is guarded with NRF5X_ENABLE_DCDC, this macro must be defined
if the DC/DC converter is to be enabled.
This implements a basic Real Time Clock based on TIM2.
As the timer is too fast and wraps around after just 8 bits, it is
not used directly. Instead TIM2 is responsible for providing a 1 Hz
tick by generating an alarm every second.
The current time data is kept in the `.noinit` section, so it will survive
a reboot, but the clock will not be updated while the bootloader runs, so
expect inaccuracies.
By using a custom EPOCH for the RTC implementation, we can extend the
range of the 32 bit counter based RTC by 118 years.
It also reduces the code size compared to the stdlib based POSIX functions.
To be able to define common configurations for all ESP CPUs, the CPU specific configuration cpu_conf.h has to include a common configuration. For that purpose cpu_conf.h in cpu/esp_common is renamed to cpu_conf_common.h and included in CPU specific configurations.
The split between GEN2_ULP32K and GEN3_ULP32K was introduced to fix
a failure in tests/periph_wdt when the external oscillator was used.
By not running the external oscillator on demand, the failure can no
longer be observed, so default GEN3_ULP32K to GEN2_ULP32K.
The lpc23xx MCU has up to three I2C interfaces.
This adds a driver for it.
The peripheral works in interrupt mode, each change of the state machine
will generate an interrupt.
The response to the states are laid out in the data sheet.
This replaces the old driver that was removed in c560e28eb6
All the more recent vendor files have them, so include them for samr30 too.
It is expected for this to become obsolete with the next vendor file update.
During the write access to the SPI flash, the IROM cache is not available and only code from the IRAM can be executed. Therefore, the code of file system implementations which access the SPI flash must reside in IRAM.
For consistency, use named GCLKs.
- `SAM0_GCLK_32KHZ` will always be 2 for samd21
- `SAM0_GCLK_MAIN` will always be 0
So no change in functionality, just makes the code easier to understand.
The same tool 'gen_esp32part.py' is used for the generation of partition tables on ESP8266 as well as n ESP32. The tool is therefore added to 'dist/tools/esptool'
Creating an `exti_config` array for a new MCU manually is tedious and error prone.
Luckiely all information is already availiable in the vendor files.
Credit for this discovery & method goes to @Sizurka
The file was generated with
```C
int main(void) {
puts("static const int8_t exti_config[PORT_GROUPS][32] = {");
for (unsigned port = 1; port < 5; ++port) {
printf("#if PORT_GROUPS >= %d\n{\n", port);
for (unsigned pin = 0; pin < 32; ++pin) {
printf("#ifdef PIN_P%c%02uA_EIC_EXTINT_NUM\n", '@' + port, pin);
printf(" PIN_P%c%02uA_EIC_EXTINT_NUM,\n", '@' + port, pin);
printf("#else\n -1,\n#endif\n");
}
printf("},\n#endif\n\n");
}
puts("};");
return 0;
}
```
No changes in generated code are expected, but this makes adding new members
of the sam0 CPU families much easier.
Set the ONDEMAND bit so clocks are only run if they have a user configured.
This saves 390 µA on same54-xpro.
examples/default:
before: 3.88 mA
after : 3.49 mA
examples/gnrc_networking: (with REB215-XPRO EXT3)
before: 13.29 mA
after : 12.9 mA
samr30 is the only MCU of this family where the vendor files do not
define the PIN_($pin)_EIC_EXTINT_NUM macro yet.
This macro is needed to create a generic EXTI configuration for all
sam0 MCUs.
The defines were generated with
sed -Ei '/define PIN_(.*)_EIC_EXTINT([0-9]*)/
{h; x;
s/define PIN_(.*)A_EIC_EXTINT([0-9]*)(.*)/
define PIN_\1A_EIC_EXTINT_NUM _L_\(\2\)
\/**< \brief EIC signal: PIN_\1 External Interrupt Line *\/
/g; G}' samr30g18a.h samr30e18a.h
Previous value was 20 K, now it's 80 K. The older family of these MCUs
(cc13x0, cc26x0) had that size, currently for cc13x2 and cc26x2 it's
80 K.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
From the data sheet:
> **Note:** Only in case when a reset occurs and the POR = 0, the BODR bit
indicates if the V DD(DCDC)(3V3) voltage was below 2.6 V or not.
So the value of BODR is undefined if POR is set.
Clear it to bring it to a defined state.
The function would always return `true` after early boot, so it
is not very useful for applications.
Now it will only (but always) return true when we woke from Deep Sleep
*after* early boot. This makes it behave the same ways as the function
of the same name on SAME54.
Rename the existing function to cpu_backup_ram_is_initialized() to better
match it's semantics.
On the MCB2388 plugging the power will result in both the POR and EXTR
bit being set.
Not sure if this is a property of the board, but it means RTC is also
reset after programming, so it behaves just like Backup RAM.
If we woke from Deep Sleep the POR bit will be cleared, so the RTC is not
reset.
RSIR is 0x1 (POR) if we woke from Deep Sleep.
This makes it hard to distinguish between real power-on and waking from
Deep Sleep, which is why the Backup RAM signature was introduced.
However, calling cpu_woke_from_backup() a second time will always return
true, as the signature will have been set up by early boot then.
Thus, clear the POR bit if the signature was already in place.
The result is:
RSIR == 0 -> woke from sleep
RSIR == 1 -> cold boot
Calling localtime() adds considerable overhead.
There are easier ways to set the date to 1970.
For tests/periph_rtc this results in this ROM change:
master:
text data bss dec hex
31328 240 98064 129632 1fa60
with this patch:
text data bss dec hex
20036 140 98168 118344 1ce48
The reboot process for ATmegas is to enable the watchdog timer and loop until
the wdt reboots this MCU. However, this reboot will keep the wdt configuration,
so that the wdt needs to be disabled during boot. This is done in get_mcusr,
but without the attribute "used" it will be optimized out in LTO builds. This
commits adds the attribute "used" to get_mcusr.
Also simplified the backward compatibility with older ATmegas (currently not
supported by RIOT) on outdated versions of avrlibc.
bitarithm.h is not needed for the interface of shed but may cause conflicts
due to different definitions of SETBIT and CLRBIT
common implementations are: (value, offset) xor (value, mask) bitarithm
implements the later
frac.c and nrf52/usbdev.c use bitarithm.h but where missing the include
sam0/rtt.c defined a bit using mask from bitarithm,
changed that to the soulution used in sam0/rtc.c
Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK
introduce helper functions to return the frequency of the individual
GCLKs and use those for baud-rate calculations.
This requires the GCLK to be part of the peripheral's config struct.
While this is already the case for most peripherals, this also adds
it for those where it wasn't used before.
As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
To simplify board definitions and for unification between samd2x and
newer models, don't use the GCLK bitmask in board definitions.
Instead use the GCLK index and generate the bitmask when needed.
There is size difference for atomic_int_fast8 and atomiic_uint_fast8
on FreeBSD, i.e., they match uint32_t with size of 4 bytes instead of
uint8_t with size of 8. Hence, tests/c11_atomics_cpp_compat buildtest
fails on FreeBSD.
The CC26x2 and CC13x2 share the same register definitions, and both are
treated equally in the TI's technical reference manual. [1]
- To avoid confusions in the future I renamed it to `cc26x2_cc13x2`.
- Documentation was updated.
- The `cc1312-launchpad` board that uses the `cc13x2` MCU was updated.
- The `cc1352-launchpad` board that uses the `cc13x2` MCU was updated.
[1]: https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
With the new toolchain version required to fix issue #13133, the compilation of `examples/posix_socket` fails due to a C linkage error in `atomic_base.h`. The reason is that including `drivers/include/mtd.h` in `boards/esp32/board_common.h` inside the `extern C` block finally leads to including `atomic_base.h` inside the `extern C` block which in turn to the C linkage error for the template definitions in this file.
For atmega boards a TX has not actually completed until UDRn is empty
as well as the Transmit Shift Register.
To avoid resetting an UART before a TX has completed we use the TXCn
flash and ISR to set a variables that indicates TX is ongoing. This
allows not reseting the UART while there are ongoing TX pending.
This fixes an issue where part of the last byte is not shifted out
of the TX shift register causing rubish on the first TX following an
uart_init.
The ADC_STATUS_SINGLEACT indicates that an operation is active, while
the ADC_STATUS_SINGLEDV indicates that data is valid.
This fixes ADC returning values of unfinished reads.
Without this change a RIOT application compiled with all-asan will
segfault as RIOT provides its own malloc by default. Add a define for
disabling custom malloc, calloc and realloc implementations and use it
when compiling with all-asan.
ESP32 can be clocked with either a 40 MHz or 26 MHz crystal. Since most boards use a 40 MHz crystal, the configuration was previously fixed to a 40 MHz crystal. This commit changes the crystal from 40 MHz to automatic detection, allowing boards with a 26 MHz crystal like the Sparkfun ESP32 Thing DEV to be used.
- Unecessary definitions are removed.
- Since the 48-bit RTC hardware timer uses a RC oscillator as clock, it is pretty inaccurate and leads to a RTC time deviation of up to 3 seconds per minute. Therefore, a calibration during the boot time determines a correction factor for the 48-bit RTC hardware timer. Function _rtc_time_to_us uses now this correction factor and converts a raw 48-bit RTC time to a corrected time in microseconds. Thus, the 48-bit RTC timer becomes much more accurate, but it can't still reach the accuracy of the PLL driven 64-bit system timer. The Advantage of using RTC over 64-bit sydtem timer is that it also continues in deep sleep mode and after software reset.
- If the 64-bit system timer is used to emulate the RTC timer, it uses the RTC hardware timer to continue its operation after software .
It is possible to use different timers as RTC timer for the periph_rtc module. Either the 48-bit RTC hardware timer is used directly or the PLL driven 64-bit system timer emulates a RTC timer. The latter one is much more accurate. Pseudomodule esp_rtc_timer controlls which timer is used. Only if esp_rtc_timer is enabled explicitly, the 48-bit RTC hardware timer is used. Otherwise the 64-bit sytstem timer is used to emulate the RTC timer.
The explicit call of rtc_init during the CPU start was removed because rtc_init is called within the function periph_init. The display of the system time at startup had to be placed after the call to periph_init.
There is an existing function that returns the system time in us as a 64 bit value. Converting this 64 value in us to a 32 bit value in ms is more easier and uses the complete 32 bit range. Using only the low part of the 64 bit system time in us and dividing it by 1e3 cuts the 32 bit range.
To control the log level and the format of the log output of SDK libraries, a bunch of library-specific printf functions are realized which map the log output from SDK libraries to RIOT's log macros.
The buffer[EHTHERNET_MAX_LEN] used in _esp_wifi_send to convert the iolist of the given packet to a plain buffer for the WiFi interface should not be on the stack to prevent the sending thread's stack from overflowing.
- Using a enum instead of _COUNTER is easier to read
- _COUNTER is also a reserved name; so better not use it to avoid issues
- Split out the pcint code into a static inline function for increased
readability
The bank index and the pin number are not necessarily identical. For all
PCINT banks except for bank 3 bank_idx was used therefore. It was likely
just forgotten to update that for bank 3 as well.
Some ESP8266/ESP8285 modules only work with DOUT SPI flash mode and a SPI flash frequency of 26 MHz. Therefore, these parameters have to be used by default. Otherwise some modules will no boot.
For better compatibility copy most of cortexm_base.ld
and use the same section names.
Only interrupt stacks and the two additional (currently unused)
heap sections are different between the two now.
Both architectures are variants of the ARM architecture and use the same
toolchain.
There is no reason to have such wildly different defaults.
This results in some tests passing that would crash before:
- [x] `tests/pkg_libcose`
- [x] `tests/pkg_qdsa`
- [x] `tests/pkg_relic`
- [x] `tests/pkg_tweetnacl`
- [x] `tests/pthread_tls`
`THREAD_EXTRA_STACKSIZE_PRINTF_FLOAT` is not used anywhere in RIOT
anymore, so just drop it.
Startup information, including board configuration, is only printed when module esp_log_startup is used. This reduces the amount of information that is printed by default to the console during the startup. The user can enable module esp_log_startup to get the additional startup information.
To avoid that murdock times out before tests/pkg_spiffs and tests/pkg_littlefs time out, the configured test timeouts for these tests is reduced to 200 seconds which should be enough. An ESP32 needs an average of 60 seconds for these tests, while an ESP8266 needs in average 100 seconds.
ESP32 nodes can crash during SPI Flash write operations if required parts of the code are not in the IRAM but in the cached SPI Flash memory, which is disabled during the SPI Flash write operations. Therefore, the code of the SPIFFS package and the VFS module are now stored in the IRAM.
Building e.g. gnrc_border_router example on FreeBSD fails due to
missing defines related to sockets. This adds the missing header
<sys/socket.h> to fix compiling.
Now that CPU and CPU_MODEL are defined in the board's Makefile.features
it can be used to determine the available features provided by the
specific model.
Setting up the .data and .bss section happens in arm7_init.c now.
The code was commented out anyway, so just remove it.
Also remove leftover variable declarations that were only used in
the dead code.
To reduce the information that are printed at the console during the startup, special bootloaders are required that suppress the outputs which are only informational. The according bootloader has to be selected during the make process.
Startup information, including board configuration, is only printed when module esp_log_startup is used. This reduces the amount of information that is printed by default to the console during the startup. The user can enable module esp_log_startup to get the additional startup information.
lpc23xx has 2k of battery RAM that is retained in Deep Power Down mode.
To not overwrite that data it must only be initialized on Power On Reset.
However, RSIR looks the same when waking up from Deep Power Down as it does
on the power-on case.
So use 4 bytes of the backup RAM to keep a signature that is only valid if
memory was retained (no power-on Reset).
A small change to the linker script is required so two sections can be
placed into flash.
The UART peripheral clock seems to be sporadically set to wrong value when the CPU clock is changed. In this case, the UART clock is not set to 115.200 kbps but to 96 kbps, so that the output in the console seems like garbage. This can also cause automatic tests to fail. Therefore, the CPU clock is only changed if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ defines a different default CPU clock than the one already used at boot time.
The common ADC API dictates that a sample call must return -1 on an
incorrect resolution. The sam0 ADC implementation instead threw an
assertion failure.
The 10 bit DAC on the lpc23xx is very simple.
It only has one channel and can only be mapped to a single pin (P0.26).
After setting the pin mode to DAC no further configuration in needed.
puf_sram only relies on an uninitialized chunk of memory.
This means to enable it we just have to hook up puf_sram_init().
All memory after __bss_end should be uninitialized at startup, so
just use that.
- TI documentation for msp430f1xx is ambiguous regarding length
of some memmory sectors. For some cpu's the acual size is 1/4 byte
smaller than advertised and one of the sectors is actually 256b and
not 512.
ref: https://e2e.ti.com/support/microcontrollers/msp430/f/166/p/798838/2962979#2962979
- Remove the first 256b sector from usage since there is not support for
variable sized pages
- Fix msp430f2617 FLASHPAGE_NUMOFF to represent accesible memory
If the user or the board definition doesn't enable `esp_wifi` or `esp_eth`, `esp_now` is defined as default netdev.
fixup! cpu/esp32: defines esp_now as default netdev
At the end of an ISR, the ATmega code was doing an `thread_yield()` instead of
a `thread_yield_higher()`. This resulted in tests/isr_yield_higher failing.
Fixing this saves a few lines of code, some ROM, and solves the issue.
Names with two leading underscores are reserved in any context of the c
standard, and thus must not be used. This ATmega platform used it however for
defining internal stuff. This commit fixes this.
To be able to catch a core panic in debugger and to get the last output from asynchronous UART , e.g., if the stack is smashed, the system is not rebooted immediately anymore but breaks, which stops the execution in debugger or reboots the system after WDT timeout.
Log outputs generated by binary ESP32 SDK libraries are mapped to the ESP32's log module which supports colored and tagged log outpus. Tagged log outputs from SDK libraries are handled accordingly.
The implementation of `log_module` for ESP32 was changed from functions to a macro-based implementation to be able to use the bunch of macros for colored and tagget log output generation.
Enable IDLE and Deep Powerdown mode.
IDLE is pretty straightforward - insteady of busy waiting, the CPU will
enter an idle state from which it will resume on any event.
Deep Power Down shuts off the entite system except for the battery backup
power domain.
That means the CPU will reset on resume and can be woken by e.g. RTC.
SLEEP and POWERDOWN disable the PLL and the PLL and Flash respectively.
This requires some proper wake-up handling.
Since this turned out to be a major time sink and those modes are never
currently never used in RIOT outside of tests, I left this as an exercise
for a future reader.
`pm_set()` gets called by the idle thread whose stack is too small
for normal DEBUG()/printf().
Use DEBUG_PUTS() instead to print the static debug strings.
Renames crypto functions of ESP32 SDK in vendor code to resolve the conflicts between `wpa-supplicant` crypto functions and RIOT's `crypto` and `hashes` modules.
To resolve the conflicts between `wpa-supplicant` crypto functions (part of the ESP32 SDK) and RIOT's `crypto` and `hashes` modules, the crypto function headers from ESP32 SDK are added to vendor code and the crypto functions are renamed using the prefix `wpa_`.
A number of tests insist that the number of thread priority levels is 16. However, when using the WiFi interface, a number of high priority threads are required to handle the WiFi hardware. In this case, the number of thread priority levels must be 32. Solves the problem of tests `tests/shell`.
Removes the dependency of the module riot_freertos from module xtimer. This avoids that xtimer is used even if it is not really needed which in turn occupies the first timer device and tests/periph_timer fails.
ESP32 log output was always tagged with additional information by default. The tag consists the type of the log message, the system time in ms, and the module or function in which the log message is generated. By introducing module `esp_log_tagged`, these additional information are disabled by default and can be enabled by using module `esp_log_tagged`.
Log module of ESP32 supports colored log outputs when module `esp_log_color` is enabled. The generation of colored log outputs is realized by a extending the bunch of macros with an additional letter indicating the type of log message,
For the implementation of the colored log output, two versions of the bootloader are introduced, one version with colored log output and one version without colors.
The modified version esptool.py from RTOS SDK that is required for flashing an image, is now placed in `dist/tools/esptool.py` and used directly from there. The advantage is that `esptool.py` hasn't to be installed explicitly anymore. Having RIOT is enough. The documentation is adapted accordingly. The oly prerequisite is that python and the pyserial module are installed.
In vendor startup code, initialization function were called as parameters of assert statement. With DEVELHELP, they are not called since the assert macro does nothing.
To make the migration progress to the new RTOS SDK easier, the new toolchain was renamed to xtensa-esp8266-elf. This makes it possible to have the new and the old toolchain installed in parallel.
If the WiFi module is used, a number of high priority tasks is created. To void priority collisions with netdev drivers, the number of priorities SCHED_PRIO_LEVELS has to be increased to 32. But in other cases, the default number should be used, also to keep automatic tests working.
Moved macros and static inline helper functions needed to access ATmega GPIOs
to cpu/atmega_common/include/atmega_gpio.h in order to reuse them for the
platform specific low level part of the Neopixel driver.
Currently, spi_acquire() will always re-configure the SPI bus.
If the configuration did not change, this is entirely uneccecary
and makes SPI operations take longer than needed.
Instead, compare the current configuration with the new configuration
and skip the initialisation if it didn't change since the last call.
The RTC expects to be clocked from a 1kHz source.
Previously it would re-configure GCLK2 from 32kHz to 1kHz when used.
Since GCLK2 is also used by EIC, this would break external interrupts
in strange and unexpected ways.
Dedicate a 1kHz clock to it to avoid the damage.
From the data sheet:
> The COUNT register requires synchronization when reading.
> Disabling the synchronization will prevent reading valid
> values from the COUNT register.
Without this bit enabled, rtt_get_counter() will always return 0.
ATmega128RFA1/ATmega256RFR2 do not have a unique CPU ID.
Use the RC oscillator callibration byte as an impromptu CPU ID and rely
on bootlader constants present on all ATmega families for the remaining
bytes.
This way we can provide a faux CPU ID on all ATmega MCUs and typical hobbyists
with no access to JTAG adapters or high voltage programmer capable of writing
the user signature have a good chance that the CPU IDs of their device do not collide.
This converts the hard-coded UART driver to the new ways.
- allow the board to configure the RX & TX pins
- allow for more than one UART
- allow setting the baudrate
- implement poweron()/poweroff() functions
Currently the cpu/lpc2387 init code hard-codes a 16 MHz
external oscillator.
Instead, calculate the PLL multiplier based on the board define
and also allow to run without an external oscillator.
Scan-build detected that sercom_id could return -1 and the value of this function is affected to uint8_t variables. Since these variables are used for shitfing bit in registers, this could lead to undefined behavior
Fix the condition to return -ENOPNOTSUPP when i2c repeated read attempted.
Currently the error occures even if a read after write is attempted.
This is the standard way to i2c_read_reg which should be supported.
The -EOPNOTSUPP requires the previous R/W state to be reading.
This means a `I2C_SR2_TRA` must be checked to be 0.
There is no hardware limitation for custom boards based on STM32 to uses
SPI bus with signals coming from different PORT and alternate functions.
This patch allow alternate's function definition per pin basis, thus enable
the support of SPI bus signals routed on differents PORT.
Signed-off-by: Yannick Gicquel <ygicquel@gmail.com>
If `SPI_CS_UNDEF` is given as the `cs` parameter, CS pin must not be handled by the driver. Furthermore, if `cont` parameter is true, CS pin must not be disabled at the end of one transfer.
The ADC2 controller of the ESP32 is used by the WiFi module. The GPIOs connected to the ADC2 controller cannot be used as ADC channels if the WiFi module is enabled. This is clarified by a note in the documentation.
This change is for all boards with a sam0 cpu. This cpu just has one ADC.
It is unnecessary to have defines with ADC_0_ prefix as if multiple ADCs
are possible.
Some defines were not used, such as ADC_0_EN, ADC_0_CHANNELS,
ADC_MAX_CHANNELS, ADC_0_CLK_SOURCE, ADC_0_CHANNELS
Change all ADC_0_ prefixes to ADC_
Many MCUs contain some Backup or Low Power SRAM that is retained'even
in the deepest sleep modes.
In such sleep modes the MCU is essentually turned off with only the RTC
still running.
It can be woken by a GPIO or a RTC alarm. When this happens, a reset is
triggered and the normal startup routine is invoked.
This adds bss & data section for this memory in the linker script.
This allows for structures to be placed in it e.g.:
e.g.:
static uint8_t persistent_buffer[64] __attribute__((section(".backup.bss")));
static uint32_t persistent_counter __attribute__((section(".backup.data"))) = 1234;
Thin archives also cause a boot loop when using the flash module.
To prevent further surprises, disable thin archives unconditionally
until the cause for this behaviour is known.
In fractional mode, 3 bits are used to store the fractional part.
Therefore we must multiply / divide by 8 instead of 10 in order to
get the correct values.
There are some constraints to the oscillators on the samd5x.
- DFLL is fixed to run at 48 MHz
- DPLL can run at 96 to 200 MHz
Always use DFLL for frequencies <= 48 MHz.
For frequencies >= 96 MHz, use DPLL directly.
For frequencies < 96 MHz, clock DPLL at twice the desired frequency
and use a divider.
At the time of configuration, the pthread-reaper uses '164' bytes of
stack when 'idle' stack is only '160'. By having double it gives some
margin.
ps
pid | name | state Q | pri | stack ( used) | base addr | current
1 | idle | pending Q | 15 | 160 ( 128) | 0x4000007c | 0x4000009c
2 | main | running Q | 7 | 2560 ( 1232) | 0x4000011c | 0x4000095c
3 | pthread-reaper | bl rx _ | 0 | 320 ( 164) | 0x40000bac | 0x40000c48
| SUM | | | 3040 ( 1524)
For a yet unknown reason, both esp8266 and esp32 get stuck in a
reboot loop when thin archives are used.
As a workaround, disable thin archives for now if esp_wifi is used.
fixes#12258
* CPU files should already have 'CPU' defined by the board.
* Do not conditionally define CPU as it is not needed.
This is part of cleanup prior to moving the CPU/CPU_MODEL to
Makefile.features.
A note says "The nomips16 attribute should not really be needed,
it works around a toolchain issue in 2016.05-03."
In fact, in 2018.09-03, the attribute leads to this error:
```cpu/mips32r2_common/thread_arch.c:191:1: error: ‘_mips_handle_exception’ redeclared with conflicting ‘nomips16’ attributes```
This this commit removes the attribute.
This reverts commit 422644bd3a.
The option is only supported after 2.6 which is currently not the
version given with 'esp' toolchain.
It was a bit too early to switch to the new version.
Version 2.7 also supports the old option with only a warning.
A naive implementation may set a RTC alarm in 30s by calling
struct tm now;
rtc_get_time(&now);
now.tm_sec += 30;
rtc_set_alarm(&now, _cb, NULL);
This works for RTC implementations that use a RTT internally and call
mktime() to convert the struct tm to a unix timestamp, as mktime() will
normalize the struct in the process.
Call rtc_tm_normalize() when the RTC uses separate registers for time / date
components to ensure it is normalized.
This also modifies tests/periph_rtc to exercise this case.
The INTFLAGS register is cleared by writing a 1 to the corresponding interrupt
flag bit. From the samr21's manual:
> Writing a zero to this bit has no effect.
> Writing a one to this bit clears the Compare 0 interrupt flag.
This is a common pattern in flag registers.
This RTT driver is using or-equal to clear the flags, which means it can
possibly clear other interrupts. There's a small chance that one event is
missed if it happens very close to another event.
Credits to @benpicco, @dylad for pointing out missing fixes.
- Moved compiler & linker flags from boards/common/msba2 to cpu/arm7_common
- Moved dependency to newlib nano to cpu/arm7_common
- Moved config to link in cpu/startup.o to cpu/arm7_common
- Removed stdio_init() from newlib's _init(), as this is too late in the boot
process to allow DEBUG()ing during periph_init()
- Added stdio_init() to the various cpu_init() routines of the ARM CPUs just
before periph_init()
Engineering sample A doesn't have a functional USB peripheral (errata
issue 94). This commit adds an assertion check for this revision to
prevent some developer headaches.
Instead of having a send buffer as member `esp_wifi` netdev, a local variable is used now as send buffer. This avoids the need for a locking mechanism and reduces the risk of deadlocks.
Receive call back function `_esp_wifi_rx_cb` is called from WiFi hardware driver with a pointer to a frame buffer that is allocated in the WiFi hardware driver. This frame buffer was freed immediately after copying its content to a single local receive buffer of the `esp_wifi` netdev. The local receive buffer remained occupied until the protocol stack had processed it. Further incoming packets were dropped. However, very often a number of subsequent WiFi frames are received at the same time before the first one is processed completely. Having the single local receive buffer to hold only one received frame, led to a number of lost packets, even at low network load. Therefore, a ringbuffer of rx_buf elements was introduced which doesn't store the frames directly but only references to the frame buffers allocated in WiFi hardware driver. Since there is enough memory to hold several frames, the frames buffers allocated in WiFi hardware driver aren't freed immediatly any longer but are kept until the frame is processed by the protocol stack. This results in a much less loss rate of packets.
Events of different type can be pending at the same time. Therefore it is not possible to use ascending identifiers for the presence of a pending event. Rather, each event type has to be represented by one bit. Thes bits ORed identify all types of pending events. In the esp_wifi_isr function all pending events are then handled in one call. Otherwise, some events might be lost.
Using flash size in megabits is deprecated by esptool.
Use the new megabyte notation.
WARNING: Flash size arguments in megabits like '8m' are deprecated.
Please use the equivalent size '1MB'.
Megabit arguments may be removed in a future release.
esptool.py v2.6
UART FIFO must contain only 1 byte when newlib's `printf` function is used. Otherwise, outputs that are still not sent over UART are lost when `printf` is called asynchronousely.
To avoid unresolved symbols for unused functions during linking, compiler option `-ffunction-sections` is used now. Linker option `--warn-unresolved-symbols` is removed to get errors if required symbols cannot be resolved.
The modules `newlib, `newlib_syscalls_default` and `stdio_uart` are now used by default for output to the UART interface. This also reduces the dependency rules.
The overridden stdio functions `puts`, `putchar` and `printf` were removed. Instead, the corresponding newlib functions are always used. Using the newlib functions fixes output conflicts when using `f *` functions like `fprintf`,` fputs`, ... with `stdout` as the file parameter.
Use the -gz option to compress ELF sections containing DWARF information.
This saves around 50% of disk space, without any side effects.
See https://gcc.gnu.org/onlinedocs/gcc-9.2.0/gcc/Debugging-Options.html#Debugging-Options
for more infomation on this option.
Some platforms have an outdated toolchain that does not support -gz so
the flag is blacklisted there. Even then, the results are quite impressive.
I used @cladmi's `buildtest` branch (https://github.com/cladmi/RIOT/tree/wip/du/buildtest)
with this change and compiled the `examples/default` application:
```
$ BUILD_IN_DOCKER=1 DOCKER="sudo docker" make -C examples/default buildtest-indocker
```
The size was obtained with:
```
$ find output -name "*.bin.bindirsize" -type f -exec tail -n1 '{}' \; | cut -f 1 | awk '{s+=$1} END {printf "%.0f", s}'
```
Results:
- Vanilla: 10328112 KB (~10GB).
- with -gz: 4982788 KB (~5GB).
This was inspired by #8496.
_exti() always assumes only 2 ports, so it will always fail when using
e.g. port C or port D on same54.
Instead, determine the number of ports from the dimensions of the exti_config
array.
As the comment above cpu_switch_context_exit notes:
sched_active_thread is not valid when cpu_switch_context_exit() is called.
Unfortunately, thread_yield(), which is called directly by
cpu_switch_context_exit(), uses sched_active_thread possibly resulting
in a null pointer dereference.
Solution: Trigger a software interrupt to perform a context switch and
let sched_run() determine the next valid thread from there.
once hardware flow control is enabled, rts should only be initialized
after the uart is enabled by setting the UE flag. This is stated in the
stm32f4 errata.
in uart_poweroff the peripheral should be disabled through the register
instead of just disabling the peripheral clock. In uart_poweron the
peripheral should be enabled after enabling the clock.
Not explicitely disabling the peripheral causes some bad signals on the
uart line sometimes.
Module `newlib` is now used by default. Therefore, the separation of initialization of ctors and the newlibc is not needed any longer. Instead of calling `do_global_ctors` and `_init` separately, `__libc_init_array` is called. Explicit function `do_global_ctors` is removed.
While deleting multiple sectors in flash, interrupts were disabled over the whole time. Thus, deleting the entire flash led to the triggering of the watchdog timer and thus to a restart. Therefore, the interrupts and the cache are disabled only for the time of deleting a single sector. The same problem occurred for read and write large data sets.
Initializing the stdio file descriptors in global reent structure with newlib fake stdio file descriptors led to the problem that newlib stdio functions printf and puts were not working since they can't operate on these fake stdio file descriptors. Therefore, this initialization was removed. Now, the real stdio file descriptors as created automatically by newlib are used. Specific functions `printf`, `puts`, `getchar`and `putchar` are not required any longer and are removed now.
Modules newlib and newlib_syscalls_default are now used by default. Conditional compilations for MODULE_NEWLIB_SYSCALLS_DEFAULT as well as alternative code are removed completely.
printf and puts used ets_printf before. Unfortunately, ets_printf adds an additional \r for each \n which is not consistent with other RIOT platforms. As a result some automatic tests failed. Therefore, both functions write now character-wise directly to the UART interface.
Memory management function like `malloc`, `calloc`, `realloc` and `free` must not be preempted when they operate on allocator structures. To avoid such a preemption, wrappers around these functions are used which simply disable all interrupts for the time of their execution.
Using a mutex for critical section handling with portENTER_CRITICAL and portEXIT_CRITICAL does not work for RIOT, as this function can also be called in the interrupt context. Therefore, the given mutex is not used. Instead, the basic default FreeRTOS mechanism for critical sections is used by simply disabling interrupts. Since context switches for the ESP32 are also based on interrupts, there is no possibility that another thread will enter the critical section once the interrupts are disabled.
- stm32f7 use sectors instead of pages, they go either from 16KB to
128KB, or from 32KB to 25KB. Smaller sectors are at the begining of
the flash. Slots must start at the begining of a sector to not overlap.
- Minimum required RIOBOOT_HDR_LEN or stm32f7 is 0x200
to respect vector table alignment
- Add CPU_FLASH_BASE
- stm32f2 uses sectors instead of pages, they go from 16KB to
128KB. Smaller sectors are at the begining of the flash. Slots
must start at the begining of a sector to not overlap.
- Minimum required RIOBOOT_HDR_LEN or stm32f2 is 0x200
to respect vector table alignment
- Stm32f4 use sectors instead of pages. They go from 16 KB to 128KB.
The bootloader will use the first sector(16Kb). Slots must start
at the begining of a sector to not overlap.
- Minimum required RIOBOOT_HDR_LEN or stm32f4 is 0x200
to respect vector table alignment
The option value length of Ethernet addresses can be more than 6 byte in lwIP. Therefore, the max_len parameter is check to be greater than or equal to ETHERNET_ADDR_LEN.
Module esp_idf_heap is enabled in cpu/esp32/Makefile.dep depending on other modules. Since cpu/esp32/Makefile.dep is read after cpu/esp32/Makefile.include, the conditional definition of the linker options for the wrapper functions had to be moved from cpu/esp32/Makefile.include to cpu/esp32/Makefile.dep.
If module esp_idf_heap is used, the memory management functions _malloc_r, _realloc_r, _calloc_r and _free_r have to be overridden by wrapper functions to use the heap_* functions of module _esp_idf_heap. However, this can lead to multiple symbol errors for these functions for some applications. To solve this symbol conflict, _malloc_r, _realloc_r, _calloc_r and _free_r functions are renamed to __wrap_* and the linker options are extended by -Wl,-wrap option when module esp_idf_heap is used.
When standard C libraries are added to BASELIBS to group them together with all other modules, there are multiple definitions for the putchar function. The one that is defined writing to the UART as standard output and the one that is provided by the standard C libraries. To solve this symbol conflict, putchar and getchar functions that use the UART as standard output/input are renamed to __wrap_putchar and __wrap_getchar and the linker options are extended by -Wl,-wrap option.
When linking an application, symbol pthread_setcancelstate is not known in standard C libraries, even if the pthread module is linked. This is because the pthread module is grouped with all other modules, but not with the default C libraries when they are added to LINK_FLAGS. Therefore, standard C libraries have to be added also to BASELIBS to group them with all other modules.
Fixes the problem that the compilation of an applications can throw unknown symbol errors for functions that aren't use at all. Thus, it is possible to remove the warning for unknown symbols and the compilation can abort if there are real unknown symbols.
- remove old header files
- fix new DMA header file macro definitions
- remove old cpu type groups (STM32L1XX_MD, STM32L1XX_MDP,
STM32L1XX_HD, STM32L1XX_XL)
- The __NOP() that was added in #8518 is now remooved.
- When DBG_STANDBY, DBG_STOP or DBG_SLEEP are set in DBG_CR a hardfault
occurs on wakeup from sleep. This was first diagnosed in #8518. When
enabled, a hardfault occured when returning from a branch to irq_restore()
we avoid the call by inlining the function call. See #11830 for more
details.
-include will throw no error if sam0_common/Makefile.features does not exist.
This may not have been intentional as none of the other sam0 implementations
do this.
Replace it with a normal include.
Although it isn't explicitly specified in API, gpio_read should return the last written output value for output ports. Since the handling of inputs and outputs is strictly separated by several registers in ESP32, gpio_read returned always the initial value of the input register. Therefore, a case distinction had to make. While for input ports the real value has to be read from the input register, the last written value for the output port has to be read from the output register.
Currently the configuration claims that external interrupt INT4 is present on
pin PE7. However, the ATmega32U4 datasheet (section 10.3.4 page 81) contains
the following remark to pin PE7: "Not present on pin-out". This commit removes
the PE7 from the interrupt config.
- split up interrupt vector code from bootloader.c to vectors.c
- moved bootloader.c to arm7_init.c
- Use consistent naming:
- use lower case for everything but preprocessor stuff
- ISRs now named isr_foo()
- Functions bl_uart_init(), bl_blink(), bl_config_init() declared but never
implemented
--> Removed declarations
- Check for c preprocessor macro CPU_MC1322X is obsolete, as CPU_MC1322X is
nowhere defined in RIOT's code base
- IRQ_Routine() is never used, nor is it ever configured as ISR
- DEBUG_Routine() is never used, nor is it ever configured as ISR
- Moved VIC.c to irq_arch.c for consistent naming scheme
- Removed unused functions IRQenabled, disableFIQ, restoreFIQ, enableFIQ
- There is not header for those functions, so they *cannot* be used
- These is obviously no user, as they *cannot* be used
- There is absolutely no documentation what they would be used for
The `mips32r2_generic` CPU was only used by the `mips-malta` board which has
been removed. The reasons for this removal are the same as for the board:
- No hardware to test.
- The board that used this CPU is not available off the shelf.
- No UART input.
- No integrated flasher (one needs to use a separate Windows tool)
For more information and discussion around MIPS, see issues:
- #11831 (Removal of mips-malta)
- #11788 (General MIPS removal)
cpu/stm32_common: cleanup periph eth
boards/nucleo-f767zi: cleanup dependencies
boards/nucleo-f767zi: fix dma configuration attribute for eth
examples/default: add nucleo-767zi in boards with netif
drivers/stm_32_eth: Add header guard for eth_config
Co-authored-By: Robin <robin@chilio.net>
stm32eth: Move to stm32_common periph
cpu/stm32_periph_eth: Rebase to current master branch
- Update DMA to use new vendor headers
- Update send to use iolist. It looks like the packet headers are now transfered as seperate iolist entries which results in the eth periph sending each header as own packet. To fix this a rather ugly workaround is used where the whole iolist content is first copied to a static buffer. This will be fixed soon in another commit
- If MAC is set to zero use luid to generate one
- Small code style fixes
cpu/stm312f7: Add periph config for on-board ethernet
boards/nucleo-f767zi: Add config for on board ethernet
tests/stm32_eth_lwip: Remove board restriction
boards/common/nucleo: Add luid module if stm32 ethernet is used
tests/stm32_eth_gnrc: Add Testcase for gnrc using the stm32 eth periph
stm32_eth: Rework netdev driver layour
tests/stm32_eth_*: Use netdev driver header file for prototypes
stm32_eth: Add auto init for stm32 eth netdev driver
boards/stm32: Enable ethernet conf for nucleo boards
stm32_eth_auto_init: Add dont be pendantic flag
stm32_eth: Remove dma specific stuff from periph_cpu.h
Looks like this was implemented in PR #9171 and 021697ae94 with the same interface.
stm32_eth: Remove eth feature from stm32f4discovery boards
stm32_eth: Migrate to stm32 DMA API
stm32_eth: Add iolist to module deps
stm32_eth: Rework send function to use iolist
stm32_eth: Fix ci build warnings
stm32_eth: Fix bug introduced with iolist usage
stm32_eth: Remove redundant static buffer
stm32_eth: Fix feature dependencies
stm32_eth: Fix wrong header guard name
stm32_eth: Implement correct l2 netstats interface
stm32_eth: Rename public functions to stm32_eth_*
stm32_eth: Fix doccheck
stm32_eth: Move register DEFINE to appropriate header file
stm32_eth: remove untested configuration for f446ze boards
stm32_eth: Move periph configuration struct to stm32_common
stm32_eth: Fix naming of eth_phy_read and eth_phy_write
stm32_eth: Remove obsolete test applications
drivers/eth-phy: add generic Ethernet PHY iface
cpu/stm32f4: implement eth driver peripheral
This implements the ethernet (MAC) peripheral of the stm32f4 as a
netdev driver.
boards/stm32f4discovery: add eth configuration
boards/stm32f4discovery: add feature stm32_eth
tests/stm32_eth_lwip: add test application
- EOP bit is cleared by writing 1 to the register.
- Guard EOP bit clear for STM32F2, STM32F4, STM32F7
and STM32L4 EOP bit is only set if EOPIE is enabled.
Since this is not the case for any platform we exclude
it when not needed.
- With this PR, On start up all GPIOs are configured as AIN. For stm32l0/4
this is done by default. Doing this saves the consumption of the input Schmitt
trigger in STOP mode which can reduce the consumption in at least 70%
from current master.
- The PNB in FLASH_CR wasn't cleared before every erase operation
and the new value was just stacked on top. After a couple of erase
the PNB written was overlapping with old ones failing to erase the
correct page.
In the `pwm_set` function, the switch-on and switch-off times for PWM channels were only determined for the following phase, but not for the current phase. This could result in a missing duty cycle when calling the function `pwm_set` if the switch-on time of the current phase was not yet reached or to an extended duty cycle if the switch-off time of the current phase had not yet been reached.
On cppcheck 1.82 it throws a warning.
Since it costs cycles and does nothing the ++dummy is (void)dummy.
A warning suppression is added so the CI is happy.
This fixes the positive result when master write data is NACKed.
This false positive occurs when the write frame is finished but a data nack occurred.
The AF check should occur first.
This commit fixes the clearing of a error condition after read.
This causes the incorrect errorcodes if the register is read
then an error occurs, then it is cleared.
By clearing only after the error is processed the bug is fixed.
This can be tested by reading a i2c slave that is not there.
There were still some things wrong with samd5x CPU init which only
showed up when used in conjunction with RIOTBOOT, that is cpu_init()
was called twice.
- gclk_connect() should block until the GCLK is ready.
- DPLL should be disabled dring configuration.
- make sure not to use DPLL for MCLK when re-configuring DPLL
- All APBxMASK bits should be in a defined state.
- always enable 1kHz oscilator output.
- Before, HSI was enabled as the default case when it is only
used for stm32f0 and stm32f1. It is now implemented explicitly
for those platforms, and only those.
- Since the Vector table must be naturally aligned to the next power
of two of the amount of supported ISR, and the table will be
placed after riotboot_hdr, we must ensure RIOTBOOT_HRD_LEN has the
same alignment.
This adds supoprt for the Atmel SAMD51 & SAME54 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
Atmel Software Framework (ASF) provides a set of low-level header files
that give access to different hardware peripherals of Atmel's ICs.
Origin: Atmel SAMD51 Series Device Support (1.1.96)
License: Apache-2.0
URL: http://packs.download.atmel.com/Atmel.SAMD51_DFP.1.1.96.atpack
Atmel Software Framework (ASF) provides a set of low-level header
files that give access to different hardware peripherals of Atmel's
ICs.
Origin: Atmel SAME54 Series Device Support (1.0.87)
License: Apache-2.0
URL: http://packs.download.atmel.com/Atmel.SAME54_DFP.1.0.87.atpack
This cleans up the sam0 timer driver:
- remove the check for the unused freq parameter
- the MCU provides dedicated SET/CLR registers to avoid
read-modify-write, so don't do read-modify-write on them.
- workaround a possible hardware bug on SAMD5x:
loop until the CMD_READSYNC is really set
