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cpu/cc26x0: Factor out code common for cc26xx/cc13xx family

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Signed-off-by: Anton Gerasimov <tossel@gmail.com>
This commit is contained in:
Anton Gerasimov 2018-06-18 20:34:08 +02:00
parent ea4b78654f
commit f6a3f14d22
31 changed files with 444 additions and 258 deletions
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4
boards/cc2650-launchpad/include/periph_conf.h
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@ -76,8 +76,8 @@ static const timer_conf_t timer_config[] = {
* @{
*/
#define UART_NUMOF (1)
#define UART_RX_PIN (2)
#define UART_TX_PIN (3)
#define UART0_RX_PIN (2)
#define UART0_TX_PIN (3)
/** @} */
/**

4
boards/cc2650stk/include/periph_conf.h
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@ -74,8 +74,8 @@ static const timer_conf_t timer_config[] = {
* @{
*/
#define UART_NUMOF (1)
#define UART_RX_PIN (28)
#define UART_TX_PIN (29)
#define UART0_RX_PIN (28)
#define UART0_TX_PIN (29)
/** @} */
/**

5
cpu/cc26x0/Makefile
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@ -2,9 +2,6 @@
MODULE = cpu
# Add a list of subdirectories, that should also be built:
DIRS = periph $(RIOTCPU)/cortexm_common
# (file triggers compiler bug. see #5775)
SRC_NOLTO += vectors.c
DIRS = periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/cc26xx_cc13xx
include $(RIOTBASE)/Makefile.base

6
cpu/cc26x0/Makefile.features
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@ -1,5 +1 @@
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_uart_modecfg
-include $(RIOTCPU)/cortexm_common/Makefile.features
-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features

4
cpu/cc26x0/Makefile.include
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@ -1,3 +1,7 @@
CPU_ARCH = cortex-m3
CPU_VARIANT = x0
VECTORS_O = $(BINDIR)/cc26xx_cc13xx/vectors.o
include ${RIOTCPU}/cc26xx_cc13xx/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

2
cpu/cc26x0/include/cc26x0_aux.h
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@ -18,7 +18,7 @@
#include <stdbool.h>
#include "cc26x0.h"
#include "cc26xx_cc13xx.h"
#ifdef __cplusplus
extern "C" {

2
cpu/cc26x0/include/cc26x0_fcfg.h
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@ -16,7 +16,7 @@
#ifndef CC26X0_FCFG_H
#define CC26X0_FCFG_H
#include <cc26x0.h>
#include <cc26xx_cc13xx.h>
#ifdef __cplusplus
extern "C" {

2
cpu/cc26x0/include/cc26x0_prcm.h
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@ -17,7 +17,7 @@
#ifndef CC26X0_PRCM_H
#define CC26X0_PRCM_H
#include <cc26x0.h>
#include <cc26xx_cc13xx.h>
#ifdef __cplusplus
extern "C" {

22
cpu/cc26x0/include/cpu_conf.h
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@ -14,40 +14,24 @@
* @brief Implementation specific CPU configuration options
*
* @author Leon M. George <leon@georgemail.eu>
* @author Anton Gerasimov <tossel@gmail.com>
*
*/
#ifndef CPU_CONF_H
#define CPU_CONF_H
#include "cpu_conf_common.h"
#include "cc26x0.h"
#include "cpu_conf_cc26xx_cc13xx.h"
#include "cc26x0_aux.h"
#include "cc26x0_ccfg.h"
#include "cc26x0_fcfg.h"
#include "cc26x0_gpio.h"
#include "cc26x0_gpt.h"
#include "cc26x0_i2c.h"
#include "cc26x0_ioc.h"
#include "cc26x0_prcm.h"
#include "cc26x0_uart.h"
#include "cc26x0_vims.h"
#include "cc26x0_wdt.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ARM Cortex-M specific CPU configuration
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (1U)
#define CPU_IRQ_NUMOF IRQN_COUNT
#define CPU_FLASH_BASE FLASH_BASE
/** @} */
/* Empty, but makes linter happy */
#ifdef __cplusplus
}

108
cpu/cc26x0/include/periph_cpu.h
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@ -19,120 +19,18 @@
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "cpu.h"
#include "periph_cpu_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Starting offset of CPU_ID
*/
#define CPUID_ADDR (&FCFG->MAC_BLE_0)
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (16U)
/**
* @name Power management configuration
* @{
*/
#define PROVIDES_PM_SET_LOWEST_CORTEXM
/** @} */
#ifndef DOXYGEN
/**
* @brief Override GPIO mode values
*/
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_IN = (IOCFG_INPUT_ENABLE | IOCFG_PULLCTL_OFF), /**< input w/o pull R */
GPIO_IN_PD = (IOCFG_INPUT_ENABLE | IOCFG_PULLCTL_DOWN), /**< input with pull-down */
GPIO_IN_PU = (IOCFG_INPUT_ENABLE | IOCFG_PULLCTL_UP), /**< input with pull-up */
GPIO_OUT = (IOCFG_PULLCTL_OFF), /**< push-pull output */
GPIO_OD = (IOCFG_IOMODE_OPEN_DRAIN | IOCFG_PULLCTL_OFF), /**< open-drain w/o pull R */
GPIO_OD_PU = (IOCFG_IOMODE_OPEN_DRAIN | IOCFG_PULLCTL_UP) /**< open-drain with pull-up */
} gpio_mode_t;
/**
* @brief Override GPIO flank values
*/
#define HAVE_GPIO_FLANK_T
typedef enum {
GPIO_FALLING = IOCFG_EDGEDET_FALLING,
GPIO_RISING = IOCFG_EDGEDET_RISING,
GPIO_BOTH = IOCFG_EDGEDET_BOTH
} gpio_flank_t;
/*
* @brief Invalid UART mode mask
*
* This mask is also used to force data_bits_t to be uint32_t type
* since it may be assigned a uint32_t variable in uart_mode
*/
#define UART_INVALID_MODE (0x8000000)
/**
* @brief Override parity values
* @{
*/
#define HAVE_UART_PARITY_T
typedef enum {
UART_PARITY_NONE = 0,
UART_PARITY_EVEN = (UART_LCRH_PEN | UART_LCRH_EPS),
UART_PARITY_ODD = UART_LCRH_PEN,
UART_PARITY_MARK = UART_INVALID_MODE | 4,
UART_PARITY_SPACE = UART_INVALID_MODE | 5
} uart_parity_t;
/** @} */
/**
* @brief Override data bits length values
* @{
*/
#define HAVE_UART_DATA_BITS_T
typedef enum {
UART_DATA_BITS_5 = UART_LCRH_WLEN_5,
UART_DATA_BITS_6 = UART_LCRH_WLEN_6,
UART_DATA_BITS_7 = UART_LCRH_WLEN_7,
UART_DATA_BITS_8 = UART_LCRH_WLEN_8
} uart_data_bits_t;
/** @} */
/**
* @brief Override stop bits length values
* @{
*/
#define HAVE_UART_STOP_BITS_T
typedef enum {
UART_STOP_BITS_1 = 0,
UART_STOP_BITS_2 = UART_LCRH_STP2,
} uart_stop_bits_t;
/** @} */
/**
* @brief Configuration of low-level general purpose timers
*
* General purpose timers (GPT[0-3]) are configured consecutively and in order
* (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
*/
typedef struct {
uint8_t cfg; /**< timer config [16,32 Bit] */
uint8_t chn; /**< number of channels [1,2] */
} timer_conf_t;
#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_READ_REGS
#define PERIPH_I2C_NEED_WRITE_REG
#define PERIPH_I2C_NEED_WRITE_REGS
#endif /* ifndef DOXYGEN */
// Empty, but makes linter happy
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CPU_H */
/** @} */

8
cpu/cc26xx_cc13xx/Makefile Normal file
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@ -0,0 +1,8 @@
MODULE = cc26xx_cc13xx
DIRS = periph
# (file triggers compiler bug. see #5775)
SRC_NOLTO += vectors.c
include $(RIOTBASE)/Makefile.base

5
cpu/cc26xx_cc13xx/Makefile.features Normal file
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@ -0,0 +1,5 @@
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_uart_modecfg
-include $(RIOTCPU)/cortexm_common/Makefile.features

5
cpu/cc26xx_cc13xx/Makefile.include Normal file
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@ -0,0 +1,5 @@
VARIANT = $(shell echo $(CPU_VARIANT) | tr 'a-z-' 'A-Z_')
CFLAGS += -DCPU_VARIANT_$(VARIANT)
USEMODULE += periph_common cc26xx_cc13xx_periph
INCLUDES += -I${RIOTCPU}/cc26xx_cc13xx/include

19
cpu/cc26xx_cc13xx/doc.txt Normal file
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@ -0,0 +1,19 @@
/**
* @defgroup cpu_cc26xx_cc13xx CC26xx_CC13xx common
* @ingroup cpu
* @brief Common code for TI cc26xx/cc13xx family
*
* This module contains code common to all cc26xx/cc13xx cpus
* supported by RIOT: @ref cpu_cc26x0, @ref cpu_cc13x2
*
*/
/**
* @defgroup cpu_cc26xx_cc13xx_definitions CC26xx_CC13xx common
* @ingroup cpu
* @brief Common definitions for TI cc26xx/cc13xx family
*
* This module contains definitions common to all cc26xx/cc13xx cpus
* supported by RIOT: @ref cpu_cc26x0, @ref cpu_cc13x2
*
*/

54
cpu/cc26x0/include/cc26x0.h → cpu/cc26xx_cc13xx/include/cc26xx_cc13xx.h
View File

@ -7,17 +7,18 @@
*/
/**
* @ingroup cpu_cc26x0_definitions
* @ingroup cpu_cc13x2_definitions
* @{
*
* @file
* @brief CC26x0 MCU interrupt definitions
* @brief CC13x2 MCU interrupt definitions
*
* @author Leon M. George <leon@georgemail.eu>
* @author Anton Gerasimov <tossel@gmail.com>
*/
#ifndef CC26X0_H
#define CC26X0_H
#ifndef CC26XX_CC13XX_H
#define CC26XX_CC13XX_H
#include <stdint.h>
@ -28,29 +29,29 @@ extern "C" {
typedef volatile uint8_t reg8_t;
typedef volatile uint32_t reg32_t;
/** @addtogroup CC26x0_cmsis CMSIS Definitions */
/** @addtogroup CC13x2_cmsis CMSIS Definitions */
/*@{*/
/** interrupt number definition */
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ****************************/
/****** Cortex-M4 Processor Exceptions Numbers ****************************/
ResetHandler_IRQn = -15, /**< 1 Reset Handler */
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /**< 3 Cortex-M3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = - 5, /**< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = - 4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = - 2, /**< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = - 1, /**< 15 Cortex-M3 System Tick Interrupt */
HardFault_IRQn = -13, /**< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = - 5, /**< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = - 4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = - 2, /**< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = - 1, /**< 15 Cortex-M4 System Tick Interrupt */
/****** CC26x0 specific Interrupt Numbers *********************************/
/****** CC13x2 specific Interrupt Numbers *********************************/
EDGE_DETECT_IRQN = 0, /**< 16 AON edge detect */
I2C_IRQN = 1, /**< 17 I2C */
RF_CPE1_IRQN = 2, /**< 18 RF Command and Packet Engine 1 */
SPIS_IRQN = 3, /**< 19 AON SpiSplave Rx, Tx and CS */
PKA_IRQN = 3, /**< 19 PKA interrupt */
AON_RTC_IRQN = 4, /**< 20 AON RTC */
UART0_IRQN = 5, /**< 21 UART0 Rx and Tx */
AON_AUX_SWEV0_IRQN = 6, /**< 22 Sensor Controller software event 0, through AON domain*/
@ -81,16 +82,25 @@ typedef enum IRQn
AUX_COMPA_IRQN = 31, /**< 47 AUX Comparator A */
AUX_ADC_IRQN = 32, /**< 48 AUX ADC IRQ */
TRNG_IRQN = 33, /**< 49 TRNG event */
#ifdef CPU_VARIANT_X2
OSC_IRQN = 34, /**< 50 Combined event from oscillator control */
AUX_TIMER2_IRQN = 35, /**< 51 AUX Timer 2 event 0 */
UART1_IRQN = 36, /**< 52 UART1 combined interrupt */
BATMON_IRQN = 37, /**< 53 UART1 combined interrupt */
IRQN_COUNT = (BATMON_IRQN + 1) /**< Number of peripheral IDs */
#else
IRQN_COUNT = (TRNG_IRQN + 1) /**< Number of peripheral IDs */
#endif
} IRQn_Type;
/**
* @brief Configuration of the Cortex-M3 processor and core peripherals
* @brief Configuration of the Cortex-M4 processor and core peripherals
*/
#define __MPU_PRESENT 1 /**< CC26x0 does provide a MPU */
#define __NVIC_PRIO_BITS 3 /**< CC26x0 offers priority levels from 0..7 */
#define __MPU_PRESENT 1 /**< CC13x2 does provide a MPU */
#define __NVIC_PRIO_BITS 3 /**< CC13x2 offers priority levels from 0..7 */
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick config is used */
#define RCOSC48M_FREQ 48000000 /**< 48 MHz */
@ -99,7 +109,11 @@ typedef enum IRQn
/**
* @brief CMSIS includes
*/
#ifdef CPU_VARIANT_X2
#include <core_cm4.h>
#else
#include <core_cm3.h>
#endif
/*@}*/
/** @ingroup cpu_specific_peripheral_memory_map
@ -113,6 +127,6 @@ typedef enum IRQn
}
#endif
#endif /* CC26X0_H */
#endif /* CC26XX_CC13XX_H */
/*@}*/

12
cpu/cc26x0/include/cc26x0_ccfg.h → cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ccfg.h
View File

@ -6,17 +6,17 @@
* details.
*/
/**
* @ingroup cpu_cc26x0_definitions
* @ingroup cpu_cc26xx_cc13xx_definitions
* @{
*
* @file
* @brief CC26x0 CCFG register definitions
* @brief CC26xx/CC13xx CCFG register definitions
*/
#ifndef CC26X0_CCFG_H
#define CC26X0_CCFG_H
#ifndef CC26XX_CC13XX_CCFG_H
#define CC26XX_CC13XX_CCFG_H
#include <cc26x0.h>
#include <cc26xx_cc13xx.h>
#ifdef __cplusplus
extern "C" {
@ -65,6 +65,6 @@ typedef struct {
} /* end extern "C" */
#endif
#endif /* CC26X0_CCFG_H */
#endif /* CC26XX_CC13XX_CCFG_H */
/*@}*/

12
cpu/cc26x0/include/cc26x0_gpio.h → cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_gpio.h
View File

@ -6,20 +6,20 @@
* details.
*/
/**
* @ingroup cpu_cc26x0_definitions
* @ingroup cpu_cc26xx_cc13xx_definitions
* @{
*
* @file
* @brief Driver for the cc26x0 GPIO controller
* @brief Driver for the cc26xx/cc13xx GPIO controller
*
* @author Leon George <leon@georgemail.eu>
*
*/
#ifndef CC26X0_GPIO_H
#define CC26X0_GPIO_H
#ifndef CC26XX_CC13XX_GPIO_H
#define CC26XX_CC13XX_GPIO_H
#include "cc26x0.h"
#include "cc26xx_cc13xx.h"
#ifdef __cplusplus
extern "C" {
@ -58,6 +58,6 @@ typedef struct {
} /* end extern "C" */
#endif
#endif /* CC26X0_GPIO_H */
#endif /* CC26XX_CC13XX_GPIO_H */
/** @} */

12
cpu/cc26x0/include/cc26x0_gpt.h → cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_gpt.h
View File

@ -7,19 +7,19 @@
*/
/**
* @ingroup cpu_cc26x0_definitions
* @ingroup cpu_cc26xx_cc13xx_definitions
* @{
*
* @file
* @brief definitions for the CC26x0 GPT moduls
* @brief definitions for the CC26xx/CC13XX GPT modules
*
* @author Leon George <leon@georgemail.eu>
*/
#ifndef CC26X0_GPT_H
#define CC26X0_GPT_H
#ifndef CC26XX_CC13XX_GPT_H
#define CC26XX_CC13XX_GPT_H
#include "cc26x0.h"
#include "cc26xx_cc13xx.h"
#ifdef __cplusplus
extern "C" {
@ -207,5 +207,5 @@ typedef struct {
}
#endif
#endif /* CC26X0_GPT_H */
#endif /* CC26XX_CC13XX_GPT_H */
/** @} */

12
cpu/cc26x0/include/cc26x0_i2c.h → cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_i2c.h
View File

@ -7,19 +7,19 @@
*/
/**
* @ingroup cpu_cc26x0_definitions
* @ingroup cpu_cc26xx_cc13xx_definitions
* @{
*
* @file
* @brief CC26x0 MCU I/O register definitions
* @brief CC26xx/CC13xx MCU I/O register definitions
*
* @author Leon George <leon@georgemail.eu>
*/
#ifndef CC26X0_I2C_H
#define CC26X0_I2C_H
#ifndef CC26XX_CC13XX_I2C_H
#define CC26XX_CC13XX_I2C_H
#include "cc26x0.h"
#include "cc26xx_cc13xx.h"
#ifdef __cplusplus
extern "C" {
@ -199,6 +199,6 @@ cycle or continues on to a repeated START condition
}
#endif
#endif /* CC26X0_I2C_H */
#endif /* CC26XX_CC13XX_I2C_H */
/*@}*/

24
cpu/cc26x0/include/cc26x0_ioc.h → cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ioc.h
View File

@ -7,19 +7,19 @@
*/
/**
* @ingroup cpu_cc26x0_definitions
* @ingroup cpu_cc26xx_cc13xx_definitions
* @{
*
* @file
* @brief CC26x0 MCU I/O register definitions
* @brief CC26xx/CC13xx MCU I/O register definitions
*
* @author Leon George <leon@georgemail.eu>
*/
#ifndef CC26X0_IOC_H
#define CC26X0_IOC_H
#ifndef CC26XX_CC13XX_IOC_H
#define CC26XX_CC13XX_IOC_H
#include "cc26x0.h"
#include "cc26xx_cc13xx.h"
#ifdef __cplusplus
extern "C" {
@ -48,10 +48,14 @@ typedef struct {
* @{
*/
#define IOCFG_PORTID_GPIO 0x00000000 /**< GPIO */
#ifdef CPU_VARIANT_X0
#define IOCFG_PORTID_AON_SCS 0x00000001 /**< AON SPI-S SCS */
#define IOCFG_PORTID_AON_SCK 0x00000002 /**< AON SPI-S SCK */
#define IOCFG_PORTID_AON_SDI 0x00000003 /**< AON SPI-S SDI */
#define IOCFG_PORTID_AON_SDO 0x00000004 /**< AON SPI-S SDO */
#endif //CPU_VARIANT_X0
#define IOCFG_PORTID_AON_CLK32K 0x00000007 /**< AON external 32kHz clock */
#define IOCFG_PORTID_AUX_IO 0x00000008 /**< AUX IO */
#define IOCFG_PORTID_SSI0_RX 0x00000009 /**< SSI0 receive */
@ -64,6 +68,14 @@ typedef struct {
#define IOCFG_PORTID_UART0_TX 0x00000010 /**< UART0 transmit */
#define IOCFG_PORTID_UART0_CTS 0x00000011 /**< UART0 clear to send */
#define IOCFG_PORTID_UART0_RTS 0x00000012 /**< UART0 request to send */
#ifdef CPU_VARIANT_X2
#define IOCFG_PORTID_UART1_RX 0x00000013 /**< UART1 receive */
#define IOCFG_PORTID_UART1_TX 0x00000014 /**< UART1 transmit */
#define IOCFG_PORTID_UART1_CTS 0x00000015 /**< UART1 clear to send */
#define IOCFG_PORTID_UART1_RTS 0x00000016 /**< UART1 request to send */
#endif // CPU_VARIANT_X2
#define IOCFG_PORTID_PORT_EVT0 0x00000017 /**< PORT EVENT 0 */
#define IOCFG_PORTID_PORT_EVT1 0x00000018 /**< PORT EVENT 1 */
#define IOCFG_PORTID_PORT_EVT2 0x00000019 /**< PORT EVENT 2 */
@ -159,6 +171,6 @@ typedef struct {
}
#endif
#endif /* CC26X0_IOC_H */
#endif /* CC26XX_CC13XX_IOC_H */
/*@}*/

18
cpu/cc26x0/include/cc26x0_uart.h → cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_uart.h
View File

@ -7,24 +7,25 @@
*/
/**
* @addtogroup cpu_cc26x0_definitions
* @addtogroup cpu_cc13x2_definitions
* @{
*
* @file
* @brief CC26x0 UART interface
* @brief CC13x2 UART interface
*
*/
#ifndef CC26X0_UART_H
#define CC26X0_UART_H
#ifndef CC26XX_CC13XX_UART_H
#define CC26XX_CC13XX_UART_H
#include "cc26x0.h"
#include "cc26xx_cc13xx.h"
#ifdef __cplusplus
extern "C" {
#endif
#define UART_BASE (0x40001000) /**< UART base address */
#define UART0_BASE (0x40001000) /**< UART0 base address */
#define UART1_BASE (0x40008000) /**< UART1 base address */
/**
* @brief UART component registers
@ -122,11 +123,12 @@ typedef struct {
#define UART_IFLS_RXSEL_7_8 0x20
/** @} */
#define UART ((uart_regs_t *) (UART_BASE)) /**< UART register bank */
#define UART0 ((uart_regs_t *) (UART0_BASE)) /**< UART0 register bank */
#define UART1 ((uart_regs_t *) (UART1_BASE)) /**< UART0 register bank */
#ifdef __cplusplus
} /* end extern "C" */
#endif
#endif /* CC26X0_UART_H */
#endif /* CC26XX_CC13XX_UART_H */
/** @} */

13
cpu/cc26x0/include/cc26x0_vims.h → cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_vims.h
View File

@ -7,15 +7,15 @@
*/
/**
* @ingroup cpu_cc26x0_definitions
* @ingroup cpu_cc26xx_cc13xx_definitions
* @{
*
* @file
* @brief CC26x0 VIMS register definitions
* @brief CC26xx/CC13xx VIMS register definitions
*/
#ifndef CC26X0_VIMS_H
#define CC26X0_VIMS_H
#ifndef CC26XX_CC13XX_VIMS_H
#define CC26XX_CC13XX_VIMS_H
#ifdef __cplusplus
extern "C" {
@ -155,7 +155,8 @@ typedef struct {
reg32_t __reserved19[2]; /**< meh */
reg32_t FSM_BSLP0; /**< FMC FSM bank sector lock program 0 */
reg32_t FSM_BSLP1; /**< FMC FSM bank sector lock program 1 */
reg32_t __reserved20[0x42]; /**< meh */
reg32_t FSM_PGM_128; /**< Enable 128-bit programming. CC26x2_CC13x2 only */
reg32_t __reserved20[0x41]; /**< meh */
reg32_t FCFG_BANK; /**< FMC flash configuration bank */
reg32_t FCFG_WRAPPER; /**< FMC flash wrapper configuration */
reg32_t FCFG_BNK_TYPE; /**< FMC flash bank type */
@ -232,6 +233,6 @@ typedef struct {
}
#endif
#endif /* CC26X0_VIMS_H */
#endif /* CC26XX_CC13XX_VIMS_H */
/*@}*/

12
cpu/cc26x0/include/cc26x0_wdt.h → cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_wdt.h
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@ -7,17 +7,17 @@
*/
/**
* @ingroup cpu_cc26x0_definitions
* @ingroup cpu_cc26xx_cc13xx_definitions
* @{
*
* @file
* @brief CC26x0 WDT register definitions
* @brief CC26xx/CC13xx WDT register definitions
*/
#ifndef CC26X0_WDT_H
#define CC26X0_WDT_H
#ifndef CC26XX_CC13XX_WDT_H
#define CC26XX_CC13XX_WDT_H
#include <cc26x0.h>
#include <cc26xx_cc13xx.h>
#ifdef __cplusplus
extern "C" {
@ -51,6 +51,6 @@ typedef struct {
} /* end extern "C" */
#endif
#endif /* CC26X0_WDT_H */
#endif /* CC26XX_CC13XX_WDT_H */
/*@}*/

54
cpu/cc26xx_cc13xx/include/cpu_conf_cc26xx_cc13xx.h Normal file
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@ -0,0 +1,54 @@
/*
* Copyright (C) 2016 Leon George
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_cc26xx_cc13xx
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Leon M. George <leon@georgemail.eu>
*
*/
#ifndef CPU_CONF_CC26XX_CC13XX_H
#define CPU_CONF_CC26XX_CC13XX_H
#include "cpu_conf_common.h"
#include "cc26xx_cc13xx.h"
#include "cc26xx_cc13xx_ccfg.h"
#include "cc26xx_cc13xx_gpio.h"
#include "cc26xx_cc13xx_gpt.h"
#include "cc26xx_cc13xx_i2c.h"
#include "cc26xx_cc13xx_ioc.h"
#include "cc26xx_cc13xx_uart.h"
#include "cc26xx_cc13xx_vims.h"
#include "cc26xx_cc13xx_wdt.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ARM Cortex-M specific CPU configuration
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (1U)
#define CPU_IRQ_NUMOF IRQN_COUNT
#define CPU_FLASH_BASE FLASH_BASE
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_CC26XX_CC13XX_H */
/** @} */

137
cpu/cc26xx_cc13xx/include/periph_cpu_common.h Normal file
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@ -0,0 +1,137 @@
/*
* Copyright (C) 2016 Leon George
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc26xx_cc13xx
* @{
*
* @file
* @brief CPU specific definitions for internal peripheral handling
*
* @author Leon M. George <leon@georgemail.de>
*/
#ifndef PERIPH_CPU_COMMON_H
#define PERIPH_CPU_COMMON_H
#include "cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Starting offset of CPU_ID
*/
#define CPUID_ADDR (&FCFG->MAC_BLE_0)
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (16U)
/**
* @name Power management configuration
* @{
*/
#define PROVIDES_PM_SET_LOWEST_CORTEXM
/** @} */
#ifndef DOXYGEN
/**
* @brief Override GPIO mode values
*/
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_IN = (IOCFG_INPUT_ENABLE | IOCFG_PULLCTL_OFF), /**< input w/o pull R */
GPIO_IN_PD = (IOCFG_INPUT_ENABLE | IOCFG_PULLCTL_DOWN), /**< input with pull-down */
GPIO_IN_PU = (IOCFG_INPUT_ENABLE | IOCFG_PULLCTL_UP), /**< input with pull-up */
GPIO_OUT = (IOCFG_PULLCTL_OFF), /**< push-pull output */
GPIO_OD = (IOCFG_IOMODE_OPEN_DRAIN | IOCFG_PULLCTL_OFF), /**< open-drain w/o pull R */
GPIO_OD_PU = (IOCFG_IOMODE_OPEN_DRAIN | IOCFG_PULLCTL_UP) /**< open-drain with pull-up */
} gpio_mode_t;
/**
* @brief Override GPIO flank values
*/
#define HAVE_GPIO_FLANK_T
typedef enum {
GPIO_FALLING = IOCFG_EDGEDET_FALLING,
GPIO_RISING = IOCFG_EDGEDET_RISING,
GPIO_BOTH = IOCFG_EDGEDET_BOTH
} gpio_flank_t;
/*
* @brief Invalid UART mode mask
*
* This mask is also used to force data_bits_t to be uint32_t type
* since it may be assigned a uint32_t variable in uart_mode
*/
#define UART_INVALID_MODE (0x8000000)
/**
* @brief Override parity values
* @{
*/
#define HAVE_UART_PARITY_T
typedef enum {
UART_PARITY_NONE = 0,
UART_PARITY_EVEN = (UART_LCRH_PEN | UART_LCRH_EPS),
UART_PARITY_ODD = UART_LCRH_PEN,
UART_PARITY_MARK = UART_INVALID_MODE | 4,
UART_PARITY_SPACE = UART_INVALID_MODE | 5
} uart_parity_t;
/** @} */
/**
* @brief Override data bits length values
* @{
*/
#define HAVE_UART_DATA_BITS_T
typedef enum {
UART_DATA_BITS_5 = UART_LCRH_WLEN_5,
UART_DATA_BITS_6 = UART_LCRH_WLEN_6,
UART_DATA_BITS_7 = UART_LCRH_WLEN_7,
UART_DATA_BITS_8 = UART_LCRH_WLEN_8
} uart_data_bits_t;
/** @} */
/**
* @brief Override stop bits length values
* @{
*/
#define HAVE_UART_STOP_BITS_T
typedef enum {
UART_STOP_BITS_1 = 0,
UART_STOP_BITS_2 = UART_LCRH_STP2,
} uart_stop_bits_t;
/** @} */
/**
* @brief Configuration of low-level general purpose timers
*
* General purpose timers (GPT[0-3]) are configured consecutively and in order
* (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
*/
typedef struct {
uint8_t cfg; /**< timer config [16,32 Bit] */
uint8_t chn; /**< number of channels [1,2] */
} timer_conf_t;
#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_READ_REGS
#define PERIPH_I2C_NEED_WRITE_REG
#define PERIPH_I2C_NEED_WRITE_REGS
#endif /* ifndef DOXYGEN */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CPU_COMMON_H */
/** @} */

3
cpu/cc26xx_cc13xx/periph/Makefile Normal file
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@ -0,0 +1,3 @@
MODULE = cc26xx_cc13xx_periph
include $(RIOTMAKE)/periph.mk

6
cpu/cc26x0/periph/gpio.c → cpu/cc26xx_cc13xx/periph/gpio.c
View File

@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_cc26x0
* @ingroup cpu_cc26xx_cc13xx
* @ingroup drivers_periph_gpio
* @{
*
@ -124,8 +124,8 @@ void isr_edge(void)
{
for (unsigned pin = 0; pin < GPIO_ISR_CHAN_NUMOF; pin++) {
/* doc claims EVFLAGS will only be set for pins that have edge detection enabled */
if (GPIO->EVFLAGS & (1 << pin)) {
GPIO->EVFLAGS |= (1 << pin);
if (GPIO->EVFLAGS & (1UL << pin)) {
GPIO->EVFLAGS |= (1UL << pin);
gpio_chan[pin].cb(gpio_chan[pin].arg);
}
}

0
cpu/cc26x0/periph/pm.c → cpu/cc26xx_cc13xx/periph/pm.c
View File

2
cpu/cc26x0/periph/timer.c → cpu/cc26xx_cc13xx/periph/timer.c
View File

@ -8,7 +8,7 @@
*/
/**
* @ingroup cpu_cc26x0
* @ingroup cpu_cc26xx_cc13xx
* @ingroup drivers_periph_timer
* @{
*

100
cpu/cc26x0/periph/uart.c → cpu/cc26xx_cc13xx/periph/uart.c
View File

@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_cc26x0
* @ingroup cpu_cc26xx_cc13xx
* @ingroup drivers_periph_uart
* @{
*
@ -15,6 +15,7 @@
* @brief Low-level UART driver implementation
*
* @author Leon M. George <leon@georgemail.eu>
* @author Anton Gerasimov <tossel@gmail.com>
*
* @}
*/
@ -44,50 +45,70 @@
*/
static uart_isr_ctx_t ctx[UART_NUMOF];
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
/* make sure the uart device is valid */
if (uart != 0) {
if (uart > UART_NUMOF) {
return UART_NODEV;
}
#if defined(CPU_VARIANT_X2)
uart_regs_t *uart_reg = (uart == 1) ? UART1 : UART0;
int tx_pin = (uart == 1) ? UART1_TX_PIN : UART0_TX_PIN;
int rx_pin = (uart == 1) ? UART1_RX_PIN : UART0_RX_PIN;
int irqn = (uart == 1) ? UART1_IRQN : UART0_IRQN;
# if UART_HW_FLOW_CONTROL
int rts_pin = (uart == 1) ? UART1_RTS_PIN : UART0_RTS_PIN;
int cts_pin = (uart == 1) ? UART1_CTS_PIN : UART0_CTS_PIN;
# endif // UART_HW_FLOW_CONTROL
#elif defined(CPU_VARIANT_X0)
uart_regs_t *uart_reg = UART0;
int tx_pin = UART0_TX_PIN;
int rx_pin = UART0_RX_PIN;
int irqn = UART0_IRQN;
# if UART_HW_FLOW_CONTROL
int rts_pin = UART0_RTS_PIN;
int cts_pin = UART0_CTS_PIN;
# endif // UART_HW_FLOW_CONTROL
#endif // CPU_VARIANT_X2
/* enable clocks: serial power domain and UART */
PRCM->PDCTL0SERIAL = 1;
while (!(PRCM->PDSTAT0 & PDSTAT0_SERIAL_ON)) ;
uart_poweron(uart);
/* disable and reset the UART */
UART->CTL = 0;
uart_reg->CTL = 0;
/* save context */
ctx[0].rx_cb = rx_cb;
ctx[0].arg = arg;
ctx[uart].rx_cb = rx_cb;
ctx[uart].arg = arg;
/* configure pins */
IOC->CFG[UART_TX_PIN] = IOCFG_PORTID_UART0_TX;
IOC->CFG[UART_RX_PIN] = (IOCFG_PORTID_UART0_RX | IOCFG_INPUT_ENABLE);
IOC->CFG[tx_pin] = IOCFG_PORTID_UART0_TX;
IOC->CFG[rx_pin] = (IOCFG_PORTID_UART0_RX | IOCFG_INPUT_ENABLE);
#if UART_HW_FLOW_CONTROL
IOC->CFG[UART_RTS_PIN] = IOCFG_PORTID_UART0_RTS;
IOC->CFG[UART_CTS_PIN] = (IOCFG_PORTID_UART0_CTS | IOCFG_INPUT_ENABLE);
IOC->CFG[rts_pin] = IOCFG_PORTID_UART0_RTS;
IOC->CFG[cts_pin] = (IOCFG_PORTID_UART0_CTS | IOCFG_INPUT_ENABLE);
#endif
/* calculate baud-rate */
uint32_t tmp = (CLOCK_CORECLOCK * 4);
tmp += (baudrate / 2);
tmp /= baudrate;
UART->IBRD = (tmp >> FRAC_BITS);
UART->FBRD = (tmp & FRAC_MASK);
uart_reg->IBRD = (tmp >> FRAC_BITS);
uart_reg->FBRD = (tmp & FRAC_MASK);
/* configure line to 8N1 mode, LRCH must be written after IBRD and FBRD! */
UART->LCRH = UART_LCRH_WLEN_8;
uart_reg->LCRH = UART_LCRH_WLEN_8;
/* enable the RX interrupt */
UART->IMSC = UART_IMSC_RXIM;
NVIC_EnableIRQ(UART0_IRQN);
uart_reg->IMSC = UART_IMSC_RXIM;
NVIC_EnableIRQ(irqn);
/* start the UART */
UART->CTL = ENABLE_MASK;
uart_reg->CTL = ENABLE_MASK;
return UART_OK;
}
@ -112,22 +133,26 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity,
stop_bits == UART_STOP_BITS_2);
/* make sure the uart device is valid */
if (uart != 0) {
if (uart >= UART_NUMOF) {
return UART_NODEV;
}
uart_regs_t *uart_reg = (uart == 1) ? UART1 : UART0;
/* cc26x0 does not support mark or space parity */
if (parity == UART_PARITY_MARK || parity == UART_PARITY_SPACE) {
return UART_NOMODE;
}
/* Disable UART and clear old settings */
UART->CTL = 0;
UART->LCRH = 0;
uart_reg->CTL = 0;
uart_reg->LCRH = 0;
/* Apply setting and enable UART */
UART->LCRH = data_bits | parity | stop_bits;
UART->CTL = ENABLE_MASK;
/* cppcheck-suppress redundantAssignment
* (reason: disable-enable cycle requires writing zero first) */
uart_reg->LCRH = data_bits | parity | stop_bits;
uart_reg->CTL = ENABLE_MASK;
return UART_OK;
}
@ -135,30 +160,30 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity,
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
(void) uart;
uart_regs_t *uart_reg = (uart == 1) ? UART1 : UART0;
for (size_t i = 0; i < len; i++) {
while (UART->FR & UART_FR_TXFF) {}
UART->DR = data[i];
while (uart_reg->FR & UART_FR_TXFF) {}
uart_reg->DR = data[i];
}
}
void uart_poweron(uart_t uart)
{
(void) uart;
uart_regs_t *uart_reg = (uart == 1) ? UART1 : UART0;
PRCM->UARTCLKGR = 1;
PRCM->UARTCLKGR |= 0x1;
PRCM->CLKLOADCTL = CLKLOADCTL_LOAD;
while (!(PRCM->CLKLOADCTL & CLKLOADCTL_LOADDONE)) {}
UART->CTL = ENABLE_MASK;
uart_reg->CTL = ENABLE_MASK;
}
void uart_poweroff(uart_t uart)
{
(void) uart;
uart_regs_t *uart_reg = (uart == 1) ? UART1 : UART0;
UART->CTL = 0;
uart_reg->CTL = 0;
PRCM->UARTCLKGR = 0;
PRCM->CLKLOADCTL = CLKLOADCTL_LOAD;
@ -166,17 +191,26 @@ void uart_poweroff(uart_t uart)
}
void isr_uart(void)
static void isr_uart(uart_t uart)
{
uart_regs_t *uart_reg = (uart == 1) ? UART1 : UART0;
/* remember pending interrupts */
uint32_t mis = UART->MIS;
uint32_t mis = uart_reg->MIS;
/* clear them */
UART->ICR = mis;
uart_reg->ICR = mis;
/* read received byte and pass it to the RX callback */
if (mis & UART_MIS_RXMIS) {
ctx[0].rx_cb(ctx[0].arg, (uint8_t)UART->DR);
ctx[uart].rx_cb(ctx[uart].arg, (uint8_t)uart_reg->DR);
}
cortexm_isr_end();
}
void isr_uart0(void) {
isr_uart(0);
}
void isr_uart1(void) {
isr_uart(1);
}

35
cpu/cc26x0/vectors.c → cpu/cc26xx_cc13xx/vectors.c
View File

@ -7,13 +7,14 @@
*/
/**
* @ingroup cpu_cc26x0
* @ingroup cpu_cc26xx_cc13xx
* @{
*
* @file
* @brief Interrupt vector definitions
*
* @author Leon M. George <leon@georgemail.eu>
* @author Anton Gerasimov <tossel@gmail.com>
*/
#include <stdint.h>
@ -27,21 +28,21 @@ void dummy_handler(void) {
dummy_handler_default();
}
/* CC26x0 specific interrupt vectors */
/* CC26xx_CC13xx specific interrupt vectors */
WEAK_DEFAULT void isr_edge(void);
WEAK_DEFAULT void isr_i2c(void);
WEAK_DEFAULT void isr_rfc_cpe1(void);
WEAK_DEFAULT void isr_aon_rx_tx_cs(void);
WEAK_DEFAULT void isr_pka(void);
WEAK_DEFAULT void isr_aon_rtc(void);
WEAK_DEFAULT void isr_uart(void);
WEAK_DEFAULT void isr_scse0_aon(void);
WEAK_DEFAULT void isr_uart0(void);
WEAK_DEFAULT void isr_aux0_aon(void);
WEAK_DEFAULT void isr_ssi0(void);
WEAK_DEFAULT void isr_ssi1(void);
WEAK_DEFAULT void isr_rfc_cpe0(void);
WEAK_DEFAULT void isr_rfc_hw(void);
WEAK_DEFAULT void isr_rfc_cmd_ack(void);
WEAK_DEFAULT void isr_i2s(void);
WEAK_DEFAULT void isr_scse1_aon(void);
WEAK_DEFAULT void isr_aux1_aon(void);
WEAK_DEFAULT void isr_watchdog(void);
WEAK_DEFAULT void isr_timer0_chan0(void);
WEAK_DEFAULT void isr_timer0_chan1(void);
@ -62,23 +63,29 @@ WEAK_DEFAULT void isr_dyn_prog(void);
WEAK_DEFAULT void isr_comp(void);
WEAK_DEFAULT void isr_adc(void);
WEAK_DEFAULT void isr_trng(void);
#ifdef CPU_VARIANT_X2
WEAK_DEFAULT void isr_osc(void);
WEAK_DEFAULT void isr_aux_timer2(void);
WEAK_DEFAULT void isr_uart1(void);
WEAK_DEFAULT void isr_batmon(void);
#endif // CPU_VARIANT_X2
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
ISR_VECTOR(1) const isr_t vector_cpu[] = {
isr_edge, /* 16 AON edge detect */
isr_i2c, /* 17 I2C */
isr_rfc_cpe1, /* 18 RF Command and Packet Engine 1 */
isr_aon_rx_tx_cs, /* 19 AON SpiSplave Rx, Tx and CS */
isr_pka, /* 19 PKA interrupt */
isr_aon_rtc, /* 20 AON RTC */
isr_uart, /* 21 UART0 Rx and Tx */
isr_scse0_aon, /* 22 Sensor Controller software event 0, through AON domain */
isr_uart0, /* 21 UART0 Rx and Tx */
isr_aux0_aon, /* 22 AUX event 0, through AON domain */
isr_ssi0, /* 23 SSI0 Rx and Tx */
isr_ssi1, /* 24 SSI1 Rx and Tx */
isr_rfc_cpe0, /* 25 RF Command and Packet Engine 0 */
isr_rfc_hw, /* 26 RF Core Hardware */
isr_rfc_cmd_ack, /* 27 RF Core Command Acknowledge */
isr_i2s, /* 28 I2S */
isr_scse1_aon, /* 29 Sensor Controller software event 1, through AON domain */
isr_aux1_aon, /* 29 AUX event 1, through AON domain */
isr_watchdog, /* 30 Watchdog timer */
isr_timer0_chan0, /* 31 Timer 0 subtimer A */
isr_timer0_chan1, /* 32 Timer 0 subtimer B */
@ -99,6 +106,12 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_comp, /* 47 AUX Comparator A */
isr_adc, /* 48 AUX ADC IRQ */
isr_trng, /* 49 TRNG event */
#ifdef CPU_VARIANT_X2
isr_osc, /* 50 Combined event from oscillator control */
isr_aux_timer2, /* 51 AUX Timer 2 event 0 */
isr_uart1, /* 52 UART 1 RX and TX */
isr_batmon, /* 53 BATMON interrupt */
#endif // CPU_VARIANT_X2
};
/** @} */