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Merge pull request #10941 from keestux/update-samr30-vendor

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cpu/samr30: update vendor files using ASF 3.35.1
This commit is contained in:
Alexandre Abadie 2019-10-02 13:35:06 +02:00 committed by GitHub
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26 changed files with 90 additions and 137 deletions
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3
cpu/sam0_common/include/vendor/README.md vendored
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@ -2,8 +2,7 @@
The include files in this directory tree are copied from Atmel
sources. Most of the sam0 files are from ASF (Atmel Software Foundation,
version 3.35.1). The SAMR30 files are from ASF 3.34.2. The SAML10 and
SAML11 files are from, so called, atpacks.
version 3.35.1). The SAML10 and SAML11 files are from, so called, atpacks.
## The sam0 files

48
cpu/sam0_common/include/vendor/samr30/README.md vendored
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@ -1,48 +0,0 @@
# CMSIS from Atmel Software Foundation (ASF)
The include files in the directory tree are copied from ASF. See
https://spaces.atmel.com/gf/project/asf/frs/?action=FrsReleaseBrowse&frs_package_id=4
(dd. 2017-04-13 ASF version 3.34.2 was used)
The directory tree was copied "as is" and its structure is as follows:
cmsis
└── samr30
├── include
│ ├── component
│ ├── instance
│ └── pio
└── source
├── gcc
└── iar
There is only one include file (per CPU variant) that should be included in
the source code. For SAMR30 that is cmsis/saml21/include/samr30.h. But
that will only work if the proper define is set. The define is named after
the variant, for example `__SAMR30G18A__`. This define must be set in the
`Makefile.include` of the board.
Be aware that if you want to make changes to any file in this tree that the
changes will be lost when a new ASF release is going to be used.
## Trailing White Space
Because of the whitespace check (dist/tools/whitespacecheck/check.sh) all
the trailing white space had to be removed. Please take this into account
when comparing to the original ASF distribution.
find include/ -name '*.h' -exec sed -i 's/\s*$//' '{}' +
find include_b/ -name '*.h' -exec sed -i 's/\s*$//' '{}' +
## LITTLE_ENDIAN
These include files define `LITTLE_ENDIAN`. But we think this is wrong. It
seems more logical to let the compiler decide in which mode the ARM code is
to be translated. In include/machine/endian.h there is already a define of
`LITTLE_ENDIAN` (and `BIG_ENDIAN`) for a different purpose.
So, we decided to remove the define from the ASF CMSIS files. The command
for it (running from this directory) is:
find include/ -name '*.h' -exec sed -i '/^#define\s\s*LITTLE_ENDIAN/d' '{}' +
find include_b/ -name '*.h' -exec sed -i '/^#define\s\s*LITTLE_ENDIAN/d' '{}' +

2
cpu/sam0_common/include/vendor/samr30/include/instance/dsu.h vendored
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@ -104,6 +104,6 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DSU peripheral ========== */
#define DSU_CLK_AHB_ID 5
#define DSU_CLK_AHB_ID 5
#endif /* _SAMR30_DSU_INSTANCE_ */

8
cpu/sam0_common/include/vendor/samr30/include/instance/eic.h vendored
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@ -72,9 +72,9 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for EIC peripheral ========== */
#define EIC_EXTINT_NUM 16
#define EIC_GCLK_ID 3
#define EIC_NUMBER_OF_CONFIG_REGS 2
#define EIC_NUMBER_OF_INTERRUPTS 16
#define EIC_EXTINT_NUM 16
#define EIC_GCLK_ID 3
#define EIC_NUMBER_OF_CONFIG_REGS 2
#define EIC_NUMBER_OF_INTERRUPTS 16
#endif /* _SAMR30_EIC_INSTANCE_ */

24
cpu/sam0_common/include/vendor/samr30/include/instance/gclk.h vendored
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@ -144,22 +144,22 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for GCLK peripheral ========== */
#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_BITS 4
#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_BITS 4
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
#define GCLK_NUM 36 // Number of Generic Clock Users
#define GCLK_SOURCE_BITS 4
#define GCLK_SOURCE_DFLL48M 7
#define GCLK_SOURCE_FDPLL 8
#define GCLK_SOURCE_GCLKGEN1 2
#define GCLK_SOURCE_GCLKIN 1
#define GCLK_SOURCE_BITS 4
#define GCLK_SOURCE_DFLL48M 7
#define GCLK_SOURCE_FDPLL 8
#define GCLK_SOURCE_GCLKGEN1 2
#define GCLK_SOURCE_GCLKIN 1
#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
#define GCLK_SOURCE_OSCULP32K 3
#define GCLK_SOURCE_OSC16M 6
#define GCLK_SOURCE_OSC32K 4
#define GCLK_SOURCE_XOSC 0
#define GCLK_SOURCE_XOSC32K 5
#define GCLK_SOURCE_OSCULP32K 3
#define GCLK_SOURCE_OSC16M 6
#define GCLK_SOURCE_OSC32K 4
#define GCLK_SOURCE_XOSC 0
#define GCLK_SOURCE_XOSC32K 5
#endif /* _SAMR30_GCLK_INSTANCE_ */

6
cpu/sam0_common/include/vendor/samr30/include/instance/mclk.h vendored
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@ -76,9 +76,9 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for MCLK peripheral ========== */
#define MCLK_CTRLA_MCSEL_GCLK 1
#define MCLK_CTRLA_MCSEL_OSC8M 0
#define MCLK_MCLK_CLK_APB_NUM 5
#define MCLK_CTRLA_MCSEL_GCLK 1
#define MCLK_CTRLA_MCSEL_OSC8M 0
#define MCLK_MCLK_CLK_APB_NUM 5
#define MCLK_SYSTEM_CLOCK 4000000 // System Clock Frequency at Reset
#endif /* _SAMR30_MCLK_INSTANCE_ */

18
cpu/sam0_common/include/vendor/samr30/include/instance/nvmctrl.h vendored
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@ -75,20 +75,20 @@
#define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register
#define NVMCTRL_CLK_AHB_ID_PICACHU 15 // Index of PICACHU AHB Clock
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF
#define NVMCTRL_FLASH_SIZE 262144
#define NVMCTRL_FLASH_SIZE 262144
#define NVMCTRL_GCLK_ID 35 // Index of Generic Clock for test
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
#define NVMCTRL_PAGE_HW 32
#define NVMCTRL_PAGE_SIZE 64
#define NVMCTRL_PAGE_W 16
#define NVMCTRL_PMSB 3
#define NVMCTRL_PSZ_BITS 6
#define NVMCTRL_ROW_PAGES 4
#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_PAGE_HW 32
#define NVMCTRL_PAGE_SIZE 64
#define NVMCTRL_PAGE_W 16
#define NVMCTRL_PMSB 3
#define NVMCTRL_PSZ_BITS 6
#define NVMCTRL_ROW_PAGES 4
#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF
#define NVMCTRL_RWWEE_PAGES 128
#define NVMCTRL_RWWEE_PAGES 128
#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area
#endif /* _SAMR30_NVMCTRL_INSTANCE_ */

2
cpu/sam0_common/include/vendor/samr30/include/instance/osc32kctrl.h vendored
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@ -66,6 +66,6 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6
#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6
#endif /* _SAMR30_OSC32KCTRL_INSTANCE_ */

12
cpu/sam0_common/include/vendor/samr30/include/instance/oscctrl.h vendored
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@ -82,14 +82,14 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for OSCCTRL peripheral ========== */
#define OSCCTRL_DFLL48M_COARSE_MSB 5
#define OSCCTRL_DFLL48M_FINE_MSB 9
#define OSCCTRL_DFLL48M_COARSE_MSB 5
#define OSCCTRL_DFLL48M_FINE_MSB 9
#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
#define OSCCTRL_DFLL48M_VERSION 0x320
#define OSCCTRL_FDPLL_VERSION 0x200
#define OSCCTRL_OSC16M_VERSION 0x100
#define OSCCTRL_XOSC_VERSION 0x120
#define OSCCTRL_DFLL48M_VERSION 0x320
#define OSCCTRL_FDPLL_VERSION 0x200
#define OSCCTRL_OSC16M_VERSION 0x100
#define OSCCTRL_XOSC_VERSION 0x120
#endif /* _SAMR30_OSCCTRL_INSTANCE_ */

4
cpu/sam0_common/include/vendor/samr30/include/instance/port.h vendored
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@ -134,14 +134,14 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PORT peripheral ========== */
#define PORT_BITS 84
#define PORT_BITS 84
#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
#define PORT_DRVSTR 1 // DRVSTR supported?
#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000D0000 }
#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC0C3FFFF, 0x00000000 }
#define PORT_EV_NUM 4
#define PORT_EV_NUM 4
#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
#define PORT_ODRAIN 0 // ODRAIN supported?

2
cpu/sam0_common/include/vendor/samr30/include/instance/rfctrl.h vendored
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@ -52,6 +52,6 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RFCTRL peripheral ========== */
#define RFCTRL_FBUSMSB 5
#define RFCTRL_FBUSMSB 5
#endif /* _SAMR30_RFCTRL_INSTANCE_ */

8
cpu/sam0_common/include/vendor/samr30/include/instance/sercom0.h vendored
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@ -136,9 +136,9 @@
/* ========== Instance parameters for SERCOM0 peripheral ========== */
#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
#define SERCOM0_GCLK_ID_CORE 18
#define SERCOM0_GCLK_ID_SLOW 17
#define SERCOM0_INT_MSB 6
#define SERCOM0_PMSB 3
#define SERCOM0_GCLK_ID_CORE 18
#define SERCOM0_GCLK_ID_SLOW 17
#define SERCOM0_INT_MSB 6
#define SERCOM0_PMSB 3
#endif /* _SAMR30_SERCOM0_INSTANCE_ */

8
cpu/sam0_common/include/vendor/samr30/include/instance/sercom1.h vendored
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@ -136,9 +136,9 @@
/* ========== Instance parameters for SERCOM1 peripheral ========== */
#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
#define SERCOM1_GCLK_ID_CORE 19
#define SERCOM1_GCLK_ID_SLOW 17
#define SERCOM1_INT_MSB 6
#define SERCOM1_PMSB 3
#define SERCOM1_GCLK_ID_CORE 19
#define SERCOM1_GCLK_ID_SLOW 17
#define SERCOM1_INT_MSB 6
#define SERCOM1_PMSB 3
#endif /* _SAMR30_SERCOM1_INSTANCE_ */

8
cpu/sam0_common/include/vendor/samr30/include/instance/sercom2.h vendored
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@ -136,9 +136,9 @@
/* ========== Instance parameters for SERCOM2 peripheral ========== */
#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
#define SERCOM2_GCLK_ID_CORE 20
#define SERCOM2_GCLK_ID_SLOW 17
#define SERCOM2_INT_MSB 6
#define SERCOM2_PMSB 3
#define SERCOM2_GCLK_ID_CORE 20
#define SERCOM2_GCLK_ID_SLOW 17
#define SERCOM2_INT_MSB 6
#define SERCOM2_PMSB 3
#endif /* _SAMR30_SERCOM2_INSTANCE_ */

8
cpu/sam0_common/include/vendor/samr30/include/instance/sercom3.h vendored
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@ -136,9 +136,9 @@
/* ========== Instance parameters for SERCOM3 peripheral ========== */
#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger
#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
#define SERCOM3_GCLK_ID_CORE 21
#define SERCOM3_GCLK_ID_SLOW 17
#define SERCOM3_INT_MSB 6
#define SERCOM3_PMSB 3
#define SERCOM3_GCLK_ID_CORE 21
#define SERCOM3_GCLK_ID_SLOW 17
#define SERCOM3_INT_MSB 6
#define SERCOM3_PMSB 3
#endif /* _SAMR30_SERCOM3_INSTANCE_ */

8
cpu/sam0_common/include/vendor/samr30/include/instance/sercom4.h vendored
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@ -136,9 +136,9 @@
/* ========== Instance parameters for SERCOM4 peripheral ========== */
#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger
#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
#define SERCOM4_GCLK_ID_CORE 22
#define SERCOM4_GCLK_ID_SLOW 17
#define SERCOM4_INT_MSB 6
#define SERCOM4_PMSB 3
#define SERCOM4_GCLK_ID_CORE 22
#define SERCOM4_GCLK_ID_SLOW 17
#define SERCOM4_INT_MSB 6
#define SERCOM4_PMSB 3
#endif /* _SAMR30_SERCOM4_INSTANCE_ */

8
cpu/sam0_common/include/vendor/samr30/include/instance/sercom5.h vendored
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@ -136,9 +136,9 @@
/* ========== Instance parameters for SERCOM5 peripheral ========== */
#define SERCOM5_DMAC_ID_RX // Index of DMA RX trigger
#define SERCOM5_DMAC_ID_TX // Index of DMA TX trigger
#define SERCOM5_GCLK_ID_CORE 24
#define SERCOM5_GCLK_ID_SLOW 23
#define SERCOM5_INT_MSB 3
#define SERCOM5_PMSB 3
#define SERCOM5_GCLK_ID_CORE 24
#define SERCOM5_GCLK_ID_SLOW 23
#define SERCOM5_INT_MSB 3
#define SERCOM5_PMSB 3
#endif /* _SAMR30_SERCOM5_INSTANCE_ */

4
cpu/sam0_common/include/vendor/samr30/include/instance/supc.h vendored
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@ -72,8 +72,8 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SUPC peripheral ========== */
#define SUPC_BOD12_CALIB_MSB 5
#define SUPC_BOD33_CALIB_MSB 5
#define SUPC_BOD12_CALIB_MSB 5
#define SUPC_BOD33_CALIB_MSB 5
#define SUPC_SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number
#endif /* _SAMR30_SUPC_INSTANCE_ */

10
cpu/sam0_common/include/vendor/samr30/include/instance/tc0.h vendored
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@ -108,16 +108,16 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC0 peripheral ========== */
#define TC0_CC_NUM 2
#define TC0_CC_NUM 2
#define TC0_DMAC_ID_MC_0 23
#define TC0_DMAC_ID_MC_1 24
#define TC0_DMAC_ID_MC_LSB 23
#define TC0_DMAC_ID_MC_MSB 24
#define TC0_DMAC_ID_MC_SIZE 2
#define TC0_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger
#define TC0_EXT 0
#define TC0_GCLK_ID 27
#define TC0_MASTER 1
#define TC0_OW_NUM 2
#define TC0_EXT 0
#define TC0_GCLK_ID 27
#define TC0_MASTER 1
#define TC0_OW_NUM 2
#endif /* _SAMR30_TC0_INSTANCE_ */

10
cpu/sam0_common/include/vendor/samr30/include/instance/tc1.h vendored
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@ -108,16 +108,16 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC1 peripheral ========== */
#define TC1_CC_NUM 2
#define TC1_CC_NUM 2
#define TC1_DMAC_ID_MC_0 26
#define TC1_DMAC_ID_MC_1 27
#define TC1_DMAC_ID_MC_LSB 26
#define TC1_DMAC_ID_MC_MSB 27
#define TC1_DMAC_ID_MC_SIZE 2
#define TC1_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger
#define TC1_EXT 0
#define TC1_GCLK_ID 27
#define TC1_MASTER 0
#define TC1_OW_NUM 2
#define TC1_EXT 0
#define TC1_GCLK_ID 27
#define TC1_MASTER 0
#define TC1_OW_NUM 2
#endif /* _SAMR30_TC1_INSTANCE_ */

10
cpu/sam0_common/include/vendor/samr30/include/instance/tc4.h vendored
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@ -108,16 +108,16 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC4 peripheral ========== */
#define TC4_CC_NUM 2
#define TC4_CC_NUM 2
#define TC4_DMAC_ID_MC_0 35
#define TC4_DMAC_ID_MC_1 36
#define TC4_DMAC_ID_MC_LSB 35
#define TC4_DMAC_ID_MC_MSB 36
#define TC4_DMAC_ID_MC_SIZE 2
#define TC4_DMAC_ID_OVF 34 // Indexes of DMA Overflow trigger
#define TC4_EXT 0
#define TC4_GCLK_ID 29
#define TC4_MASTER 0
#define TC4_OW_NUM 2
#define TC4_EXT 0
#define TC4_GCLK_ID 29
#define TC4_MASTER 0
#define TC4_OW_NUM 2
#endif /* _SAMR30_TC4_INSTANCE_ */

2
cpu/sam0_common/include/vendor/samr30/include/instance/tcc0.h vendored
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@ -122,7 +122,7 @@
#define TCC0_OTMX 1 // Output Matrix feature implemented
#define TCC0_OW_NUM 8 // Number of Output Waveforms
#define TCC0_PG 1 // Pattern Generation feature implemented
#define TCC0_SIZE 24
#define TCC0_SIZE 24
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave

2
cpu/sam0_common/include/vendor/samr30/include/instance/tcc1.h vendored
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@ -110,7 +110,7 @@
#define TCC1_OTMX 0 // Output Matrix feature implemented
#define TCC1_OW_NUM 4 // Number of Output Waveforms
#define TCC1_PG 1 // Pattern Generation feature implemented
#define TCC1_SIZE 24
#define TCC1_SIZE 24
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave

2
cpu/sam0_common/include/vendor/samr30/include/instance/tcc2.h vendored
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@ -106,7 +106,7 @@
#define TCC2_OTMX 0 // Output Matrix feature implemented
#define TCC2_OW_NUM 2 // Number of Output Waveforms
#define TCC2_PG 0 // Pattern Generation feature implemented
#define TCC2_SIZE 16
#define TCC2_SIZE 16
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave

5
cpu/sam0_common/include/vendor/samr30/include/samr30e18a.h vendored
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@ -3,7 +3,7 @@
*
* \brief Header file for SAMR30E18A
*
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
@ -217,6 +217,7 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

5
cpu/sam0_common/include/vendor/samr30/include/samr30g18a.h vendored
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@ -3,7 +3,7 @@
*
* \brief Header file for SAMR30G18A
*
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
@ -217,6 +217,7 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */