Merge pull request #7583 from haukepetersen/add_sam3_rtt

cpu/sam3: added RTT driver

boards/common/arduino-due/Makefile.features

@@ -6,6 +6,7 @@ FEATURES_PROVIDED += periph_adc
 FEATURES_PROVIDED += periph_dac
 FEATURES_PROVIDED += periph_gpio periph_gpio_irq
 FEATURES_PROVIDED += periph_pwm
+FEATURES_PROVIDED += periph_rtt
 FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart

boards/common/arduino-due/include/periph_conf.h

@@ -47,6 +47,16 @@ extern "C" {
 #define CLOCK_FWS           (4)         /* 4 is save for 84MHz */
 /** @} */
 
+/**
+ * @name    Enable external oscillator for driving the slow clock
+ *
+ * @warning Many (older?) arduino-due boards do not have the external 32khz
+ *          oscillator soldered on, so only enable this after you make sure its
+ *          equipped on your specific board */
+#ifndef CLOCK_SCLK_XTAL
+#define CLOCK_SCLK_XTAL     (0)
+#endif
+
 /**
  * @name    Timer peripheral configuration
  * @{
@@ -62,6 +72,13 @@ static const timer_conf_t timer_config[] = {
 #define TIMER_NUMOF         ARRAY_SIZE(timer_config)
 /** @} */
 
+/**
+ * @name    RTT configuration
+ * @{
+ */
+#define RTT_FREQUENCY       (1U)        /* 1Hz */
+/** @} */
+
 /**
  * @name    UART configuration
  * @{

cpu/sam3/cpu.c

@@ -30,6 +30,11 @@
 #define MORKEY              (0x37)
 /** @} */
 
+/**
+ * @brief   Key for writing the SUPC control register
+ */
+#define SUPCKEY             (0xa5)
+
 /**
  * @brief   Start-up time for external crystal (will be multiplied by 8)
  */
@@ -91,6 +96,13 @@ void cpu_init(void)
     /* wait for master clock to be ready */
     while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
 
+    /* setup the SCLK: switch to external oscillator if applicable */
+#if CLOCK_SCLK_XTAL
+    /* enable external oscillator */
+    SUPC->SUPC_CR = (SUPC_CR_KEY(SUPCKEY) | SUPC_CR_XTALSEL);
+    while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST)) {}
+#endif
+
     /* initialize stdio prior to periph_init() to allow use of DEBUG() there */
     stdio_init();
 

cpu/sam3/include/periph_cpu.h

@@ -70,6 +70,11 @@ typedef uint32_t gpio_t;
  */
 #define TIMER_CHANNELS      (3)
 
+/**
+ * @brief   The RTT width is fixed to 32-bit
+ */
+#define RTT_MAX_VALUE       (0xffffffff)
+
 /**
  * @brief   Generate GPIO mode bitfields
  *

cpu/sam3/periph/rtt.c

@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2017,2020 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_sam3
+ * @ingroup     drivers_periph_rtt
+ *
+ * @note        The hardware RTT unit does neither support overflow interrupts
+ *              nor setting the counter value. For this, this RTT driver does
+ *              not implement those functions.
+ * @{
+ *
+ * @file
+ * @brief       Low-level RTT driver implementation
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include "cpu.h"
+#include "periph/rtt.h"
+
+#define ENABLE_DEBUG        (0)
+#include "debug.h"
+
+static struct {
+    rtt_cb_t cb;
+    void *arg;
+} isr_ctx;
+
+void rtt_init(void)
+{
+    /* enable RTT module */
+    rtt_poweron();
+
+    /* configure and apply the pre-scaler */
+    RTT->RTT_MR = RTT_MR_RTPRES(CHIP_FREQ_XTAL_32K / RTT_FREQUENCY);
+    RTT->RTT_MR |= RTT_MR_RTTRST;
+
+    /* resetting the timer takes two slow clock cycles, so we wait for this to
+     * complete */
+    while (RTT->RTT_VR != 0) {}
+
+    /* configure NVIC line */
+    NVIC_EnableIRQ(RTT_IRQn);
+}
+
+uint32_t rtt_get_counter(void)
+{
+    return RTT->RTT_VR;
+}
+
+void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
+{
+    /* cancel any existing alarm */
+    RTT->RTT_MR &= ~(RTT_MR_ALMIEN);
+
+    /* set new alarm */
+    isr_ctx.cb  = cb;
+    isr_ctx.arg = arg;
+    /* the alarm value is RTT_AR + 1, so we need to subtract 1 from the target
+     * value here */
+    RTT->RTT_AR = (alarm - 1);
+
+    /* (re-)enable the alarm */
+    RTT->RTT_MR |= RTT_MR_ALMIEN;
+}
+
+uint32_t rtt_get_alarm(void)
+{
+    if (RTT->RTT_MR & RTT_MR_ALMIEN) {
+        return RTT->RTT_AR;
+    }
+    return 0;
+}
+
+void rtt_clear_alarm(void)
+{
+    RTT->RTT_MR &= ~(RTT_MR_ALMIEN);
+}
+
+void rtt_poweron(void)
+{
+    PMC->PMC_PCER0 |= (1 << ID_RTT);
+}
+
+void rtt_poweroff(void)
+{
+    PMC->PMC_PCER0 &= ~(1 << ID_RTT);
+}
+
+void isr_rtt(void)
+{
+    uint32_t state = RTT->RTT_SR;       /* this clears all pending flags */
+    if (state & RTT_SR_ALMS) {
+        RTT->RTT_MR &= ~(RTT_MR_ALMIEN);
+        isr_ctx.cb(isr_ctx.arg);
+    }
+
+    cortexm_isr_end();
+}