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Merge pull request #13409 from aabadie/pr/cpu/nrf_gpio_t

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cpu/nrf5x: provide gpio_t type definition
This commit is contained in:
benpicco 2020-02-21 18:55:46 +01:00 committed by GitHub
commit 8d77ec55ae
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11 changed files with 39 additions and 31 deletions
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4
boards/feather-nrf52840/include/periph_conf.h
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@ -39,8 +39,8 @@ static const uart_conf_t uart_config[] = {
.dev = NRF_UARTE0,
.rx_pin = GPIO_PIN(0,24),
.tx_pin = GPIO_PIN(0,25),
.rts_pin = (uint8_t)GPIO_UNDEF,
.cts_pin = (uint8_t)GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_pin = GPIO_UNDEF,
.irqn = UARTE0_UART0_IRQn,
},
};

4
boards/nrf52840-mdk/include/periph_conf.h
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@ -40,8 +40,8 @@ static const uart_conf_t uart_config[] = {
.dev = NRF_UARTE0,
.rx_pin = GPIO_PIN(0,19),
.tx_pin = GPIO_PIN(0,20),
.rts_pin = (uint8_t)GPIO_UNDEF,
.cts_pin = (uint8_t)GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_pin = GPIO_UNDEF,
.irqn = UARTE0_UART0_IRQn,
},
};

8
boards/nrf52840dk/include/periph_conf.h
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@ -50,16 +50,16 @@ static const uart_conf_t uart_config[] = {
.dev = NRF_UARTE0,
.rx_pin = GPIO_PIN(0,8),
.tx_pin = GPIO_PIN(0,6),
.rts_pin = (uint8_t)GPIO_UNDEF,
.cts_pin = (uint8_t)GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_pin = GPIO_UNDEF,
.irqn = UARTE0_UART0_IRQn,
},
{ /* Mapped to Arduino D0/D1 pins */
.dev = NRF_UARTE1,
.rx_pin = GPIO_PIN(1,1),
.tx_pin = GPIO_PIN(1,2),
.rts_pin = (uint8_t)GPIO_UNDEF,
.cts_pin = (uint8_t)GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_pin = GPIO_UNDEF,
.irqn = UARTE1_IRQn,
},
};

4
boards/particle-argon/include/periph_conf.h
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@ -36,8 +36,8 @@ static const uart_conf_t uart_config[] = {
.dev = NRF_UARTE0,
.rx_pin = GPIO_PIN(0,8),
.tx_pin = GPIO_PIN(0,6),
.rts_pin = (uint8_t)GPIO_UNDEF,
.cts_pin = (uint8_t)GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_pin = GPIO_UNDEF,
.irqn = UARTE0_UART0_IRQn,
},
{

4
boards/particle-boron/include/periph_conf.h
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@ -36,8 +36,8 @@ static const uart_conf_t uart_config[] = {
.dev = NRF_UARTE0,
.rx_pin = GPIO_PIN(0,8),
.tx_pin = GPIO_PIN(0,6),
.rts_pin = (uint8_t)GPIO_UNDEF,
.cts_pin = (uint8_t)GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_pin = GPIO_UNDEF,
.irqn = UARTE0_UART0_IRQn,
},
{

4
boards/particle-xenon/include/periph_conf.h
View File

@ -36,8 +36,8 @@ static const uart_conf_t uart_config[] = {
.dev = NRF_UARTE0,
.rx_pin = GPIO_PIN(0,8),
.tx_pin = GPIO_PIN(0,6),
.rts_pin = (uint8_t)GPIO_UNDEF,
.cts_pin = (uint8_t)GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_pin = GPIO_UNDEF,
.irqn = UARTE0_UART0_IRQn,
},
};

4
boards/reel/include/periph_conf.h
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@ -39,8 +39,8 @@ static const uart_conf_t uart_config[] = {
.dev = NRF_UARTE0,
.rx_pin = GPIO_PIN(0,8),
.tx_pin = GPIO_PIN(0,6),
.rts_pin = (uint8_t)GPIO_UNDEF,
.cts_pin = (uint8_t)GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_pin = GPIO_UNDEF,
.irqn = UARTE0_UART0_IRQn,
},
};

4
cpu/nrf51/include/periph_cpu.h
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@ -88,8 +88,8 @@ typedef enum {
*/
typedef struct {
NRF_TWI_Type *dev; /**< hardware device */
uint8_t pin_scl; /**< SCL pin */
uint8_t pin_sda; /**< SDA pin */
gpio_t pin_scl; /**< SCL pin */
gpio_t pin_sda; /**< SDA pin */
uint8_t ppi; /**< PPI channel to use */
i2c_speed_t speed; /**< bus speed */
} i2c_conf_t;

14
cpu/nrf52/include/periph_cpu.h
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@ -105,8 +105,8 @@ typedef enum {
*/
typedef struct {
NRF_TWIM_Type *dev; /**< TWIM hardware device */
uint8_t scl; /**< SCL pin */
uint8_t sda; /**< SDA pin */
gpio_t scl; /**< SCL pin */
gpio_t sda; /**< SDA pin */
i2c_speed_t speed; /**< Bus speed */
} i2c_conf_t;
/** @} */
@ -158,7 +158,7 @@ typedef enum {
*/
typedef struct {
NRF_PWM_Type *dev; /**< PWM device descriptor */
uint32_t pin[PWM_CHANNELS]; /**< PWM out pins */
gpio_t pin[PWM_CHANNELS]; /**< PWM out pins */
} pwm_conf_t;
#ifdef CPU_MODEL_NRF52840XXAA
@ -167,10 +167,10 @@ typedef struct {
*/
typedef struct {
NRF_UARTE_Type *dev; /**< UART with EasyDMA device base register address */
uint8_t rx_pin; /**< RX pin */
uint8_t tx_pin; /**< TX pin */
uint8_t rts_pin; /**< RTS pin - set to GPIO_UNDEF when not using HW flow control */
uint8_t cts_pin; /**< CTS pin - set to GPIO_UNDEF when not using HW flow control */
gpio_t rx_pin; /**< RX pin */
gpio_t tx_pin; /**< TX pin */
gpio_t rts_pin; /**< RTS pin - set to GPIO_UNDEF when not using HW flow control */
gpio_t cts_pin; /**< CTS pin - set to GPIO_UNDEF when not using HW flow control */
uint8_t irqn; /**< IRQ channel */
} uart_conf_t;
#endif

16
cpu/nrf5x_common/include/periph_cpu_common.h
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@ -55,7 +55,7 @@ extern "C" {
/**
* @brief Override GPIO_UNDEF value
*/
#define GPIO_UNDEF (UINT_MAX)
#define GPIO_UNDEF (UINT8_MAX)
/**
* @brief Generate GPIO mode bitfields
@ -84,6 +84,14 @@ extern "C" {
/** @} */
#ifndef DOXYGEN
/**
* @brief Overwrite the default gpio_t type definition
* @{
*/
#define HAVE_GPIO_T
typedef uint8_t gpio_t;
/** @} */
/**
* @brief Override GPIO modes
*
@ -162,9 +170,9 @@ typedef enum {
*/
typedef struct {
NRF_SPI_Type *dev; /**< SPI device used */
uint8_t sclk; /**< CLK pin */
uint8_t mosi; /**< MOSI pin */
uint8_t miso; /**< MISO pin */
gpio_t sclk; /**< CLK pin */
gpio_t mosi; /**< MOSI pin */
gpio_t miso; /**< MISO pin */
} spi_conf_t;
/**

4
cpu/nrf5x_common/periph/uart.c
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@ -44,8 +44,8 @@
#define UART_PIN_TX uart_config[uart].tx_pin
#define UART_PIN_RTS uart_config[uart].rts_pin
#define UART_PIN_CTS uart_config[uart].cts_pin
#define UART_HWFLOWCTRL (uart_config[uart].rts_pin != (uint8_t)GPIO_UNDEF && \
uart_config[uart].cts_pin != (uint8_t)GPIO_UNDEF)
#define UART_HWFLOWCTRL (uart_config[uart].rts_pin != GPIO_UNDEF && \
uart_config[uart].cts_pin != GPIO_UNDEF)
#define ISR_CTX isr_ctx[uart]
#define RAM_MASK (0x20000000)