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cpu: do not locally export compilation variables

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These are already exported by `makefiles/vars.inc.mk`.
It is a prerequisite to allow handling compilation without global exports.
This commit is contained in:
Gaëtan Harter 2019-08-27 16:06:41 +02:00
parent ef542ef92c
commit 1be5b7b10b
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GPG Key ID: 76DF6BCF1B1F883B
14 changed files with 29 additions and 36 deletions
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2
cpu/atmega32u4/Makefile.include
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@ -1,5 +1,5 @@
# this CPU implementation is using the new core/CPU interface
export CFLAGS += -DCOREIF_NG=1
CFLAGS += -DCOREIF_NG=1
# tell the build system that the CPU depends on the atmega common files
USEMODULE += atmega_common

6
cpu/atmega_common/Makefile.include
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@ -1,7 +1,7 @@
# include module specific includes
export INCLUDES += -I$(RIOTCPU)/atmega_common/include \
-isystem$(RIOTCPU)/atmega_common/avr_libc_extra/include \
-isystem$(RIOTCPU)/atmega_common/avr_libc_extra/include/vendor
INCLUDES += -I$(RIOTCPU)/atmega_common/include \
-isystem$(RIOTCPU)/atmega_common/avr_libc_extra/include \
-isystem$(RIOTCPU)/atmega_common/avr_libc_extra/include/vendor
# avr libc needs some RIOT-specific support code
USEMODULE += avr_libc_extra

2
cpu/efm32/Makefile.features
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@ -12,7 +12,7 @@ ifeq (1,$(EFM32_TNRG))
endif
ifeq (1,$(EFM32_UART_MODES))
export CFLAGS += -DEFM32_UART_MODES=1
CFLAGS += -DEFM32_UART_MODES=1
endif
include $(RIOTCPU)/cortexm_common/Makefile.features

2
cpu/efm32/Makefile.include
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@ -4,7 +4,7 @@ export CPU_ARCH = $(EFM32_ARCHITECTURE)
export CPU_FAM = $(EFM32_FAMILY)
# the em_device.h header requires a global define with the cpu model
export CFLAGS += -D$(shell echo $(CPU_MODEL) | tr 'a-z' 'A-Z')
CFLAGS += -D$(shell echo $(CPU_MODEL) | tr 'a-z' 'A-Z')
# include Gecko SDK package
USEPKG += gecko_sdk

2
cpu/mips32r2_common/Makefile.include
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@ -1,4 +1,4 @@
export INCLUDES += -I$(RIOTCPU)/mips32r2_common/include
INCLUDES += -I$(RIOTCPU)/mips32r2_common/include
export USEMODULE += mips32r2_common
export USEMODULE += mips32r2_common_periph

2
cpu/mips_pic32_common/Makefile.include
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@ -1,6 +1,6 @@
include $(RIOTCPU)/mips32r2_common/Makefile.include
export INCLUDES += -I$(RIOTCPU)/mips_pic32_common/include
INCLUDES += -I$(RIOTCPU)/mips_pic32_common/include
USEMODULE += mips_pic32_common
USEMODULE += mips_pic32_common_periph

6
cpu/mips_pic32mx/Makefile.include
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@ -4,14 +4,14 @@ include $(RIOTCPU)/mips_pic32_common/Makefile.include
include $(RIOTMAKE)/arch/mips.inc.mk
# define build specific options
export CFLAGS += -march=m4k -DSKIP_COPY_TO_RAM
CFLAGS += -march=m4k -DSKIP_COPY_TO_RAM
export LINKFLAGS += -Wl,--defsym,__use_excpt_boot=0 $(CFLAGS)
export LINKFLAGS += -Tpic32mx512_12_128_uhi.ld
# the pickit programmer (MPLAB-IPE) wants physical addresses in the hex file!!
export OBJCOPY = objcopy #use system objcopy as toolchain one is broken.
export OFLAGS += \
OBJCOPY = objcopy #use system objcopy as toolchain one is broken.
OFLAGS += \
--change-section-lma .bootflash-0xA0000000 \
--change-section-lma .exception_vector-0x80000000 \
--change-section-lma .text-0x80000000 \

8
cpu/mips_pic32mz/Makefile.include
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@ -4,15 +4,15 @@ include $(RIOTCPU)/mips_pic32_common/Makefile.include
include $(RIOTMAKE)/arch/mips.inc.mk
# define build specific options
export CFLAGS += -march=m5101 -mmicromips -DSKIP_COPY_TO_RAM
export CFLAGS += -DMIPS_MICROMIPS
CFLAGS += -march=m5101 -mmicromips -DSKIP_COPY_TO_RAM
CFLAGS += -DMIPS_MICROMIPS
export LINKFLAGS += -Wl,--defsym,__use_excpt_boot=0 $(CFLAGS)
export LINKFLAGS += -Tpic32mz2048_uhi.ld
# the pickit programmer (MPLAB-IPE) wants physical addresses in the hex file!!
export OBJCOPY = objcopy #use system objcopy as toolchain one is broken.
export OFLAGS += \
OBJCOPY = objcopy #use system objcopy as toolchain one is broken.
OFLAGS += \
--change-section-lma .lowerbootflashalias-0xA0000000 \
--change-section-lma .bootflash1-0xA0000000 \
--change-section-lma .bootflash2-0xA0000000 \

3
cpu/msp430_common/Makefile.include
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@ -2,9 +2,8 @@ PSEUDOMODULES += msp430_malloc
INCLUDES += -I$(RIOTCPU)/msp430_common/include/
# export the CPU model
MODEL = $(shell echo $(CPU_MODEL) | tr 'a-z' 'A-Z')
export CFLAGS += -DCPU_MODEL_$(MODEL)
CFLAGS += -DCPU_MODEL_$(MODEL)
export UNDEF += $(BINDIR)/msp430_common/startup.o
export USEMODULE += msp430_common msp430_common_periph msp430_malloc

6
cpu/nrf5x_common/Makefile.include
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@ -1,6 +1,5 @@
# export the CPU family so we can differentiate between them in the code
FAM = $(shell echo $(CPU_FAM) | tr 'a-z-' 'A-Z_')
export CFLAGS += -DCPU_FAM_$(FAM)
CFLAGS += -DCPU_FAM_$(FAM)
# include nrf5x common periph drivers
USEMODULE += nrf5x_common_periph
@ -8,5 +7,4 @@ USEMODULE += nrf5x_common_periph
# link common cpu code
USEMODULE += cpu_common
# export the common include directory
export INCLUDES += -I$(RIOTCPU)/nrf5x_common/include
INCLUDES += -I$(RIOTCPU)/nrf5x_common/include

9
cpu/sam0_common/Makefile.include
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@ -19,9 +19,9 @@ ROM_START_ADDR ?= 0x00000000
RAM_START_ADDR ?= 0x20000000
# this CPU implementation doesn't use CMSIS initialization
export CFLAGS += -DDONT_USE_CMSIS_INIT
export CFLAGS += -DDONT_USE_PREDEFINED_CORE_HANDLERS
export CFLAGS += -DDONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
CFLAGS += -DDONT_USE_CMSIS_INIT
CFLAGS += -DDONT_USE_PREDEFINED_CORE_HANDLERS
CFLAGS += -DDONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
# For Cortex-M cpu we use the common cortexm.ld linker script
LINKER_SCRIPT ?= cortexm.ld
@ -29,5 +29,4 @@ LINKER_SCRIPT ?= cortexm.ld
# include sam0 common periph drivers
USEMODULE += sam0_common_periph
# export the common include directory
export INCLUDES += -I$(RIOTCPU)/sam0_common/include
INCLUDES += -I$(RIOTCPU)/sam0_common/include

5
cpu/sam_common/Makefile.include
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@ -2,10 +2,9 @@
CFLAGS += -DCPU_FAM_$(shell echo $(CPU_FAM) | tr 'a-z-' 'A-Z_')
# this CPU implementation doesn't use CMSIS initialization
export CFLAGS += -DDONT_USE_CMSIS_INIT
CFLAGS += -DDONT_USE_CMSIS_INIT
# for the sam[drl] CPUs we hold all linkerscripts in the sam0 common folder
export LINKFLAGS += -L$(RIOTCPU)/sam_common/ldscripts
# export the common include directory
export INCLUDES += -I$(RIOTCPU)/sam_common/include
INCLUDES += -I$(RIOTCPU)/sam_common/include

2
cpu/stellaris_common/Makefile.include
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@ -1,4 +1,4 @@
# define stellaris specific flags and includes
export STELLARISWARE = $(RIOTCPU)/stellaris_common/include/vendor
# define build specific options
export CFLAGS += -I$(STELLARISWARE) -DPART_$(CPU_MODEL) -c -DTARGET_IS_BLIZZARD_RA1
CFLAGS += -I$(STELLARISWARE) -DPART_$(CPU_MODEL) -c -DTARGET_IS_BLIZZARD_RA1

10
cpu/stm32_common/Makefile.include
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@ -1,6 +1,5 @@
# export the CPU family so we can differentiate between them in the code
FAM = $(shell echo $(CPU_FAM) | tr 'a-z-' 'A-Z_')
export CFLAGS += -DCPU_FAM_$(FAM)
CFLAGS += -DCPU_FAM_$(FAM)
# All stm32 families provide pm support
USEMODULE += pm_layered
@ -12,8 +11,7 @@ USEMODULE += stm32_common stm32_common_periph
export LINKFLAGS += -L$(RIOTCPU)/stm32_common/ldscripts
LINKER_SCRIPT ?= stm32_common.ld
# export the common include directory
export INCLUDES += -I$(RIOTCPU)/stm32_common/include
INCLUDES += -I$(RIOTCPU)/stm32_common/include
# Compute ROM_LEN and RAM_LEN
include $(RIOTCPU)/stm32_common/stm32_mem_lengths.mk
@ -26,8 +24,8 @@ FLASHSIZE := $(shell echo $$(( $(LEN) * $(KB) )) )
CPU_LINE ?= $(shell echo $(CPU_MODEL) | cut -c -9 | tr 'a-z-' 'A-Z_')xx
# Set CFLAGS
export CFLAGS += -D$(CPU_LINE) -DCPU_LINE_$(CPU_LINE)
export CFLAGS += -DSTM32_FLASHSIZE=$(FLASHSIZE)U
CFLAGS += -D$(CPU_LINE) -DCPU_LINE_$(CPU_LINE)
CFLAGS += -DSTM32_FLASHSIZE=$(FLASHSIZE)U
info-stm32:
@$(COLOR_ECHO) "CPU: $(CPU_MODEL)"