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cpu/*: add cortex_mpu to known-to-support CPU families
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@ -4,6 +4,8 @@ FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += periph_uart_modecfg
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += puf_sram
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-include $(RIOTCPU)/cortexm_common/Makefile.features
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@ -1,3 +1,5 @@
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CPU_ARCH = cortex-m3
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FEATURES_PROVIDED += cortexm_mpu
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-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features
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@ -1,3 +1,5 @@
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CPU_ARCH = cortex-m4f
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FEATURES_PROVIDED += cortexm_mpu
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-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features
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@ -5,7 +5,3 @@ FEATURES_PROVIDED += periph_pm
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FEATURES_PROVIDED += cpp
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FEATURES_PROVIDED += cpu_check_address
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FEATURES_PROVIDED += ssp
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ifneq ($(CPU_ARCH),cortex-m0)
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FEATURES_PROVIDED += cortexm_mpu
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endif
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@ -4,6 +4,7 @@ include $(RIOTCPU)/efm32/efm32-features.mk
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CPU_ARCH = $(EFM32_ARCHITECTURE)
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FEATURES_PROVIDED += arch_efm32
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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@ -1,5 +1,6 @@
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CPU_ARCH = cortex-m4f
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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@ -1,3 +1,5 @@
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CPU_ARCH = cortex-m4f
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FEATURES_PROVIDED += cortexm_mpu
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-include $(RIOTCPU)/cortexm_common/Makefile.features
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@ -2,6 +2,7 @@ CPU_ARCH = cortex-m3
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# This CPU only implements one CPU_MODEL with the same name
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CPU_MODEL = lpc1768
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_pm
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@ -8,4 +8,7 @@ FEATURES_PROVIDED += periph_adc
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# feature to mark this
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FEATURES_PROVIDED += ble_nimble_netif
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# all nrf52 have an MPU
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FEATURES_PROVIDED += cortexm_mpu
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-include $(RIOTCPU)/nrf5x_common/Makefile.features
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@ -1,6 +1,7 @@
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CPU_ARCH = cortex-m3
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CPU_FAM = sam3
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_hwrng
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@ -3,5 +3,6 @@ CPU_FAM = samd5x
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FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += backup_ram
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FEATURES_PROVIDED += cortexm_mpu
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include $(RIOTCPU)/sam0_common/Makefile.features
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@ -1,6 +1,7 @@
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CPU_ARCH = cortex-m23
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CPU_FAM = saml1x
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_hwrng
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include $(RIOTCPU)/sam0_common/Makefile.features
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@ -2,5 +2,6 @@ CPU_ARCH = cortex-m3
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CPU_FAM = stm32f2
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FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += cortexm_mpu
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-include $(RIOTCPU)/stm32_common/Makefile.features
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@ -4,4 +4,10 @@ CPU_FAM = stm32f3
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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# only some stm32f3 have an MPU
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STM32F3_WITH_MPU += stm32f303re stm32f303vc stm32f303ze
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ifneq (, $(filter $(CPU_MODEL), $(STM32F3_WITH_MPU)))
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FEATURES_PROVIDED += cortexm_mpu
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endif
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-include $(RIOTCPU)/stm32_common/Makefile.features
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@ -1,6 +1,7 @@
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CPU_ARCH = cortex-m4f
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CPU_FAM = stm32f4
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_hwrng
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# the granularity of provided feature definition for STMs is currently by CPU
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@ -1,5 +1,6 @@
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CPU_ARCH = cortex-m7
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CPU_FAM = stm32f7
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_hwrng
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-include $(RIOTCPU)/stm32_common/Makefile.features
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@ -8,4 +8,10 @@ FEATURES_PROVIDED += periph_hwrng
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BOARDS_WITHOUT_HWRNG += nucleo-l031k6
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# only some stm32l0 have an MPU
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STM32L0_WITH_MPU += stm32l052t8
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ifneq (, $(filter $(CPU_MODEL), $(STM32L0_WITH_MPU)))
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FEATURES_PROVIDED += cortexm_mpu
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endif
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-include $(RIOTCPU)/stm32_common/Makefile.features
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@ -1,6 +1,7 @@
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CPU_ARCH = cortex-m3
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CPU_FAM = stm32l1
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_eeprom
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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@ -1,6 +1,7 @@
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CPU_ARCH = cortex-m4f
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CPU_FAM = stm32l4
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FEATURES_PROVIDED += cortexm_mpu
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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FEATURES_PROVIDED += periph_hwrng
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