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cpu/*: add cortex_mpu to known-to-support CPU families

This commit is contained in:
Kaspar Schleiser 2020-03-02 15:01:22 +01:00
parent cbca43bf6c
commit a3c527fdbc
19 changed files with 34 additions and 4 deletions

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@ -4,6 +4,8 @@ FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_uart_modecfg
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += puf_sram
-include $(RIOTCPU)/cortexm_common/Makefile.features

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@ -1,3 +1,5 @@
CPU_ARCH = cortex-m3
FEATURES_PROVIDED += cortexm_mpu
-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features

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@ -1,3 +1,5 @@
CPU_ARCH = cortex-m4f
FEATURES_PROVIDED += cortexm_mpu
-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features

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@ -5,7 +5,3 @@ FEATURES_PROVIDED += periph_pm
FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += cpu_check_address
FEATURES_PROVIDED += ssp
ifneq ($(CPU_ARCH),cortex-m0)
FEATURES_PROVIDED += cortexm_mpu
endif

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@ -4,6 +4,7 @@ include $(RIOTCPU)/efm32/efm32-features.mk
CPU_ARCH = $(EFM32_ARCHITECTURE)
FEATURES_PROVIDED += arch_efm32
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw

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@ -1,5 +1,6 @@
CPU_ARCH = cortex-m4f
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio periph_gpio_irq

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@ -1,3 +1,5 @@
CPU_ARCH = cortex-m4f
FEATURES_PROVIDED += cortexm_mpu
-include $(RIOTCPU)/cortexm_common/Makefile.features

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@ -2,6 +2,7 @@ CPU_ARCH = cortex-m3
# This CPU only implements one CPU_MODEL with the same name
CPU_MODEL = lpc1768
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_pm

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@ -8,4 +8,7 @@ FEATURES_PROVIDED += periph_adc
# feature to mark this
FEATURES_PROVIDED += ble_nimble_netif
# all nrf52 have an MPU
FEATURES_PROVIDED += cortexm_mpu
-include $(RIOTCPU)/nrf5x_common/Makefile.features

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@ -1,6 +1,7 @@
CPU_ARCH = cortex-m3
CPU_FAM = sam3
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_hwrng

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@ -3,5 +3,6 @@ CPU_FAM = samd5x
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += backup_ram
FEATURES_PROVIDED += cortexm_mpu
include $(RIOTCPU)/sam0_common/Makefile.features

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@ -1,6 +1,7 @@
CPU_ARCH = cortex-m23
CPU_FAM = saml1x
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += periph_hwrng
include $(RIOTCPU)/sam0_common/Makefile.features

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@ -2,5 +2,6 @@ CPU_ARCH = cortex-m3
CPU_FAM = stm32f2
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += cortexm_mpu
-include $(RIOTCPU)/stm32_common/Makefile.features

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@ -4,4 +4,10 @@ CPU_FAM = stm32f3
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw
# only some stm32f3 have an MPU
STM32F3_WITH_MPU += stm32f303re stm32f303vc stm32f303ze
ifneq (, $(filter $(CPU_MODEL), $(STM32F3_WITH_MPU)))
FEATURES_PROVIDED += cortexm_mpu
endif
-include $(RIOTCPU)/stm32_common/Makefile.features

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@ -1,6 +1,7 @@
CPU_ARCH = cortex-m4f
CPU_FAM = stm32f4
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += periph_hwrng
# the granularity of provided feature definition for STMs is currently by CPU

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@ -1,5 +1,6 @@
CPU_ARCH = cortex-m7
CPU_FAM = stm32f7
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += periph_hwrng
-include $(RIOTCPU)/stm32_common/Makefile.features

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@ -8,4 +8,10 @@ FEATURES_PROVIDED += periph_hwrng
BOARDS_WITHOUT_HWRNG += nucleo-l031k6
# only some stm32l0 have an MPU
STM32L0_WITH_MPU += stm32l052t8
ifneq (, $(filter $(CPU_MODEL), $(STM32L0_WITH_MPU)))
FEATURES_PROVIDED += cortexm_mpu
endif
-include $(RIOTCPU)/stm32_common/Makefile.features

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@ -1,6 +1,7 @@
CPU_ARCH = cortex-m3
CPU_FAM = stm32l1
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += periph_eeprom
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw

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@ -1,6 +1,7 @@
CPU_ARCH = cortex-m4f
CPU_FAM = stm32l4
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw
FEATURES_PROVIDED += periph_hwrng