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cpu/sam0_common: distribute PM_NUM_MODES among siblings
Also adapt the defines to the documentation - CPUs define up to 4 power modes (from zero, the lowest power mode, to PM_NUM_MODES-1, the highest) - >> there is an implicit extra idle mode (which has the number PM_NUM_MODES) << Previously on saml21 this would always generate pm_set(3) which is an illegal state. Now pm_layered will correctly generate pm_set(2) for IDLE modes. Idle power consumption dropped from 750µA to 368µA and wake-up from standby is also possible. (Before it would just enter STANDBY again as the mode register was never written with the illegal value.)
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@ -96,17 +96,6 @@ enum {
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*/
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#define GPIO_MODE(pr, ie, pe) (pr | (ie << 1) | (pe << 2))
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/**
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* @name Power mode configuration
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* @{
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*/
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#ifdef CPU_SAML1X
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#define PM_NUM_MODES (2)
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#else
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#define PM_NUM_MODES (3)
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#endif
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/** @} */
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#ifndef DOXYGEN
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/**
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* @brief Override GPIO modes
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@ -28,6 +28,13 @@
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extern "C" {
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#endif
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/**
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* @name Power mode configuration
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* @{
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*/
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#define PM_NUM_MODES (3)
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/** @} */
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/**
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* @brief Override the default initial PM blocker
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* @todo Idle modes are enabled by default, deep sleep mode blocked
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@ -43,6 +43,13 @@ extern "C" {
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*/
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#define SAM0_DPLL_FREQ_MAX_HZ (200000000U)
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/**
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* @name Power mode configuration
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* @{
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*/
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#define PM_NUM_MODES (3)
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/** @} */
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/**
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* @name SAMD5x GCLK definitions
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* @{
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@ -26,6 +26,13 @@
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extern "C" {
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#endif
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/**
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* @name Power mode configuration
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* @{
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*/
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#define PM_NUM_MODES (1)
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/** @} */
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/**
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* @brief Override the default initial PM blocker
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* @todo Idle modes are enabled by default, deep sleep mode blocked
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@ -31,6 +31,13 @@ extern "C" {
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*/
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#define CPU_BACKUP_RAM_NOT_RETAINED (1)
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/**
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* @name Power mode configuration
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* @{
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*/
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#define PM_NUM_MODES (2)
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/** @} */
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/**
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* @name SAML21 GCLK definitions
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* @{
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