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cpu/sam0: use defines for GCLK IDs

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Give the clocks explicit names to better identify their meaning.
This commit is contained in:
Benjamin Valentin 2019-12-16 19:41:16 +01:00 committed by Benjamin Valentin
parent df33ffd0d3
commit 38b6ee56f3
11 changed files with 101 additions and 51 deletions
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2
cpu/sam0_common/periph/rtc.c
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@ -66,7 +66,7 @@ static inline void _rtc_set_enabled(bool on)
static void _rtc_clock_setup(void)
{
/* Use 1024 Hz GCLK3 */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(3) | GCLK_CLKCTRL_ID_RTC;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(SAM0_GCLK_1KHZ) | GCLK_CLKCTRL_ID_RTC;
while (GCLK->STATUS.bit.SYNCBUSY) {}
}
#else

2
cpu/sam0_common/periph/rtt.c
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@ -65,7 +65,7 @@ static inline void _rtt_reset(void)
static void _rtt_clock_setup(void)
{
/* Setup clock GCLK2 with OSC32K */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(2) | GCLK_CLKCTRL_ID_RTC;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(SAM0_GCLK_32KHZ) | GCLK_CLKCTRL_ID_RTC;
while (GCLK->STATUS.bit.SYNCBUSY) {}
}
#else

4
cpu/sam0_common/periph/wdt.c
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@ -83,9 +83,9 @@ static uint32_t ms_to_per(uint32_t ms)
#ifdef CPU_SAMD21
static void _wdt_clock_setup(void)
{
/* Connect to GCLK4 (~1.024 kHz) */
/* Connect to GCLK3 (~1.024 kHz) */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_WDT
| GCLK_CLKCTRL_GEN_GCLK4
| GCLK_CLKCTRL_GEN(SAM0_GCLK_1KHZ)
| GCLK_CLKCTRL_CLKEN;
}
#else

50
cpu/samd21/cpu.c
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@ -58,15 +58,13 @@ void sam0_gclk_enable(uint8_t id)
uint32_t sam0_gclk_freq(uint8_t id)
{
switch (id) {
case 0:
case SAM0_GCLK_MAIN:
return CLOCK_CORECLOCK;
case 1:
case SAM0_GCLK_1MHZ:
return 1000000;
case 2:
case SAM0_GCLK_32KHZ:
return 32768;
case 3:
return 32768;
case 4:
case SAM0_GCLK_1KHZ:
return 1024;
default:
return 0;
@ -97,8 +95,8 @@ static void clk_init(void)
#endif
/* Setup GCLK2 with divider 1 (32.768kHz) */
GCLK->GENDIV.reg = (GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(0));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_GENEN
GCLK->GENDIV.reg = (GCLK_GENDIV_ID(SAM0_GCLK_32KHZ) | GCLK_GENDIV_DIV(0));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(SAM0_GCLK_32KHZ) | GCLK_GENCTRL_GENEN
| GCLK_GENCTRL_RUNSTDBY
#if GEN2_ULP32K
| GCLK_GENCTRL_SRC_OSCULP32K);
@ -119,12 +117,12 @@ static void clk_init(void)
/* setup generic clock 1 to feed DPLL with 1MHz */
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(8) |
GCLK_GENDIV_ID(1));
GCLK_GENDIV_ID(SAM0_GCLK_1MHZ));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
GCLK_GENCTRL_SRC_OSC8M |
GCLK_GENCTRL_ID(1));
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN(1) |
GCLK_CLKCTRL_ID(1) |
GCLK_GENCTRL_ID(SAM0_GCLK_1MHZ));
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN(SAM0_GCLK_1MHZ) |
GCLK_CLKCTRL_ID_FDPLL |
GCLK_CLKCTRL_CLKEN);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
@ -137,10 +135,10 @@ static void clk_init(void)
/* select the PLL as source for clock generator 0 (CPU core clock) */
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(CLOCK_PLL_DIV) |
GCLK_GENDIV_ID(0));
GCLK_GENDIV_ID(SAM0_GCLK_MAIN));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
GCLK_GENCTRL_SRC_FDPLL |
GCLK_GENCTRL_ID(0));
GCLK_GENCTRL_ID(SAM0_GCLK_MAIN));
#elif CLOCK_USE_XOSC32_DFLL
/* Use External 32.768KHz Oscillator */
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND |
@ -158,14 +156,14 @@ static void clk_init(void)
/* setup generic clock 1 as 1MHz for timer.c */
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(8) |
GCLK_GENDIV_ID(1));
GCLK_GENDIV_ID(SAM0_GCLK_1MHZ));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
GCLK_GENCTRL_SRC_OSC8M |
GCLK_GENCTRL_ID(1));
GCLK_GENCTRL_ID(SAM0_GCLK_1MHZ));
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
/* set GCLK2 as source for DFLL */
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN_GCLK2 |
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN(SAM0_GCLK_32KHZ) |
GCLK_CLKCTRL_ID_DFLL48 |
GCLK_CLKCTRL_CLKEN);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
@ -197,9 +195,13 @@ static void clk_init(void)
while ((SYSCTRL->PCLKSR.reg & mask) != mask) { } /* Wait for DFLL lock */
/* select the DFLL as source for clock generator 0 (CPU core clock) */
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(1U) | GCLK_GENDIV_ID(0));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(0));
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0;
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(1U) | GCLK_GENDIV_ID(SAM0_GCLK_MAIN));
GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN
| GCLK_GENCTRL_SRC_DFLL48M
| GCLK_GENCTRL_ID(SAM0_GCLK_MAIN);
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_ID_DFLL48
| GCLK_CLKCTRL_GEN(SAM0_GCLK_MAIN);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
@ -208,18 +210,18 @@ static void clk_init(void)
}
#else /* do not use PLL, use internal 8MHz oscillator directly */
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(CLOCK_DIV) |
GCLK_GENDIV_ID(0));
GCLK_GENDIV_ID(SAM0_GCLK_MAIN));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
GCLK_GENCTRL_SRC_OSC8M |
GCLK_GENCTRL_ID(0));
GCLK_GENCTRL_ID(SAM0_GCLK_MAIN));
#endif
/* make sure we synchronize clock generator 0 before we go on */
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
/* Setup GCLK3 with divider 32 (1024 Hz) */
GCLK->GENDIV.reg = (GCLK_GENDIV_ID(3) | GCLK_GENDIV_DIV(4));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(3) | GCLK_GENCTRL_GENEN
GCLK->GENDIV.reg = (GCLK_GENDIV_ID(SAM0_GCLK_1KHZ) | GCLK_GENDIV_DIV(4));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(SAM0_GCLK_1KHZ) | GCLK_GENCTRL_GENEN
| GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_DIVSEL
#if GEN2_ULP32K
| GCLK_GENCTRL_SRC_OSCULP32K);

12
cpu/samd21/include/periph_cpu.h
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@ -44,6 +44,18 @@ extern "C" {
#define SAMD21_PM_IDLE_0 (3U) /**< Idle 0 (stops CPU) */
/** @} */
/**
* @name SAMD21 GCLK definitions
* @{
*/
enum {
SAM0_GCLK_MAIN = 0, /**< 48 MHz main clock */
SAM0_GCLK_1MHZ, /**< 1 MHz clock for xTimer */
SAM0_GCLK_32KHZ, /**< 32 kHz clock */
SAM0_GCLK_1KHZ, /**< 1 kHz clock */
};
/** @} */
/**
* @brief Mapping of pins to EXTI lines, -1 means not EXTI possible
*/

30
cpu/samd5x/cpu.c
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@ -110,16 +110,20 @@ void sam0_gclk_enable(uint8_t id)
/* clocks 0 & 1 are always running */
switch (id) {
case 5:
case SAM0_GCLK_8MHZ:
/* 8 MHz clock used by xtimer */
#if USE_DPLL
gclk_connect(5, GCLK_SOURCE_DPLL0, GCLK_GENCTRL_DIV(DPLL_DIV * CLOCK_CORECLOCK / 8000000));
gclk_connect(SAM0_GCLK_8MHZ,
GCLK_SOURCE_DPLL0,
GCLK_GENCTRL_DIV(DPLL_DIV * CLOCK_CORECLOCK / 8000000));
#else
gclk_connect(5, GCLK_SOURCE_DFLL, GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / 8000000));
gclk_connect(SAM0_GCLK_8MHZ,
GCLK_SOURCE_DFLL,
GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / 8000000));
#endif
break;
case 6:
gclk_connect(6, GCLK_SOURCE_DFLL, 0);
case SAM0_GCLK_48MHZ:
gclk_connect(SAM0_GCLK_48MHZ, GCLK_SOURCE_DFLL, 0);
break;
}
}
@ -127,13 +131,13 @@ void sam0_gclk_enable(uint8_t id)
uint32_t sam0_gclk_freq(uint8_t id)
{
switch (id) {
case 0:
case SAM0_GCLK_MAIN:
return CLOCK_CORECLOCK;
case 1:
case SAM0_GCLK_32KHZ:
return 32768;
case 5:
case SAM0_GCLK_8MHZ:
return 8000000;
case 6:
case SAM0_GCLK_48MHZ:
return SAM0_DFLL_FREQ_HZ;
default:
return 0;
@ -179,19 +183,19 @@ void cpu_init(void)
CMCC->CTRL.bit.CEN = 1;
xosc32k_init();
gclk_connect(1, GCLK_SOURCE_XOSC32K, 0);
gclk_connect(SAM0_GCLK_32KHZ, GCLK_SOURCE_XOSC32K, 0);
/* make sure main clock is not sourced from DPLL */
dfll_init();
gclk_connect(0, GCLK_SOURCE_DFLL, 0);
gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DFLL, 0);
#if USE_DPLL
fdpll0_init(CLOCK_CORECLOCK * DPLL_DIV);
/* source main clock from DPLL */
gclk_connect(0, GCLK_SOURCE_DPLL0, GCLK_GENCTRL_DIV(DPLL_DIV));
gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DPLL0, GCLK_GENCTRL_DIV(DPLL_DIV));
#else
gclk_connect(0, GCLK_SOURCE_DFLL, GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / CLOCK_CORECLOCK));
gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DFLL, GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / CLOCK_CORECLOCK));
#endif
/* initialize stdio prior to periph_init() to allow use of DEBUG() there */

12
cpu/samd5x/include/periph_cpu.h
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@ -43,6 +43,18 @@ extern "C" {
*/
#define SAM0_DPLL_FREQ_MAX_HZ (200000000U)
/**
* @name SAMD5x GCLK definitions
* @{
*/
enum {
SAM0_GCLK_MAIN = 0, /**< 120 MHz main clock */
SAM0_GCLK_32KHZ, /**< 32 kHz clock */
SAM0_GCLK_8MHZ, /**< 8 MHz clock for xTimer */
SAM0_GCLK_48MHZ, /**< 48 MHz DFLL clock */
};
/** @} */
/**
* @brief Mapping of pins to EXTI lines, -1 means not EXTI possible
*/

10
cpu/saml1x/cpu.c
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@ -80,9 +80,9 @@ void sam0_gclk_enable(uint8_t id)
uint32_t sam0_gclk_freq(uint8_t id)
{
switch (id) {
case 0:
case SAM0_GCLK_MAIN:
return CLOCK_CORECLOCK;
case 1:
case SAM0_GCLK_32KHZ:
return 32768;
default:
return 0;
@ -132,11 +132,11 @@ void cpu_init(void)
_xosc32k_setup();
/* Setup GCLK generators */
_gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
_gclk_setup(SAM0_GCLK_MAIN, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
#if EXTERNAL_OSC32_SOURCE
_gclk_setup(1, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K);
_gclk_setup(SAM0_GCLK_32KHZ, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K);
#else
_gclk_setup(1, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K);
_gclk_setup(SAM0_GCLK_32KHZ, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K);
#endif
/* initialize stdio prior to periph_init() to allow use of DEBUG() there */

10
cpu/saml1x/include/periph_cpu.h
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@ -32,6 +32,16 @@ extern "C" {
*/
#define PM_BLOCKER_INITIAL { .val_u32 = 0x00000001 }
/**
* @name SAML1x GCLK definitions
* @{
*/
enum {
SAM0_GCLK_MAIN = 0, /**< 16 MHz main clock */
SAM0_GCLK_32KHZ, /**< 32 kHz clock */
};
/** @} */
/**
* @brief Mapping of pins to EXTI lines, -1 means not EXTI possible
*/

10
cpu/saml21/cpu.c
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@ -73,9 +73,9 @@ void sam0_gclk_enable(uint8_t id)
uint32_t sam0_gclk_freq(uint8_t id)
{
switch (id) {
case 0:
case SAM0_GCLK_MAIN:
return CLOCK_CORECLOCK;
case 1:
case SAM0_GCLK_32KHZ:
return 32768;
default:
return 0;
@ -126,11 +126,11 @@ void cpu_init(void)
_xosc32k_setup();
/* Setup GCLK generators */
_gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
_gclk_setup(SAM0_GCLK_MAIN, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
#if EXTERNAL_OSC32_SOURCE
_gclk_setup(1, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K);
_gclk_setup(SAM0_GCLK_32KHZ, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K);
#else
_gclk_setup(1, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K);
_gclk_setup(SAM0_GCLK_32KHZ, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K);
#endif
#ifdef MODULE_PERIPH_PM

10
cpu/saml21/include/periph_cpu.h
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@ -31,6 +31,16 @@ extern "C" {
*/
#define CPU_BACKUP_RAM_NOT_RETAINED (1)
/**
* @name SAML21 GCLK definitions
* @{
*/
enum {
SAM0_GCLK_MAIN = 0, /**< 16 MHz main clock */
SAM0_GCLK_32KHZ, /**< 32 kHz clock */
};
/** @} */
/**
* @brief Mapping of pins to EXTI lines, -1 means not EXTI possible
*/