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cpu/esp*: common irq_arch in cpu/esp_common
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@ -21,21 +21,12 @@
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#ifndef IRQ_ARCH_H
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#define IRQ_ARCH_H
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#include "irq.h"
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#include "sched.h"
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#include "thread.h"
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#include "irq_arch_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Indicates the interrupt nesting depth
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*
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* The variable is increment on entry into and decremented on exit from an ISR.
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*/
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extern volatile uint32_t irq_interrupt_nesting;
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/**
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* @name CPU interrupt numbers
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*
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@ -56,37 +47,6 @@ extern volatile uint32_t irq_interrupt_nesting;
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#define CPU_INUM_TIMER 19 /**< Level interrupt with medium priority 2 */
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/** @} */
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/**
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* @name Macros to enter and exit an ISR
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*
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* Since all the stuff is done in `_frxt_int_enter` and `_frxt_int_exit`, these
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* macros are doing nothing and are kept only for source code compatibility.
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*
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* @{
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*/
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#define irq_isr_enter()
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#define irq_isr_exit()
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/** @} */
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/**
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* @name Macros to enter and exit a critical region
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*
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* @note: since they use a local variable they can be used only in same function
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*
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* @{
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*/
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#define critical_enter() int _irq_state = irq_disable()
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#define critical_exit() irq_restore(_irq_state)
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/** @} */
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/**
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* @name Macros to enter and exit a critical region with state variable
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* @{
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*/
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#define critical_enter_var(m) m = irq_disable()
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#define critical_exit_var(m) irq_restore(m)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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@ -21,89 +21,13 @@
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#define ENABLE_DEBUG 0
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#include "debug.h"
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#include <stdint.h>
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#include <stdio.h>
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#include "irq.h"
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#include "irq_arch.h"
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#include "cpu.h"
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#include "esp_common.h"
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#include "esp_err.h"
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#include "esp/common_macros.h"
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#include "esp/xtensa_ops.h"
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#include "rom/ets_sys.h"
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#include "soc/dport_reg.h"
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#include "xtensa/xtensa_context.h"
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#include "xtensa/xtensa_api.h"
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extern unsigned _xtos_set_intlevel(unsigned intlevel);
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/**
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* @brief Set on entry into and reset on exit from an ISR
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*/
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volatile uint32_t irq_interrupt_nesting = 0;
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/**
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* @brief Disable all maskable interrupts
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*/
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unsigned int IRAM irq_disable(void)
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{
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uint32_t _saved_intlevel;
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/* read and set interrupt level with one asm instruction (RSIL) */
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__asm__ volatile ("rsil %0, " XTSTR(XCHAL_NUM_INTLEVELS+1) : "=a" (_saved_intlevel));
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/* mask out everything else of the PS register that do not belong to
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interrupt level (bits 3..0) */
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_saved_intlevel &= 0xf;
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DEBUG ("%s new %08x (old %08x)\n", __func__,
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XCHAL_NUM_INTLEVELS + 1, _saved_intlevel);
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return _saved_intlevel;
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}
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/**
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* @brief Enable all maskable interrupts
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*/
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unsigned int IRAM irq_enable(void)
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{
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uint32_t _saved_intlevel;
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/* read and set interrupt level with one asm instruction (RSIL) */
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__asm__ volatile ("rsil %0, 0" : "=a" (_saved_intlevel));
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/* mask out everything else of the PS register that do not belong to
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interrupt level (bits 3..0) */
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_saved_intlevel &= 0xf;
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DEBUG ("%s new %08x (old %08x)\n", __func__, 0, _saved_intlevel);
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return _saved_intlevel;
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}
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/**
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* @brief Restore the state of the IRQ flags
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*/
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void IRAM irq_restore(unsigned int state)
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{
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/* restore the interrupt level using a rom function, performance is not
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important here */
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#if 0
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__asm__ volatile ("wsr %0, ps; rsync" :: "a" (state));
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DEBUG ("%s %02x\n", __func__, state);
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#else
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unsigned _saved_intlevel = _xtos_set_intlevel(state);
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DEBUG ("%s new %08x (old %08x)\n", __func__, state, _saved_intlevel);
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#endif
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}
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/**
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* @brief See if the current context is inside an ISR
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*/
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int IRAM irq_is_in(void)
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{
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DEBUG("irq_interrupt_nesting = %d\n", irq_interrupt_nesting);
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return irq_interrupt_nesting;
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}
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struct _irq_alloc_table_t {
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int src; /* peripheral interrupt source */
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uint32_t intr; /* interrupt number */
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@ -21,52 +21,12 @@
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#ifndef IRQ_ARCH_H
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#define IRQ_ARCH_H
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#include "irq.h"
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#include "sched.h"
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#include "thread.h"
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#include "irq_arch_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Indicates the interrupt nesting depth
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*
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* The variable is increment on entry into and decremented on exit from an ISR.
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*/
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extern uint32_t irq_interrupt_nesting;
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/**
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* @name Macros to enter and exit an ISR
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*
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* Since all the stuff is done in `_frxt_int_enter` and `_frxt_int_exit`, these
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* macros are doing nothing and are kept only for source code compatibility.
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*
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* @{
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*/
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#define irq_isr_enter()
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#define irq_isr_exit()
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/** @} */
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/**
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* @name Macros to enter and exit a critical region
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*
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* @note since they use a local variable they can be used only in same function
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*
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* @{
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*/
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#define critical_enter() int _irq_state = irq_disable()
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#define critical_exit() irq_restore(_irq_state)
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/** @} */
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/**
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* @name Macros to enter and exit a critical region with state variable
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* @{
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*/
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#define critical_enter_var(m) m = irq_disable()
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#define critical_exit_var(m) irq_restore(m)
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/** @} */
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/**
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* @name Software interrupt types
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*
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74
cpu/esp_common/include/irq_arch_common.h
Normal file
74
cpu/esp_common/include/irq_arch_common.h
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@ -0,0 +1,74 @@
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/*
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* Copyright (C) 2019 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_esp_common
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* @{
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*
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* @file
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* @brief Implementation of the kernels irq interface
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*
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* @}
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*/
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#ifndef IRQ_ARCH_COMMON_H
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#define IRQ_ARCH_COMMON_H
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#include "irq.h"
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#include "sched.h"
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#include "thread.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Indicates the interrupt nesting depth
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*
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* The variable is incremented on entry into and decremented on exit from an ISR.
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*/
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extern volatile uint32_t irq_interrupt_nesting;
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/**
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* @name Macros to enter and exit an ISR
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*
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* Since all the stuff is done in `_frxt_int_enter` and `_frxt_int_exit`, these
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* macros are doing nothing and are kept only for source code compatibility.
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*
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* @{
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*/
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#define irq_isr_enter()
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#define irq_isr_exit()
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/** @} */
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/**
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* @name Macros to enter and exit a critical region
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*
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* @note: since they use a local variable they can be used only in same function
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*
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* @{
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*/
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#define critical_enter() int _irq_state = irq_disable()
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#define critical_exit() irq_restore(_irq_state)
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/** @} */
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/**
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* @name Macros to enter and exit a critical region with state variable
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* @{
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*/
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#define critical_enter_var(m) m = irq_disable()
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#define critical_exit_var(m) irq_restore(m)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* IRQ_ARCH_COMMON_H */
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*/
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/**
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* @ingroup cpu_esp8266
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* @ingroup cpu_esp_common
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* @{
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*
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* @file
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@ -42,14 +42,16 @@ volatile uint32_t irq_interrupt_nesting = 0;
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*/
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unsigned int IRAM irq_disable(void)
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{
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uint32_t _saved_interrupt_level;
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uint32_t state;
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/* read and set interrupt level (RSIL) */
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__asm__ volatile ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) : "=a" (_saved_interrupt_level));
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DEBUG ("%s %02x(%02x)\n", __func__,
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(_saved_interrupt_level & 0xfffffff0) | (XCHAL_EXCM_LEVEL),
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_saved_interrupt_level);
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return _saved_interrupt_level;
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__asm__ volatile ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) : "=a" (state) :: "memory");
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/* mask out everything else of the PS register that do not belong to
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interrupt level (bits 3..0) */
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state &= 0xf;
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DEBUG("%s %02x(%02x)\n", __func__, XCHAL_EXCM_LEVEL, state);
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return state;
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}
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/**
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@ -57,13 +59,16 @@ unsigned int IRAM irq_disable(void)
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*/
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unsigned int IRAM irq_enable(void)
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{
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uint32_t _saved_interrupt_level;
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uint32_t state;
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/* read and set interrupt level (RSIL) */
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__asm__ volatile ("rsil %0, 0" : "=a" (_saved_interrupt_level));
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DEBUG ("%s %02x (%02x)\n", __func__,
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_saved_interrupt_level & 0xfffffff0, _saved_interrupt_level);
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return _saved_interrupt_level;
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__asm__ volatile ("rsil %0, 0" : "=a" (state) :: "memory");
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/* mask out everything else of the PS register that do not belong to
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interrupt level (bits 3..0) */
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state &= 0xf;
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DEBUG("%s %02x(%02x)\n", __func__, 0, state);
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return state;
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}
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/**
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@ -71,9 +76,19 @@ unsigned int IRAM irq_enable(void)
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*/
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void IRAM irq_restore(unsigned int state)
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{
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uint32_t old = 0;
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/* write interrupt level and sync */
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DEBUG ("%s %02x\n", __func__, state);
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__asm__ volatile ("wsr %0, ps; rsync" :: "a" (state));
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__asm__ volatile ("extui %1, %1, 0, 4 \n" /* mask intlevel bits in param */
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"rsr.ps %0 \n" /* read current PS value */
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"movi.n a4, -16 \n"
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"and a4, a4, %0 \n" /* mask out intlevel bits in PS */
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"or a4, a4, %1 \n" /* or intlevel with PS */
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"wsr.ps a4 \n" /* write back PS */
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"rsync \n"
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: "+a" (old) : "a" (state) : "memory");
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DEBUG("%s %02x(%02x)\n", __func__, state, old & 0xf);
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}
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/**
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