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Merge pull request #12035 from gschorcht/cpu/esp32/fix_periph_flash
cpu/esp32: fix and improve periph/flash
This commit is contained in:
benpicco
GitHub
commit
52bf448a3b
@ -20,16 +20,12 @@
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#if MODULE_MTD
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#include <errno.h>
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#include <string.h>
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#include <stdlib.h>
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#include "esp_common.h"
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#include "irq_arch.h"
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#include "log.h"
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#include "mtd.h"
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#include "rom/cache.h"
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@ -38,6 +34,9 @@
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#include "esp_partition.h"
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#include "esp_spi_flash.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#define ESP_PART_TABLE_ADDR 0x8000 /* TODO configurable as used in Makefile.include */
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#define ESP_PART_TABLE_SIZE 0xC00
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#define ESP_PART_ENTRY_SIZE 0x20
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@ -169,9 +168,6 @@ esp_err_t IRAM_ATTR spi_flash_read(size_t addr, void *buff, size_t size)
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/* size must be within the flash address space */
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CHECK_PARAM_RET (addr + size <= _flash_end, -EOVERFLOW);
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/* prepare for write access */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
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int result = ESP_ROM_SPIFLASH_RESULT_OK;
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uint32_t len = size;
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@ -182,9 +178,17 @@ esp_err_t IRAM_ATTR spi_flash_read(size_t addr, void *buff, size_t size)
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uint32_t len_in_word = 4 - pos_in_word;
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len_in_word = (len_in_word < len) ? len_in_word : len;
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/* disable interrupts and the cache */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
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result = esp_rom_spiflash_read (word_addr, (uint32_t*)_flash_buf, 4);
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memcpy(buff, _flash_buf + pos_in_word, len_in_word);
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/* enable interrupts and the cache */
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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buff = (uint8_t*)buff + len_in_word;
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addr += len_in_word;
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len -= len_in_word;
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@ -198,9 +202,17 @@ esp_err_t IRAM_ATTR spi_flash_read(size_t addr, void *buff, size_t size)
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len_full_words = ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM;
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}
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/* disable interrupts and the cache */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
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result |= esp_rom_spiflash_read (addr, (uint32_t*)_flash_buf, len_full_words);
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memcpy(buff, _flash_buf, len_full_words);
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/* enable interrupts and the cache */
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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buff = (uint8_t*)buff + len_full_words;
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addr += len_full_words;
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len -= len_full_words;
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@ -208,13 +220,17 @@ esp_err_t IRAM_ATTR spi_flash_read(size_t addr, void *buff, size_t size)
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/* if there is some remaining, we need to prepare last word */
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if (len && result == ESP_ROM_SPIFLASH_RESULT_OK) {
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/* disable interrupts and the cache */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
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result |= esp_rom_spiflash_read (addr, (uint32_t*)_flash_buf, 4);
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memcpy(buff, _flash_buf, len);
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}
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/* reset read access */
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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/* enable interrupts and the cache */
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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}
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/* return with the ESP-IDF error code that is mapped from ROM error code */
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RETURN_WITH_ESP_ERR_CODE(result);
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@ -230,8 +246,6 @@ esp_err_t IRAM_ATTR spi_flash_write(size_t addr, const void *buff, size_t size)
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CHECK_PARAM_RET (addr + size <= _flash_end, -EOVERFLOW);
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/* prepare for write access */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
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int result = esp_rom_spiflash_unlock();
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uint32_t len = size;
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@ -242,10 +256,18 @@ esp_err_t IRAM_ATTR spi_flash_write(size_t addr, const void *buff, size_t size)
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uint32_t len_in_word = 4 - pos_in_word;
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len_in_word = (len_in_word < len) ? len_in_word : len;
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/* disable interrupts and the cache */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
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result |= esp_rom_spiflash_read (word_addr, (uint32_t*)_flash_buf, 4);
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memcpy(_flash_buf + pos_in_word, buff, len_in_word);
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result |= esp_rom_spiflash_write (word_addr, (uint32_t*)_flash_buf, 4);
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/* enable interrupts and the cache */
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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buff = (uint8_t*)buff + len_in_word;
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addr += len_in_word;
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len -= len_in_word;
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@ -259,9 +281,17 @@ esp_err_t IRAM_ATTR spi_flash_write(size_t addr, const void *buff, size_t size)
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len_full_words = ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM;
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}
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/* disable interrupts and the cache */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
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memcpy(_flash_buf, buff, len_full_words);
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result |= esp_rom_spiflash_write (addr, (uint32_t*)_flash_buf, len_full_words);
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/* enable interrupts and the cache */
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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buff = (uint8_t*)buff + len_full_words;
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addr += len_full_words;
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len -= len_full_words;
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@ -269,15 +299,21 @@ esp_err_t IRAM_ATTR spi_flash_write(size_t addr, const void *buff, size_t size)
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/* if there is some remaining, we need to prepare last word */
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if (len && result == ESP_ROM_SPIFLASH_RESULT_OK) {
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/* disable interrupts and the cache */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
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result |= esp_rom_spiflash_read (addr, (uint32_t*)_flash_buf, 4);
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memcpy(_flash_buf, buff, len);
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result |= esp_rom_spiflash_write (addr, (uint32_t*)_flash_buf, 4);
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/* enable interrupts and the cache */
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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}
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/* reset write access */
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esp_rom_spiflash_lock();
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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/* return with the ESP-IDF error code that is mapped from ROM error code */
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RETURN_WITH_ESP_ERR_CODE(result);
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@ -298,21 +334,36 @@ esp_err_t IRAM_ATTR spi_flash_erase_range(size_t addr, size_t size)
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CHECK_PARAM_RET (size % _flashchip->sector_size == 0, -ENOTSUP)
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/* prepare for write access */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
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uint32_t result = esp_rom_spiflash_unlock();
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/* erase as many sectors as necessary */
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uint32_t sec = addr / _flashchip->sector_size;
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uint32_t cnt = size / _flashchip->sector_size;
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while (cnt-- && result == ESP_ROM_SPIFLASH_RESULT_OK) {
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result = esp_rom_spiflash_erase_sector (sec++);
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uint32_t sec_per_block = _flashchip->block_size / _flashchip->sector_size;
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while (cnt && result == ESP_ROM_SPIFLASH_RESULT_OK) {
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/* disable interrupts and the cache */
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critical_enter();
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Cache_Read_Disable(PRO_CPU_NUM);
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/* erase block-wise (64 kByte) if cnt is at least sec_per_block */
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if (cnt >= sec_per_block) {
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result = esp_rom_spiflash_erase_block (sec / sec_per_block);
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sec += sec_per_block;
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cnt -= sec_per_block;
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}
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else {
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result = esp_rom_spiflash_erase_sector (sec++);
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cnt--;
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}
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/* enable interrupts and the cache */
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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}
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/* reset write access */
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esp_rom_spiflash_lock();
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Cache_Read_Enable(PRO_CPU_NUM);
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critical_exit();
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/* return with the ESP-IDF error code that is mapped from ROM error code */
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RETURN_WITH_ESP_ERR_CODE(result);
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@ -406,7 +457,11 @@ static int _flash_write (mtd_dev_t *dev, const void *buff, uint32_t addr, uint32
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/* size must be within the flash address space */
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CHECK_PARAM_RET (_flash_beg + addr + size <= _flash_end, -EOVERFLOW);
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return (spi_flash_write(_flash_beg + addr, buff, size) == ESP_OK) ?(int)size : -EIO;
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/* addr + size must be within a page */
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CHECK_PARAM_RET (size <= _flashchip->page_size, -EOVERFLOW);
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CHECK_PARAM_RET ((addr % _flashchip->page_size) + size <= _flashchip->page_size, -EOVERFLOW);
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return (spi_flash_write(_flash_beg + addr, buff, size) == ESP_OK) ? (int)size : -EIO;
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}
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static int _flash_erase (mtd_dev_t *dev, uint32_t addr, uint32_t size)
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@ -419,8 +474,8 @@ static int _flash_erase (mtd_dev_t *dev, uint32_t addr, uint32_t size)
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CHECK_PARAM_RET (_flash_beg + addr + size <= _flash_end, -EOVERFLOW);
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/* size must be a multiple of sector_size && at least one sector */
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CHECK_PARAM_RET (size >= _flashchip->sector_size, -ENOTSUP);
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CHECK_PARAM_RET (size % _flashchip->sector_size == 0, -ENOTSUP)
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CHECK_PARAM_RET (size >= _flashchip->sector_size, -EOVERFLOW);
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CHECK_PARAM_RET (size % _flashchip->sector_size == 0, -EOVERFLOW)
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return (spi_flash_erase_range(_flash_beg + addr, size) == ESP_OK) ? 0 : -EIO;
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}
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