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cc26xx_cc13xx: fix UART1 initialization

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Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
This commit is contained in:
Jean Pierre Dudey 2020-04-07 09:54:39 -05:00
parent 5fe7831152
commit d4084d6df9
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GPG Key ID: 631A70D74E41F1AD
3 changed files with 68 additions and 30 deletions
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2
cpu/cc26x2_cc13x2/include/cc26x2_cc13x2_prcm.h
View File

@ -258,7 +258,7 @@ typedef struct {
#define GPIOCLKGR_CLK_EN 0x1
#define I2CCLKGR_CLK_EN 0x1
#define UARTCLKGR_CLK_EN_UART0 0x1
#define UARTCLKGR_CLK_EN_UART1 0x1
#define UARTCLKGR_CLK_EN_UART1 0x2
/** @} */
/** @ingroup cpu_specific_peripheral_memory_map

53
cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_uart.h
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@ -24,31 +24,28 @@
extern "C" {
#endif
#define UART0_BASE (0x40001000) /**< UART0 base address */
#define UART1_BASE (0x40008000) /**< UART1 base address */
/**
* @brief UART component registers
* @brief UART component registers
*/
typedef struct {
reg32_t DR; /**< data */
reg32_t DR; /**< Data */
union {
reg32_t RSR; /**< status */
reg32_t ECR; /**< error clear */
reg32_t RSR; /**< Status */
reg32_t ECR; /**< Error clear */
};
reg32_t __reserved1[4]; /**< meh */
reg32_t __reserved1[4]; /**< Reserved */
reg32_t FR; /**< flag */
reg32_t __reserved2[2]; /**< meh */
reg32_t IBRD; /**< integer baud-rate divisor */
reg32_t FBRD; /**< fractional baud-rate divisor */
reg32_t LCRH; /**< line control */
reg32_t CTL; /**< control */
reg32_t IFLS; /**< interrupt fifo level select */
reg32_t IMSC; /**< interrupt mask set/clear */
reg32_t RIS; /**< raw interrupt status */
reg32_t MIS; /**< masked interrupt status */
reg32_t ICR; /**< interrupt clear */
reg32_t DMACTL; /**< DMA control */
reg32_t __reserved2[2]; /**< Reserved */
reg32_t IBRD; /**< Integer baud-rate divisor */
reg32_t FBRD; /**< Fractional baud-rate divisor */
reg32_t LCRH; /**< Line control */
reg32_t CTL; /**< Control */
reg32_t IFLS; /**< Interrupt fifo level select */
reg32_t IMSC; /**< Interrupt mask set/clear */
reg32_t RIS; /**< Raw interrupt status */
reg32_t MIS; /**< Masked interrupt status */
reg32_t ICR; /**< Interrupt clear */
reg32_t DMACTL; /**< MMA control */
} uart_regs_t;
/**
@ -123,8 +120,22 @@ typedef struct {
#define UART_IFLS_RXSEL_7_8 0x20
/** @} */
#define UART0 ((uart_regs_t *) (UART0_BASE)) /**< UART0 register bank */
#define UART1 ((uart_regs_t *) (UART1_BASE)) /**< UART0 register bank */
/**
* @ingroup cpu_specific_peripheral_memory_map
* @{
*/
#define UART0_BASE (PERIPH_BASE + 0x1000) /**< UART0 base address */
#define UART1_BASE (PERIPH_BASE + 0xB000) /**< UART1 base address */
/** @} */
/**
* @brief UART0 register bank
*/
#define UART0 ((uart_regs_t *) (UART0_BASE))
/**
* @brief UART1 register bank
*/
#define UART1 ((uart_regs_t *) (UART1_BASE))
#ifdef __cplusplus
} /* end extern "C" */

43
cpu/cc26xx_cc13xx/periph/uart.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2016 Leon George
* Copyright (C) 2020 Locha Inc
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -16,6 +17,7 @@
*
* @author Leon M. George <leon@georgemail.eu>
* @author Anton Gerasimov <tossel@gmail.com>
* @author Jean Pierre Dudey <jeandudey@hotmail.com>
*
* @}
*/
@ -60,10 +62,21 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
int cts_pin = uart_config[uart].cts_pin;
#endif
/* enable clocks: serial power domain and UART */
if (!power_is_domain_enabled(POWER_DOMAIN_SERIAL)) {
power_enable_domain(POWER_DOMAIN_SERIAL);
if (uart == 0) {
/* UART0 requires serial domain to be enabled */
if (!power_is_domain_enabled(POWER_DOMAIN_SERIAL)) {
power_enable_domain(POWER_DOMAIN_SERIAL);
}
}
#ifdef CPU_VARIANT_X2
else if (uart == 1) {
/* UART1 requires periph domain to be enabled */
if (!power_is_domain_enabled(POWER_DOMAIN_PERIPHERALS)) {
power_enable_domain(POWER_DOMAIN_PERIPHERALS);
}
}
#endif
uart_poweron(uart);
/* disable and reset the UART */
@ -74,12 +87,26 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
ctx[uart].arg = arg;
/* configure pins */
IOC->CFG[tx_pin] = IOCFG_PORTID_UART0_TX;
IOC->CFG[rx_pin] = (IOCFG_PORTID_UART0_RX | IOCFG_INPUT_ENABLE);
if (uart == 0) {
IOC->CFG[tx_pin] = IOCFG_PORTID_UART0_TX;
IOC->CFG[rx_pin] = (IOCFG_PORTID_UART0_RX | IOCFG_INPUT_ENABLE);
#ifdef MODULE_PERIPH_UART_HW_FC
if (rts_pin != GPIO_UNDEF && cts_pin != GPIO_UNDEF) {
IOC->CFG[rts_pin] = IOCFG_PORTID_UART0_RTS;
IOC->CFG[cts_pin] = (IOCFG_PORTID_UART0_CTS | IOCFG_INPUT_ENABLE);
if (rts_pin != GPIO_UNDEF && cts_pin != GPIO_UNDEF) {
IOC->CFG[rts_pin] = IOCFG_PORTID_UART0_RTS;
IOC->CFG[cts_pin] = (IOCFG_PORTID_UART0_CTS | IOCFG_INPUT_ENABLE);
}
#endif
}
#ifdef CPU_VARIANT_X2
else if (uart == 1) {
IOC->CFG[tx_pin] = IOCFG_PORTID_UART1_TX;
IOC->CFG[rx_pin] = (IOCFG_PORTID_UART1_RX | IOCFG_INPUT_ENABLE);
#ifdef MODULE_PERIPH_UART_HW_FC
if (rts_pin != GPIO_UNDEF && cts_pin != GPIO_UNDEF) {
IOC->CFG[rts_pin] = IOCFG_PORTID_UART1_RTS;
IOC->CFG[cts_pin] = (IOCFG_PORTID_UART1_CTS | IOCFG_INPUT_ENABLE);
}
#endif
}
#endif