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https://github.com/RIOT-OS/RIOT.git
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cc26x2_cc13x2: fix FCFG1 register offsets
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
This commit is contained in:
Jean Pierre Dudey
parent
cbcd7d58e7
commit
e944638d3d
@ -22,112 +22,102 @@
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extern "C" {
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#endif
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define FCFG_BASE 0x50001000 /**< base address of FCFG memory */
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/*@}*/
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/**
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* FCFG registers
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* @brief FCFG registers
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*/
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typedef struct {
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uint8_t __reserved1[0xA0]; /**< meh */
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/* TODO does it pad here? */
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reg8_t __reserved1[0xA0]; /**< Reserved */
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reg32_t MISC_CONF_1; /**< misc config */
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reg32_t MISC_CONF_2; /**< misc config */
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reg32_t __reserved2[7]; /**< meh */
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reg32_t CONFIG_FE_CC26; /**< internal */
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reg32_t CONFIG_FE_CC13; /**< internal */
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reg32_t CONFIG_RF_COMMON; /**< internal */
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reg32_t CONFIG_SYNTH_DIV2_CC26_2G4; /**< config of synthesizer in divide-by-2-mode */
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reg32_t CONFIG_SYNTH_DIV2_CC13_2G4; /**< config of synthesizer in divide-by-2-mode */
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reg32_t CONFIG_SYNTH_DIV2_CC26_1G; /**< config of synthesizer in divide-by-2-mode */
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reg32_t CONFIG_SYNTH_DIV2_CC13_1G; /**< config of synthesizer in divide-by-2-mode */
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reg32_t CONFIG_SYNTH_DIV4_CC26; /**< config of synthesizer in divide-by-4-mode */
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reg32_t CONFIG_SYNTH_DIV4_CC13; /**< config of synthesizer in divide-by-4-mode */
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reg32_t CONFIG_SYNTH_DIV5; /**< config of synthesizer in divide-by-5-mode */
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reg32_t CONFIG_SYNTH_DIV6_CC26; /**< config of synthesizer in divide-by-5-mode */
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reg32_t CONFIG_SYNTH_DIV6_CC13; /**< config of synthesizer in divide-by-5-mode */
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reg32_t CONFIG_SYNTH_DIV10; /**< config of synthesizer in divide-by-10-mode */
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reg32_t CONFIG_SYNTH_DIV12_CC26; /**< config of synthesizer in divide-by-12-mode */
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reg32_t CONFIG_SYNTH_DIV12_CC13; /**< config of synthesizer in divide-by-12-mode */
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reg32_t CONFIG_SYNTH_DIV15; /**< config of synthesizer in divide-by-15-mode */
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reg32_t CONFIG_SYNTH_DIV30; /**< config of synthesizer in divide-by-30-mode */
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reg32_t __reserved3[23]; /**< meh */
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reg32_t FLASH_NUMBER; /**< manufacturing lot number */
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reg32_t __reserved4; /**< meh */
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reg32_t FLASH_COORDINATE; /**< chip coordinates on a wafer */
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reg32_t FLASH_E_P; /**< internal */
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reg32_t FLASH_C_E_P_R; /**< internal */
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reg32_t FLASH_P_R_PV; /**< internal */
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reg32_t FLASH_EH_SEQ; /**< internal */
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reg32_t FLASH_VHV_E; /**< internal */
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reg32_t FLASH_PP; /**< internal */
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reg32_t FLASH_PROG_EP; /**< internal */
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reg32_t FLASH_ERA_PW; /**< internal */
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reg32_t FLASH_VHV; /**< internal */
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reg32_t FLASH_VHV_PV; /**< internal */
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reg32_t FLASH_V; /**< internal */
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reg32_t __reserved5[38]; /**< meh */
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reg32_t USER_ID; /* user identification */
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reg32_t __reserved6[6]; /**< meh */
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reg32_t FLASH_OTP_DATA3; /**< internal */
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reg32_t ANA2_TRIM; /**< internal */
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reg32_t LDO_TRIM; /**< internal */
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reg32_t __reserved7[11]; /**< meh */
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reg32_t __reserved2[0x2]; /**< Reserved */
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reg32_t HPOSC_MEAS_5; /**< Internal */
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reg32_t HPOSC_MEAS_4; /**< Internal */
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reg32_t HPOSC_MEAS_3; /**< Internal */
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reg32_t HPOSC_MEAS_2; /**< Internal */
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reg32_t HPOSC_MEAS_1; /**< Internal */
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reg32_t CONFIG_FE_CC26; /**< Internal */
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reg32_t CONFIG_FE_CC13; /**< Internal */
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reg32_t CONFIG_RF_COMMON; /**< Internal */
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reg32_t CONFIG_SYNTH_DIV2_CC26_2G4; /**< Config of synthesizer in divide-by-2-mode */
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reg32_t CONFIG_SYNTH_DIV2_CC13_2G4; /**< Config of synthesizer in divide-by-2-mode */
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reg32_t CONFIG_SYNTH_DIV2_CC26_1G; /**< Config of synthesizer in divide-by-2-mode */
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reg32_t CONFIG_SYNTH_DIV2_CC13_1G; /**< Config of synthesizer in divide-by-2-mode */
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reg32_t CONFIG_SYNTH_DIV4_CC26; /**< Config of synthesizer in divide-by-4-mode */
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reg32_t CONFIG_SYNTH_DIV4_CC13; /**< Config of synthesizer in divide-by-4-mode */
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reg32_t CONFIG_SYNTH_DIV5; /**< Config of synthesizer in divide-by-5-mode */
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reg32_t CONFIG_SYNTH_DIV6_CC26; /**< Config of synthesizer in divide-by-5-mode */
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reg32_t CONFIG_SYNTH_DIV6_CC13; /**< Config of synthesizer in divide-by-5-mode */
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reg32_t CONFIG_SYNTH_DIV10; /**< Config of synthesizer in divide-by-10-mode */
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reg32_t CONFIG_SYNTH_DIV12_CC26; /**< Config of synthesizer in divide-by-12-mode */
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reg32_t CONFIG_SYNTH_DIV12_CC13; /**< Config of synthesizer in divide-by-12-mode */
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reg32_t CONFIG_SYNTH_DIV15; /**< Config of synthesizer in divide-by-15-mode */
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reg32_t CONFIG_SYNTH_DIV30; /**< Config of synthesizer in divide-by-30-mode */
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reg32_t __reserved3[0x17]; /**< Reserved */
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reg32_t FLASH_NUMBER; /**< Manufacturing lot number */
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reg32_t __reserved4; /**< Reserved */
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reg32_t FLASH_COORDINATE; /**< Chip coordinates on a wafer */
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reg32_t FLASH_E_P; /**< Internal */
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reg32_t FLASH_C_E_P_R; /**< Internal */
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reg32_t FLASH_P_R_PV; /**< Internal */
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reg32_t FLASH_EH_SEQ; /**< Internal */
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reg32_t FLASH_VHV_E; /**< Internal */
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reg32_t FLASH_PP; /**< Internal */
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reg32_t FLASH_PROG_EP; /**< Internal */
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reg32_t FLASH_ERA_PW; /**< Internal */
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reg32_t FLASH_VHV; /**< Internal */
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reg32_t FLASH_VHV_PV; /**< Internal */
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reg32_t FLASH_V; /**< Internal */
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reg32_t __reserved5[0x3E]; /**< Reserved */
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reg32_t USER_ID; /* User identification */
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reg32_t __reserved6[0x6]; /**< Reserved */
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reg32_t FLASH_OTP_DATA3; /**< Internal */
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reg32_t ANA2_TRIM; /**< Internal */
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reg32_t LDO_TRIM; /**< Internal */
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reg32_t __reserved7[0xB]; /**< Reserved */
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reg32_t MAC_BLE_0; /**< MAC BLE address 0 */
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reg32_t MAC_BLE_1; /**< MAC BLE address 1 */
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reg32_t MAC_15_4_0; /**< MAC IEEE 802.15.4 address 0 */
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reg32_t MAC_15_4_1; /**< MAC IEEE 802.15.4 address 1 */
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reg32_t __reserved8[4]; /**< meh */
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reg32_t __reserved8[0x4]; /**< Reserved */
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reg32_t FLASH_OTP_DATA4; /**< Internal */
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reg32_t MISC_TRIM; /**< Miscellaneous trim parameters */
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reg32_t RCOSC_HF_TEMPCOMP; /**< Internal */
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reg32_t __reserved9; /**< meh */
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reg32_t __reserved9; /**< Reserved */
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reg32_t ICEPICK_DEVICE_ID; /**< IcePick Device Identification */
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reg32_t FCFG1_REVISION; /**< Factory configuration revision */
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reg32_t MISC_OTP_DATA; /**< Miscelanous OTP data */
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reg32_t __reserved10[8]; /**< meh */
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reg32_t __reserved10[0x8]; /**< Reserved */
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reg32_t IOCONF; /**< I/O Configuration */
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reg32_t __reserved11; /**< meh */
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reg32_t __reserved11; /**< Reserved */
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reg32_t CONFIG_IF_ADC; /**< Internal */
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reg32_t CONFIG_OSC_TOP; /**< Internal */
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reg32_t __reserved12[2]; /**< meh */
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reg32_t __reserved12[0x2]; /**< Reserved */
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reg32_t SOC_ADC_ABS_GAIN; /**< AUX_ADC gain in absolute reference mode */
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reg32_t SOC_ADC_REL_GAIN; /**< AUX_ADC gain in relative reference mode */
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reg32_t __reserved13; /**< meh */
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reg32_t __reserved13; /**< Reserved */
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reg32_t SOC_ADC_OFFSET_INT; /**< AUX_ADC temperature offsets in absolute reference mode */
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reg32_t SOC_ADC_REF_TRIM_AND_OFFSET_EXT; /**< Internal */
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reg32_t AMPCOMP_TH1; /**< Internal */
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reg32_t AMPCOMP_TH2; /**< Internal */
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reg32_t AMPCOMP_CTRL1; /**< Internal */
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reg32_t ANABYPASS_VALUE2; /**< Internal */
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reg32_t __reserved14[2]; /**< meh */
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reg32_t __reserved14[0x2]; /**< Reserved */
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reg32_t VOLT_TRIM; /**< Internal */
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reg32_t OSC_CONF; /**< OSC configuration */
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reg32_t FREQ_OFFSET; /**< Internal */
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reg32_t __reserved15; /**< meh */
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reg32_t __reserved15; /**< Reserved */
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reg32_t MISC_OTP_DATA_1; /**< Internal */
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reg32_t PWD_CURR_20C; /**< power down current control 20C */
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reg32_t PWD_CURR_35C; /**< power down current control 35C */
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reg32_t PWD_CURR_50C; /**< power down current control 50C */
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reg32_t PWD_CURR_65C; /**< power down current control 65C */
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reg32_t PWD_CURR_80C; /**< power down current control 80C */
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reg32_t PWD_CURR_95C; /**< power down current control 95C */
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reg32_t PWD_CURR_110C; /**< power down current control 110C */
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reg32_t PWD_CURR_125C; /**< power down current control 125C */
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reg32_t __reserved16[5]; /**< meh */
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reg32_t SHDW_DIE_ID_0; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_0.* */
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reg32_t SHDW_DIE_ID_1; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_1.* */
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reg32_t SHDW_DIE_ID_2; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_2.* */
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reg32_t SHDW_DIE_ID_3; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_3.* */
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reg32_t __reserved17[2]; /**< meh */
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reg32_t __reserved16[0xC]; /**< Reserved */
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reg32_t SHDW_DIE_ID_0; /**< Shadow of JTAG_TAP::EFUSE::DIE_ID_0.* */
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reg32_t SHDW_DIE_ID_1; /**< Shadow of JTAG_TAP::EFUSE::DIE_ID_1.* */
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reg32_t SHDW_DIE_ID_2; /**< Shadow of JTAG_TAP::EFUSE::DIE_ID_2.* */
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reg32_t SHDW_DIE_ID_3; /**< Shadow of JTAG_TAP::EFUSE::DIE_ID_3.* */
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reg32_t __reserved17[0x7]; /**< Reserved */
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reg32_t SHDW_OSC_BIAS_LDO_TRIM; /**< Internal */
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reg32_t SHDW_ANA_TRIM; /**< Internal */
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reg32_t __reserved18[3]; /**< meh */
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reg32_t __reserved18[0x3]; /**< Reserved */
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reg32_t DAC_BIAS_CNF; /**< Internal */
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reg32_t __reserved19[2]; /**< meh */
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reg32_t __reserved19[0x2]; /**< Reserved */
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reg32_t TFW_PROBE; /**< Internal */
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reg32_t TFW_FT; /**< Internal */
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reg32_t DAC_CAL0; /**< Internal */
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@ -136,7 +126,20 @@ typedef struct {
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reg32_t DAC_CAL3; /**< Internal */
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} fcfg_regs_t;
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#define FCFG ((fcfg_regs_t *) (FCFG_BASE)) /**< FCFG register bank */
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief FCFG1 base address
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*/
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#define FCFG_BASE (0x50001000)
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/** @} */
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/**
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* @brief FCFG1 register bank
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*/
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#define FCFG ((fcfg_regs_t *) (FCFG_BASE))
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#ifdef __cplusplus
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} /* end extern "C" */
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@ -144,4 +147,4 @@ typedef struct {
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#endif /* CC26X2_CC13X2_FCFG_H */
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/*@}*/
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/** @} */
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