cc26xx_cc13xx: add ADI3 and masked access

- Added ADI instruction offsets
- Added register banks and address bases for masked access (writes).

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>

cpu/cc26x2_cc13x2/include/cc26x2_cc13x2_aux.h

@@ -416,6 +416,35 @@ typedef struct {
     reg8_t LPMBIAS; /**< Internal */
 } adi_4_aux_regs_t;
 
+/**
+ * @brief   ADI_4_AUX registers using masked 8-bit access
+ */
+typedef struct {
+    reg8_m8_t MUX0; /**< Multiplexer 0 */
+    reg8_m8_t MUX1; /**< Multiplexer 1 */
+    reg8_m8_t MUX2; /**< Multiplexer 2 */
+    reg8_m8_t MUX3; /**< Multiplexer 3 */
+    reg8_m8_t ISRC; /**< Current Source */
+    reg8_m8_t COMP; /**< Comparator */
+    reg8_m8_t MUX4; /**< Multiplexer 4 */
+    reg8_m8_t ADC0; /**< ADC Control 0 */
+    reg8_m8_t ADC1; /**< ADC Control 1 */
+    reg8_m8_t ADCREF0; /**< ADC Reference 0 */
+    reg8_m8_t ADCREF1; /**< ADC Reference 1 */
+    reg8_m8_t __reserved1[0x3]; /**< Reserved */
+    reg8_m8_t LPMBIAS; /**< Internal */
+} adi_4_aux_regs_m8_t;
+
+/**
+ * @brief   ADI_4_AUX register values
+ * @{
+ */
+#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_m 0x00000038
+#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_s 3
+#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_m    0x0000003F
+#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_s    0
+/** @} */
+
 /**
  * @ingroup cpu_specific_peripheral_memory_map
  * @{
@@ -424,12 +453,20 @@ typedef struct {
  * @brief   ADI_4_AUX base address
  */
 #define ADI_4_AUX_BASE       (PERIPH_BASE + 0xCB000)
+/**
+ * @brief   ADI_4_AUX base address for masked 8-bit access
+ */
+#define ADI_4_AUX_BASE_M8    (ADI_4_AUX_BASE + ADI_MASK8B)
 /** @} */
 
 /**
  * @brief   ADI_4_AUX register bank
  */
 #define ADI_4_AUX            ((adi_4_aux_regs_t *) (ADI_4_AUX_BASE))
+/**
+ * @brief   ADI_4_AUX register bank
+ */
+#define ADI_4_AUX_M8         ((adi_4_aux_regs_m8_t *) (ADI_4_AUX_BASE_M8))
 
 /**
  * @brief   Semamphore used for ADDI

cpu/cc26xx_cc13xx/include/cc26xx_cc13xx.h

@@ -146,6 +146,18 @@ typedef enum IRQn
 #define PERIPH_BASE_NONBUF 0x60000000 /**< Peripheral base address (nonbuf) */
 /*@}*/
 
+/**
+ * @brief   ADI master instruction offsets
+ * @{
+ */
+#define ADI_DIR            0x00000000
+#define ADI_SET            0x00000010
+#define ADI_CLR            0x00000020
+#define ADI_MASK4B         0x00000040
+#define ADI_MASK8B         0x00000060
+#define ADI_MASK16B        0x00000080
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_adi.h

@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2020 Locha Inc
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_cc26xx_cc13xx_definitions
+ * @{
+ *
+ * @file
+ * @brief           CC26xx/CC13xx MCU I/O register definitions
+ *
+ * @author          Jean Pierre Dudey <jeandudey@hotmail.com>
+ */
+
+#ifndef CC26XX_CC13XX_ADI_H
+#define CC26XX_CC13XX_ADI_H
+
+#include "cc26xx_cc13xx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   ADI_3_REFSYS registers
+ */
+typedef struct {
+    reg8_t __reserved1; /**< Reserved */
+    reg8_t ATESTCTL1; /**< Internal */
+    reg8_t REFSYSCTL0; /**< Internal */
+    reg8_t REFSYSCTL1; /**< Internal */
+    reg8_t REFSYSCTL2; /**< Internal */
+    reg8_t REFSYSCTL3; /**< Internal */
+    reg8_t DCDCCTL0; /**< DCDC Control 0 */
+    reg8_t DCDCCTL1; /**< DCDC Control 1 */
+    reg8_t DCDCCTL2; /**< DCDC Control 2 */
+    reg8_t DCDCCTL3; /**< Internal */
+    reg8_t DCDCCTL4; /**< Internal */
+    reg8_t DCDCCTL5; /**< Internal */
+#ifdef CPU_VARIANT_X2
+    reg8_t AUX_DEBUG; /**< RECHARGE_CONTROL_1 */
+    reg8_t CTL_RECHARGE_CMP0; /**< Recharge Comparator Control Byte 0 */
+    reg8_t CTL_RECHARGE_CMP1; /**< Recharge Comparator Control Byte 1 */
+#endif
+} adi_3_refsys_regs_t;
+
+/**
+ * @brief   ADI_3_REFSYS registers
+ */
+typedef struct {
+    reg8_m4_t __reserved1; /**< Reserved */
+    reg8_m4_t ATESTCTL1; /**< Internal */
+    reg8_m4_t REFSYSCTL0; /**< Internal */
+    reg8_m4_t REFSYSCTL1; /**< Internal */
+    reg8_m4_t REFSYSCTL2; /**< Internal */
+    reg8_m4_t REFSYSCTL3; /**< Internal */
+    reg8_m4_t DCDCCTL0; /**< DCDC Control 0 */
+    reg8_m4_t DCDCCTL1; /**< DCDC Control 1 */
+    reg8_m4_t DCDCCTL2; /**< DCDC Control 2 */
+    reg8_m4_t DCDCCTL3; /**< Internal */
+    reg8_m4_t DCDCCTL4; /**< Internal */
+    reg8_m4_t DCDCCTL5; /**< Internal */
+#ifdef CPU_VARIANT_X2
+    reg8_m4_t AUX_DEBUG; /**< RECHARGE_CONTROL_1 */
+    reg8_m4_t CTL_RECHARGE_CMP0; /**< Recharge Comparator Control Byte 0 */
+    reg8_m4_t CTL_RECHARGE_CMP1; /**< Recharge Comparator Control Byte 1 */
+#endif
+} adi_3_refsys_regs_m4_t;
+
+/**
+ * @brief   ADI3 register values
+ * @{
+ */
+#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST 0x00000002
+#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN   0x00000040
+/** @} */
+
+/**
+ * @ingroup cpu_specific_peripheral_memory_map
+ * @{
+ */
+/**
+ * @brief   ADI3 base address
+ */
+#define ADI_3_REFSYS_BASE    (PERIPH_BASE + 0x86200)
+/**
+ * @brief   ADI3 base address for SET instruction
+ */
+#define ADI_3_REFSYS_BASE_SET (ADI_3_REFSYS_BASE + ADI_SET)
+/**
+ * @brief   ADI3 base address for CLR instruction
+ */
+#define ADI_3_REFSYS_BASE_CLR (ADI_3_REFSYS_BASE + ADI_CLR)
+/**
+ * @brief   ADI3 base address for 4-bit masked access
+ */
+#define ADI_3_REFSYS_BASE_M4 (ADI_3_REFSYS_BASE + ADI_MASK4B)
+/** @} */
+
+/**
+ * @brief   ADI3 register bank
+ */
+#define ADI3                 ((adi_3_refsys_regs_t *) (ADI_3_REFSYS_BASE))
+/**
+ * @brief   ADI3 register bank for SET instruction
+ */
+#define ADI3_SET             ((adi_3_refsys_regs_t *) (ADI_3_REFSYS_BASE_SET))
+/**
+ * @brief   ADI3 register bank for CLR instruction
+ */
+#define ADI3_CLR             ((adi_3_refsys_regs_t *) (ADI_3_REFSYS_BASE_CLR))
+/**
+ * @brief   ADI3 register bank for 4-bit masked access
+ */
+#define ADI3_M4              ((adi_3_refsys_regs_m4_t *) (ADI_3_REFSYS_BASE_M4))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CC26XX_CC13XX_ADI_H */
+/** @} */

cpu/cc26xx_cc13xx/include/cpu_conf_cc26xx_cc13xx.h

@@ -24,6 +24,7 @@
 
 #include "cc26xx_cc13xx.h"
 
+#include "cc26xx_cc13xx_adi.h"
 #include "cc26xx_cc13xx_ccfg.h"
 #include "cc26xx_cc13xx_gpio.h"
 #include "cc26xx_cc13xx_gpt.h"