`flashpage_write_raw()` got renamed to `flashpage_write()`.
Now `sam0_flashpage_aux_write_raw()` is the only remaining 'raw'
function, even though it behaves just like `flashpage_write()`.
So let's also rename that for consistency.
Flash Customer Configuration Area (CCA) is never written when the
riotboot module is used. This required a riot application to have
been previously flashed. riotboot will completely ignore this
section, neither writing or erasing it.
Slot flashing is currenly only supported with Jlink.
Co-authored-by: Brenton Chetty <brent7984@gmail.com>
Note that Kconfig.models was not generated with gen_kconfig.py tool
due to lack of ProductsList.xlsx file for STM32MP1 family.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In STM32MP1 family, independant watchdogs (IWDG1 and IWDG2) are
dedicated to the MPU (Cortex-A7). Thus simply disable the feature
for STM32MP1 family.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
The stm32mp157c has the particularity to not having flash memory but
only SRAM.
Thus a part of SRAM must be considered as a ROM to flash the firmware
into.
In case of the stm32mp157c, the RETRAM (64kB) is used as ROM and the
4 banks of SRAM (384kB) are used as RAM.
However, as ROM_LEN, RAM_LEN, ROM_START_ADDRESS, RAM_START_ADDRESS and
ROM_OFFSET could be overloaded by user, set them with "?=" operator.
If the ROM_START_ADDRESS and the RAM_START_ADDRESS are not set at the
end of that file, it is a classic stm32 MCU with flash, thus set this
variables with common memory addresses for stm32 MCU family:
ROM_START_ADDR ?= 0x08000000
RAM_START_ADDR ?= 0x20000000
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In Engineering mode (BOOT0 off and BOOT2 on), only the Cortex-M4
core is running. It means that all clocks have to be setup
by the Cortex-M4 core.
In other modes, the clocks are setup by the Cortex-A7 and then should
not be setup by Cortex-M4.
stm32mp1_eng_mode pseudomodule have to be used in Engineering mode
to ensure clocks configuration with IS_USED(MODULE_STM32MP1_ENG_MODE)
macro.
This macro can also be used in periph_conf.h to define clock source
for each peripheral.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
STM32_PM_STOP and STM32_PM_STANDBY are always defined in periph_cpu.h,
Thus it is not needed to test them.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
According to stm32mp157 documentation:
* "The CStop mode is entered for MCU when the SLEEPDEEP bit in the Cortex®-M4 System Control
register is set." Thus set PM_STOP_CONFIG to 0.
* "The CStandby mode applies only to the MPU sub-system."
Set PM_STANDBY_CONFIG to (0) and do not enter standby mode for
stm32mp1.
As PM_STOP_CONFIG is already defined before for CPU_FAM_STM32WB, replace
it with CPU_FAM_STM32MP1.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
stm32mp1 is configuring gpio slightly differently that common stm32:
* port_num is computed differently, thus test MCU family to apply
the good calculation.
* Rising and falling edge state on interrupts. Do not test if falling
or rising edge, just launch the callback in all cases.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
Normally, CMSIS headers are retrieved as package from ST git repository
for each stm32.
However stm32mp1 family does not have a CMSIS headers repository but
have been included into RIOT source code in a previous commit.
For stm32mp1, CMSIS headers package must then not be retrieved and
vectors have to be generated from already in-source CMSIS headers.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
Include stm32mp1 vendors header. CORE_CM4 must be defined to include
Cortex-M4 core headers.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
stm32mp1 ordering informations are not the same than classical
single MCU.
And as stm32mp1 has no flash, just extract second part of model name
and pincount.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
The stm32mp1 family has no flash. The firmware is loaded directly in
RAM by stlink programmer or by Cortex-A7 bootloader/OS.
Thus bootloader is useless for this family, disable it.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
As stm32mp1 family accesses gpio pins with a different
offset than other stm32, create a specific macro.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
clk_conf is a useful tool to produce clock headers for new boards.
But it only supports STM32Fx families.
This commits add the definition of a new family: STM32MP1.
Only the STM32MP157 is supported for now.
First build clk_conf:
$ make -C cpu/stm32/dist/clk_conf/
Clock header can be generated with the following command once clk_conf is
built:
$ cpu/stm32/dist/clk_conf/clk_conf stm32mp157 208000000 24000000 1
This command line will produce a core clock of 208MHz with a 24MHz HSE
oscillator and will use LSE clock which corresponds to the STM32MP157C-DK2
board configuration.
The command will output the header to copy paste into the periph_conf.h of
the board:
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 209MHz */
#define CLOCK_CORECLOCK (208000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (24000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_MCU_DIV RCC_MCUDIVR_MCUDIV_1 /* max 209MHz */
#define CLOCK_MCU (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_APB1DIVR_APB1DIV_2 /* max 104MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_APB2DIVR_APB2DIV_2 /* max 104MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB3_DIV RCC_APB3DIVR_APB3DIV_2 /* max 104MHz */
#define CLOCK_APB3 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (2)
#define CLOCK_PLL_N (52)
#define CLOCK_PLL_P (3)
#define CLOCK_PLL_Q (13)
/** @} */
This result has been verified with STM32CubeMX, the official ST tool.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
APB1 bus clock is always enabled is not manageable by RCC register.
So avoid enabling it.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
* Setup i2c speed to I2C_SPEED_LOW by default
* enable i2c_write_regs() function.
* i2c frequency needs to be specified into board periph_conf.h
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
In some CMSIS headers, "typedef enum" could be preceded by white
spaces. Thus consider them when parsing the line.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
b4f29035ce adapted the can_linux module to
the periph_can interface. This is a cleanup of some things that stayed
behind. Here the makefile is removed, the references to can_linux in the
dependency resolution and configuration Makefile are changed to the
standard periph_can, and the startup code is adapted.
Default values were wrong for WB when using HSE 32MHz as PLL input source
Default PLL input source was wrong when not using HSE and the board
provides an HSE
By using the RTC helper functions instead of POSIX mktime()/gmtime()
we can not only extend the RTC range beyond Y2038.
For tests/periph_rtc:
before:
text data bss dec hex filename
28028 248 2472 30748 781c stk3700/tests_periph_rtc.elf
after:
text data bss dec hex filename
19400 144 2424 21968 55d0 stk3700/tests_periph_rtc.elf
fixes#13277
irq_arch.h previously included cpu.h, which in term included the vendor header
files. Those were needed to get the GIE define (general interrupt enable bit).
However, the vendor files use fancy defines like `#define N (0x0004)` that
easily conflict with application code. Due to the widespread use of the IRQ API,
it is better to not include the vendor files in irq_arch.h.
This commit adds a local define for the GIE bit and uses this instead of
including cpu.h.
If no local port is specified for socket_zep to listen on, don't listen
on a local port at all instead of listening on a default port.
This does not work with multiple instances of socket_zep anyway.
The reception code hands RX DMA descriptors back to the DMA right after its
contents were copied into the network stack internal buffer. This increases
the odds that the DMA never runs out of DMA descriptors to fill, even under
high load. However, the loop fetching the Ethernet frame stops to iterate at the
end of the frame. If the DMA used one more descriptor to store the FCS, this
was not returned back to the DMA. This commit fixes it.
Some SAMD21 CPUs from the D series have an additional TCC3 and / or
an additional analog comperator.
Add those to `vectors.c`.
Also rename the i2s interrupt to the proper name used by other sam0
devices.
MCG_Lite is used in many KL parts and is a less advanced clock generator
than the full MCG used in the K series. This change lets the MCG_Lite
and MCG share the same user facing API, with some configuration
differences.
Expose the auto-negotiation feature of the Ethernet device via the
pseudo-module stm32_eth_auto. With this enabled, the static speed configuration
set in the boards periph_conf.h will only be used if the PHY lacks
auto-negotiation capabilities - which is unlikely to ever happen.
When enabling & disabling interrupts back-to-back pending interrupts
are not serviced on Cortex-M23/M33.
Flush the pipeline to give interrupts a chance of executing in `sched_arch_idle()`.
This fixes `no_idle_thread` on Cortex-M23.
The RISC-V toolchain in riotdocker has issues with picolibc and
will still include newlib headers.
This leads to conflicts like
```
In file included from [01m[Knanostubs.c:22[m[K:
[01m[K/usr/local/picolibc/riscv-none-embed/include/stdio.h:270:23:[m[K [01;31m[Kerror: [m[Kconflicting types for '[01m[K__FILE[m[K'
typedef struct __file [01;31m[K__FILE[m[K;
[01;31m[K^~~~~~[m[K
In file included from [01m[K/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/riscv-none-embed/include/reent.h:93[m[K,
from [01m[Knanostubs.c:20[m[K:
[01m[K/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/riscv-none-embed/include/sys/reent.h:287:26:[m[K [01;36m[Knote: [m[Kprevious declaration of '[01m[K__FILE[m[K' was here
typedef struct __sFILE [01;36m[K__FILE[m[K;
[01;36m[K^~~~~~[m[K
```
The problem does not occur when installing both the toolchain and picolibc
directly from the Debian / Ubuntu repositories, but CI uses an older Ubuntu
version that does not have those packages yet, so it builds them manually.
Blacklist RISC-V until CI has been updated.
> Fixes a typo on XOSC selection bitfield that would
make the CPU crash when changing it.
> Sets the other fields to their default values.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
Previously, only an link-up event was triggered, not an link down event. And
additionally, once the link-up event was sent, the link status was no longer
monitored. As a result, once a link-up was sent, no further link event were
triggered.
The methods to read from / write to MII registers had an address argument to
allow specifying the PHY to communicate with. However, only a single PHY is
available on all boards supported and the driver is not able to operate with
multiple PHYs anyway - thus, drop this parameter for ease of use.
This fixes a bug in the _get_link_status() function, which used hard coded the
address 0; which might not be correct for all boards.
read_csr() returns an unsigned long, not a uint32_t. This causes a
-Wformat warning to be emitted when compiling with clang. This commit
fixes the warning by changing the format string.
This requires -nostartfiles to be only passed to the linker, not the
compiler, as it is a linker flag and passing it to the compiler causes a
clang warning to be emitted.
Additionally, clang does not seem to support `-mcmodel=medlow` and
`-msmall-data-limit=8` but these options do not seem strictly necessary
to me anyhow thus they are deactivated conditionally when using clang.
The link status was previously not returned via the value parameter, as required
by the netdev_driver_t API. As a result, e.g. the `ifconfig` shell command
showed garbage.
It turns out hooking up an unused peripheral to a disabled GCLK
leads to surprising power savings.
Name the GCLK to be more explicit (and since not all members of
the extended samd2x family have a GCLK7).
Turns out we can just use a non-existing GCLK ID for this, this
even saves us a real GCLK that we can use for something else.
Also make sure to disable *all* peripherals by using
`GCLK_CLKCTRL_ID_Msk` instead of relying on a magic value.
Looks like we previously missed some, since this leads to some
additional power savings:
master: 4.22 mA
this patch: 4.09 mA
>Now `ROM_LEN` is the "real" length, 352K and 128K respectively
and the CCFG position is determined by subtracting it's size
from `_rom_length` symbol.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
The PWM decodeer, in LOAD=Single mode, loads data in groups of 4
half-words. Previously, if any channel was not connected to a pin (a
connection that's immaterial to the loader), a smaller number would be
given resulting in the decoder not loading anything at all.
See-Also: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf#page=256
Once PWM is running, the active PWM module overrides the PIN_CNF state;
only when PWM is stopped the pin returns into its PIN_CNF state (which,
then, the board may set to whatever idle means there).
(Moreover, the code there only worked for P0 registers, not eg. the
P1.09 of the nrf52840dongle's RGB LED).
Native CAN device was not properly ported to periph_can interface.
This commit fixes this by renaming all needed structures and files so
auto_init_can can initialize the native device. FEATURES_PROVIDED is
also updated for native.
- Enforced that ISR_STACKSIZE is indeed a multiple of 4
- With this enforced, every cast that triggers a -Wcast-align warning is now
a false positives, so those were silenced by (intermediately) casting to
`uintptr_t`.
This didn't change binaries for me. Either the linker script already took care
of it through the section names of the stacks, or I just was lucky. If I was
just luck, this fixes a bug. If not, it makes the hidden alignment explicit in
the C code, so that code review is easier.
Verified that each warning generated by -Wcast-align is indeed a false positive
and used an (intermediate) cast to `uintptr_t` to silence the warnings.
This is an implementation of the ESP32 SoftAP mode using the
`esp_wifi_ap` pseudomodule.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
> Allows flahsing CCFG configuration using Kconfig,
formely "make menuconfig".
> Supports cc26x0, cc26x2_cc13x2.
> Can be used to enable bootloader backdoor, to use
cc2538-bsl flashing script.
> Not all options are in Kconfig, most important ones,
others can be added in further commits.
> On cc13xx targets the VDDR high option can be enabled
using Kconfig.
> With this, RIOT can flash blank chips and the firmware
will run just fine.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
This add a custom ldscript for cc26xx_cc13xx CPUs,
which allows linking CCFG configuration, usage of GPRAM,
etc.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
The RTC on the fe310 is emulated using the RTT.
This only works if the RTT frequency is 1 Hz, so default to that
value in case `periph_rtc` is selected.
Use RTC helper functions instead of libc functions.
This gives us y2038 safety by the extended epoch and saves
a good chunk of memory:
picolibc mktime():
text data bss dec hex filename
15048 520 2504 18072 4698 tests/periph_rtc/bin/hifive1/tests_periph_rtc.elf
rtc_mktime():
text data bss dec hex filename
7632 40 2452 10124 278c tests/periph_rtc/bin/hifive1/tests_periph_rtc.elf
This modifies the cortex-m thread specifics to allow running the PendSV
interrupt continuously at lower priority and removes the priority
modifications during the interrupt itself. Interrupts are disabled
during the scheduling itself, but enabled briefly after the sleep to
ensure that they are handled if activated during the scheduling or the
sleep.
