4d96c1f8e0
Merge pull request #17281 from dylad/pr/cpu/stm32/usbdev_fs_support
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cpu/stm32: add new usbdev FS support
2021-12-02 21:57:49 +01:00
Marian Buschsieweke
ec39b8e3aa
Merge pull request #17320 from aabadie/pr/cpu/stm32_ztimer
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cpu/stm32: migrate adc and eth periphs to ztimer
2021-12-02 20:05:43 +01:00
dylad
f5cd2d1438
cpu/stm32: enable HSI48 when needed for L4/Wx
2021-12-02 14:26:03 +01:00
dylad
083e53406d
cpu/stm32: add support for a new USBDEV periph
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Also rename the other usbdev driver to avoid conflicts
2021-12-02 14:26:03 +01:00
924c2fd6da
cpu/stm32/adc: migrate to ztimer
2021-12-02 13:44:03 +01:00
0c7d2a0f55
cpu/stm32/eth: migrate to ztimer
2021-12-02 12:22:41 +01:00
337b99002a
cpu/stm32/stmclk: enable 48MHz when usbdev is used
2021-12-01 10:15:19 +01:00
f07696e7a2
cpu/stm32/usbdev: poweron USB during initialization
2021-12-01 10:15:19 +01:00
6c60326612
cpu/stm32/kfconfigs: add new CPU from L4 family
2021-11-29 14:26:00 +01:00
a9106719c2
cpu/stm32/kfconfigs: add new CPUs from G4 family
2021-11-29 14:20:20 +01:00
658fa5d048
cpu/stm32/kfconfigs: add new CPUs from G0 family
2021-11-29 14:19:16 +01:00
16db45f77e
cpu/stm32: fix missing clock configuration defines for g0
2021-11-29 14:12:18 +01:00
d09f2e99e3
cpu/stm32/kfconfigs: add new CPUs from WB family
2021-11-29 13:57:20 +01:00
1746bf9e6f
cpu/stm32/dist: fix bug in gen_kconfig.py script
2021-11-29 13:52:26 +01:00
6a219d7cfa
cpu/stm32: bump cmsis versions to latest release
2021-11-29 13:22:59 +01:00
Gunar Schorcht
007e29ebb5
cpu/periph/i2c: update implementations to new I2C API
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Make all `spi_acquire` implementations return `void` and add assertions to check for valid device identifier where missing.
2021-11-29 06:35:25 +01:00
06530c4297
cpu/stm32: clone cmsis header in build/stm32
2021-11-19 13:24:57 +01:00
c81df904ea
stm32/usbdev: Adapt to xmit API
2021-11-16 20:17:04 +01:00
76215adef1
Merge pull request #17154 from maribu/cpu/stm32/periph_usb
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cpu/stm32/periph/usbdev: fix alignment issues
2021-11-16 11:20:34 +01:00
Francisco
72abac66f1
Merge pull request #17183 from fjmolinas/pr_stm32wl_adc
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cpu/stm32/wl: initial periph_adc implementation
2021-11-15 19:06:24 +01:00
benpicco
70ae34a448
Merge pull request #16979 from ospoco/master
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cpu/stm32: Add hardening changes to stm32
2021-11-15 15:09:01 +01:00
Francisco Molina
63c51d4add
cpu/stm32/wl: initial periph_adc implementation
2021-11-15 09:52:45 +01:00
VanL
ee832148b3
cpu/stm32: Add hardening changes to stm32
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Initialize STM32 RDP in a glitch-resistant fashion to prevent
debugger use when restrictions are set by the designer.
2021-11-11 15:58:52 -06:00
Francisco Molina
ec0e3d242e
cpu/stm32/include/cpu_conf_stm32_common.h: fix typo in macro
2021-11-11 19:58:34 +01:00
Marian Buschsieweke
825a598ca7
cpu/stm32/periph/usbdev: fix alignment issues
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Make sure in `_usbdev_new_ep()` that `usbdev_ep_t::buf` is always aligned to 4
bytes. With this in mind, add intermediate casts to `uintptr_t` before casting
`usbdev_ep_t::buf` to `uint32_t *` to silence `-Wcast-align`, as we now manually
enforced correct alignment.
2021-11-06 20:19:39 +01:00
Leandro Lanzieri
f64b166319
Merge pull request #16845 from MrKevinWeiss/pr/kconfig/supportstms
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.murdock: Add nucleo boards to kconfig test
2021-11-01 09:55:22 +01:00
766ebf0af5
stm32/usbdev: Use ztimer instead of xtimer
2021-10-27 18:56:42 +02:00
MrKevinWeiss
9b6a63a951
drivers/kconfig: simplify shared rtt/rtc hardware in kconfig
2021-10-14 11:28:46 +02:00
MrKevinWeiss
c7820cf7e5
*/rtt|rtc: Fix Kconfig modeling
2021-10-14 11:28:44 +02:00
benpicco
ffd1254eac
Merge pull request #16959 from bissell-homecare-inc/stm32g031-disco
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boards/stm32g031-disco,examples,tests: Added STM32G031-DISCO board
2021-10-13 23:17:06 +02:00
Dave VanKampen
55ea8cfb97
boards/stm32g031-disco,examples,tests: Added STM32G031-DISCO board
2021-10-13 12:14:45 -04:00
kl
0f2d10dfb7
cpu/stm32: add HWRNG support to CPU_LINE STM32F469XX
2021-10-13 11:22:45 +02:00
luisan00
af4c01bbc6
cpu/stm32: add stm32f469i to ADCs defs
2021-10-11 23:35:48 +02:00
luisan00
6459d4c344
cpu/stm32: fix duplicated defs
2021-10-10 00:04:51 +02:00
Francisco
211c1a51d8
Merge pull request #16886 from bissell-homecare-inc/g030_ram_len
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cpu/stm32: added RAM_LEN identifier for stm32g03x
2021-09-28 13:40:42 +02:00
benpicco
d1768e95a5
Merge pull request #16885 from bissell-homecare-inc/g0_adc
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cpu/stm32: added ADC for g0
2021-09-25 18:32:19 +02:00
Dave VanKampen
6414c64f89
cpu/stm32: added ADC for g0
2021-09-24 10:20:09 -04:00
Dave VanKampen
664f5d156d
cpu/stm32: added RAM_LEN identifier for stm32g03x
2021-09-23 10:06:33 -04:00
Dave VanKampen
7ab8ec391a
cpu/stm32: added APB12 bus multiplier entry for applicable cpus
2021-09-23 08:46:52 -04:00
Jean Pierre Dudey
ffff68deaf
Merge pull request #16813 from jeandudey/doc1
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cpu: fix doxygen grouping warnings
2021-09-13 11:30:27 +02:00
Francisco Molina
8e17b67a2f
cpu/stm32: add rtc_mem
2021-09-07 10:06:31 +02:00
Jean-Pierre De Jesus DIAZ
9d1cff3b55
cpu/stm32: fix doxygen grouping warnings
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Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
2021-09-05 20:39:15 +02:00
Hugues Larrive
f292cfc8ce
drivers/periph_spi: remove duplicated includes introduced in #15902
2021-09-02 09:40:31 +02:00
Francisco
a1cbcc9ede
Merge pull request #15902 from maribu/spi-api-change-1
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drivers/periph_spi: let spi_acquire return void
2021-09-02 08:50:56 +02:00
Marian Buschsieweke
f04b522601
cpu/periph_spi: update implementations to new API
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Make all spi_acquire() implementations return `void` and add assertions to
check for valid parameters, where missing.
2021-09-01 21:38:40 +02:00
Benjamin Valentin
f903ec90d4
drivers/flashpage: flashpage_page() takes a const argument
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All addresses to flashpage_page() must be in flash. Flash memory is
`const`, therefore this function must also take `const` pointers.
2021-08-27 14:08:25 +02:00
benpicco
0b69747389
Merge pull request #16023 from maribu/max_pdu_size
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sys/net/netopt: Drop deprecated NETOPT_MAX_PACKET_SIZE
2021-08-26 14:40:18 +02:00
Benjamin Valentin
39b81c332e
cpu/stm32: remove ErrorStatus enum from vendor files
2021-08-25 18:42:40 +02:00
Jan Romann
4384795cb9
treewide: Remove excessive newlines
2021-08-13 19:50:38 +02:00
benpicco
775d6095bc
Merge pull request #16660 from fjmolinas/pr_lora_e5_dev
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boards/lora-e5-dev: initial support
2021-07-21 14:36:58 +02:00
Francisco Molina
c62f6e0590
cpu/stm32/flashpage: adapt to non dual-core stm32wl
2021-07-21 11:28:16 +02:00
Francisco Molina
8a8e023d04
cpu/stm32/wl: common subghz debug pin initialization
2021-07-21 11:28:15 +02:00
Francisco Molina
f2995240d4
cpu/stm32: handle parsing stm32wlex CPU_MODELs
2021-07-21 11:23:47 +02:00
benpicco
4f905bfa8c
Merge pull request #15493 from benpicco/riotboot-serial
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riotboot: implement serial flasher
2021-07-21 11:01:31 +02:00
Benjamin Valentin
a93deb4e95
cpu/stm32: usbdev: fix pm_layered include
2021-07-20 22:51:59 +02:00
aidiaz
5b9d8bd6c8
Update rtc_all.c for CPU_FAM_STM32L5 support.
2021-07-19 10:49:38 -04:00
José Alamos
934c875aba
Merge pull request #16579 from akshaim/pr/wl55jc_lorawan_final
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drivers/sx126x: Add support for Nucleo -WL55JC
2021-07-09 14:48:11 +02:00
Akshai M
f58a021f6d
cpu/stm32wl : Add HW Debug pins
2021-07-09 11:16:41 +02:00
Akshai M
a4bbf0cffc
cpu/stm32 : APB3 and VDDTCXO config
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Add APB3 disable, Enable VDDTCXO for Radio
2021-07-09 11:16:41 +02:00
Akshai M
f68dab9ccb
cpu/stm32: add GPIO_AF_UNDEF
2021-07-09 11:16:41 +02:00
Jose Alamos
97f20198a0
stm32/eth: avoid explicit cast to netdev
2021-07-09 10:38:35 +02:00
Akshai M
d3aa6ca00b
stm32/periph/spi : Add check for GPIO_UNDEF
2021-07-08 13:38:07 +02:00
MrKevinWeiss
02a2de4916
cpu/stm32: Add Kconfig dependency modeling
2021-07-02 15:11:05 +02:00
Francisco
52f5746904
Merge pull request #16545 from aidiaz/periph_rtt_l5
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cpu/stm32/periph/rtt_all: RTT peripheral support for CPU_FAM_STM32L5
2021-06-15 18:19:11 +02:00
aidiaz
fc1cd85c76
cpu/stm32/periph_rtt: RTT peripheral support for CPU_FAM_STM32L5
2021-06-15 09:49:55 -04:00
Rémy Grünblatt
deb8d34c43
cpu/stm32: Generate the irqs in a reproducible manner
2021-05-29 14:28:36 +02:00
Jean Pierre Dudey
5fd6daac3e
Merge pull request #16319 from jue89/fix/stm32-gpio_all-isr
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cpu/stm32/gpio_all: fix IRQ handler for G0/L5/MP1 families
2021-05-23 21:40:02 +02:00
Francisco
967cbcd7e1
Merge pull request #16478 from jue89/fix/stm32-gpio_f1-isr
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cpu/stm32/gpio_f1: fix IRQ handler
2021-05-19 08:55:04 +02:00
Hugues Larrive
1cf34afb76
cpu/stm32/periph/adc_f3.c: e-mail update
2021-05-15 05:53:45 +02:00
127d6853c7
cpu/stm32/gen_kconfig: use openpyxl package instead of xlrd
2021-05-01 11:31:56 +02:00
d39fd7c773
cpu/stm32/genkconfig: make copyright year configurable
2021-05-01 11:31:11 +02:00
benpicco
08f1f9768d
Merge pull request #16418 from fjmolinas/pr_stm32_spi_param_order
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cpu/stm32/periph/spi: fix wrong parameter order
2021-04-30 14:37:17 +02:00
Benjamin Valentin
d47a880915
cpu: add periph_rtt_overflow feature
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The RTT overflow callback is not available on all RTT implementations.
This means it is either a no-op or `rtt_set_overflow_cb()` is a no-op
or it will overwrite the alarm set with `rtt_set_alarm()`.
This adds a feature to indicate that proper overflow reporting is available.
2021-04-30 11:58:00 +02:00
Francisco Molina
fc9fc5c057
cpu/stm32/periph/spi: fix wrong parameter order
2021-04-30 09:17:38 +02:00
Benjamin Valentin
49585fc517
cpu/stm32: flashpage: use common helper functions
2021-04-27 16:52:37 +02:00
Akshai M
1f7a10305a
stm32/periph/flashpage: Reset cache
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Co-authored-by: Francisco <femolina@uc.cl>
2021-04-20 21:04:36 +02:00
Akshai M
efb86039c6
cpu/stm32wl: Add RTT support
2021-04-20 21:04:36 +02:00
Akshai M
2cf081b509
cpu/stm32wl: Flashpage configuration
2021-04-20 21:04:36 +02:00
Akshai M
df1cae172c
stm32/irqs: Adapt generators to support WL
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Co-authored-by: Alexandre Abadie <alexandre.abadie@inria.fr>
2021-04-20 21:04:36 +02:00
Akshai M
b816c67bdd
nucleo-wl55jc: Add Kconfig files
2021-04-20 21:04:35 +02:00
Akshai M
fd8ddd6161
boards: add nucleo-wl55jc
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Co-authored-by: Kevin "Tristate Tom" Weiss <weiss.kevin604@gmail.com>
2021-04-20 21:04:29 +02:00
Akshai M
c485c774cf
cpu/stm32: add stm32wl
2021-04-20 20:57:48 +02:00
Jue
80360e5308
cpu/stm32/gpio_f1: fix IRQ handler
2021-04-12 18:45:04 +02:00
Jue
2f503f11fa
cpu/stm32/gpio_all: fix IRQ handler for G0/L5/MP1 families
2021-04-12 17:01:33 +02:00
Francisco
700046238f
Merge pull request #16261 from maribu/cpu/stm32/periph_eth
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cpu/stm32/periph_eth: fix format specifier in DEBUG()
2021-04-07 09:32:09 +02:00
Francisco
e04dd4dcce
Merge pull request #16272 from jue89/fix/stm32_gpio_irq
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cpu/stm32/gpio: fix IRQ handler
2021-04-02 13:07:39 +02:00
Jue
43f83a520b
cpu/stm32/gpio: fix IRQ handler
2021-04-01 19:31:27 +01:00
Marian Buschsieweke
164aa72250
cpu/stm32/periph_eth: fix format specifier in DEBUG()
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Use PRIu32 instead of lu to make LLVM happy.
2021-03-31 10:11:46 +02:00
Karl Fessel
cf7078ab0a
stm32/ptp: avoid creating a new rounding rule
2021-03-29 16:27:27 +02:00
Marian Buschsieweke
28e6544748
Merge pull request #16236 from maribu/cpu/stm32/periph_eth
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cpu/stm32/periph_eth: bugfix
2021-03-28 09:20:15 +02:00
Marian Buschsieweke
7b08b97eb6
cpu/stm32/periph_eth: bugfix & cleanup
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Fix compilation with module `stm32_eth_link_up` when `stm32_eth_auto`
is not used by relying on the compiler to optimize unused functions
and variables out, rather than using the preprocessor.
2021-03-26 17:42:45 +01:00
Marian Buschsieweke
650559276f
cpu/stm32/periph_ptp: bugfix & better debug output
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- Clear the PTP timer interrupt *after* the user callback is executed
- Otherwise it would be possible that the ISR sets another super
short timeout that triggers during ISR, which also gets cleared
- This is a pretty nasty race condition :-/
- The debug output was a bit too verbose to be generally useful. Some
noise is now silenced unless `DEBUG_VERBOSE` is `#define`d to 1
2021-03-23 22:58:10 +01:00
Benjamin Valentin
dde3ca5f46
cpu/stm32: candev: derive number of CAN interfaces from vendor header
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We can deduce the number of available CAN interfaces from the vendor headers
so no need to hard-code this number for individual part numbers.
2021-03-09 11:30:21 +01:00
benpicco
b09f799038
Merge pull request #16161 from madokapeng/nucleo722ze_CAN_support
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boards/nucleo-f722ze: Add periph_can
2021-03-08 19:22:38 +01:00
madokapeng
905723be59
sys/include/can: Add loopback operation mode
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tests/candev: Add loopback mode for testing purpose
2021-03-08 12:13:15 -05:00
Marian Buschsieweke
ab89234040
drivers/periph/rtt: add periph_rtt_set_counter feature
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Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
2021-03-08 14:16:46 +01:00
madokapeng
a38cd1477e
boards/nucleo-f722ze: Add periph_can support
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cpu/stm32: Add CAN support for f722ze board
f722ze board has ONLY 1 CAN interface, fix compiling error which
treats f722xx has more than 1 CAN.
2021-03-05 23:22:44 -05:00
Marian Buschsieweke
b9cb75fedf
drivers/periph/rtt: add periph_rtt_set_counter feature
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Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
2021-03-04 18:05:06 +01:00
Marian Buschsieweke
720b350f6f
cpu/stm32: fix periph_rtt
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For some reason rtt_get_alarm was never implemented. This adds the
missing function.
2021-03-03 17:02:59 +01:00
Francisco
c91499997e
Merge pull request #16030 from benpicco/drivers/mtd_flashpage-fix_native
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drivers/mtd_flashpage: fixes for native (and stm32l0, stm32l4)
2021-02-23 15:12:06 +01:00
benpicco
d014f5e6d0
Merge pull request #14911 from OTAkeys/pr/can_stm32_deepsleep_opt
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stm32/can: add option to enable deep-sleep per device
2021-02-22 22:52:46 +01:00
Benjamin Valentin
2bdc5cf6d7
cpu/stm32: fix FLASHPAGE_ERASE_STATE for stm32l4
2021-02-18 14:22:11 +01:00
benpicco
77035d6df3
Merge pull request #15900 from benpicco/cpu/stm32f1-gpio_test_and_clear
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cpu/stm32: GPIO/f1: use bitarithm_test_and_clear()
2021-02-17 15:32:39 +01:00
Marian Buschsieweke
dbd241ef26
cpu/stm32/periph_ptp: update to new API
2021-02-10 10:09:26 +01:00
Francisco Molina
85caf7cbc7
drivers/flashpage: add FLASHPAGE_ERASE_STATE definition
2021-02-09 11:11:46 +01:00
b666b78602
Merge pull request #15914 from fjmolinas/pr_stm32_flashpage_fix_per
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cpu/stm32/flashpage: reset PER after erase
2021-02-03 10:21:04 +01:00
Francisco
3b2a55a923
Merge pull request #15865 from benpicco/pm_layered-default
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cpu: make pm_layered a DEFAULT_MODULE
2021-02-03 08:17:29 +01:00
Vincent Dupont
2edf37ed5b
cpu/stm32/can: use en_deep_sleep_wake_up by default
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Add en_deep_sleep_wake_up = true in default candev_conf in can_params.h
2021-02-02 15:39:27 +01:00
Vincent Dupont
eb0f6582c7
stm32/can: add option to enable deep-sleep per device
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Deep-sleep was based on using rx pin as external interrupt to be able to
wake up from stop mode. If rx pin cannot be used as interrupt or user
does not need to wake up from stop from the CAN, an option is now
present. If en_deep_sleep_wake_up is set to false, setting the device to
sleep simply unblock stop mode. Otherwise the behavior is unchanged.
2021-02-02 15:32:25 +01:00
Francisco Molina
3d68406c5b
cpu/stm32/flashpage: reset PER after erase
2021-02-02 11:42:09 +01:00
benpicco
837b55fc17
Merge pull request #15420 from bergzand/pr/stm32f4/flashpage_support
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stm32f{2,4,7}: Initial flashpage support
2021-02-01 19:23:51 +01:00
b6e80bf487
stm32f4: Initial flashpage support
2021-02-01 18:23:05 +01:00
benpicco
efd8afd3ab
Merge pull request #15899 from OTAkeys/pr/stm32-fix-exti
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cpu/stm32/gpio: fix EXTI flag clearing
2021-02-01 18:22:25 +01:00
Benjamin Valentin
a5c222d830
cpu/stm32: GPIO/f1: use bitarithm_test_and_clear()
2021-02-01 13:47:41 +01:00
Vincent Dupont
3e8e109e8b
cpu/stm32/gpio: fix EXTI flag clearing
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In case a non-gpio EXTI (>= 16) is pending, the isr_exti() used to clear
the flag and try to call a callback, which was out-of-bouds, thus
generating a hard fault.
This fixes it by masking the pending_isr variables with 0xFFFF.
2021-02-01 13:30:48 +01:00
118643ab2d
stm32: Resolve RAM size to bytes
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The ram size is exposed as macro value and available for use in code.
For the stm32 it has a value in kilobytes suffixed with 'k'. This is
less than optimal for usage in arithmetic. This commit modifies the
value to bytes so that it can be used in preprocessor magic
2021-02-01 10:53:40 +01:00
Benjamin Valentin
f12a82e4f9
cpu/stm32: use common pm_off() function
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The code is identical to the one found in sys/pm_layered/pm.c
2021-01-27 14:07:22 +01:00
Benjamin Valentin
9c1455d55f
cpu: make pm_layered a DEFAULT_MODULE
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Allow to disable pm_layered in the bootloader to save some ROM.
2021-01-27 13:21:20 +01:00
Marian Buschsieweke
62aa3d103f
cpu/stm32/periph_eth: RX Timestamps
2021-01-26 10:44:04 +01:00
87cd41a6d1
Merge pull request #15657 from aabadie/pr/cpu/stm32_merge_clock_headers
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cpu/stm32: merge clock source selection headers
2021-01-25 13:57:05 +01:00
49a3592f92
Merge pull request #15849 from benpicco/cpu/stm32f7-adc
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cpu/stm32: add periph_adc for STM32F7
2021-01-25 13:12:22 +01:00
5fef40ab5a
cpu/stm32/clk: cleanup common clock configuration
2021-01-25 11:46:35 +01:00
dfed1b0567
cpu/stm32: merge g0 and g4 clock configuration headers
2021-01-25 11:46:34 +01:00
0aadf367cc
cpu/stm32: rework common clock source selection header
2021-01-25 11:46:34 +01:00
Francisco
947c63666e
Merge pull request #15834 from leandrolanzieri/pr/cpu/stm32/kconfig_features_conflict_fix
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cpu/stm32/kconfig: fix rtt/rtc error symbol
2021-01-25 10:15:32 +01:00
AravindKarri
63252d17c0
cpu/stm32/adc_f4: add support for stm32f7
2021-01-24 22:30:49 +01:00
Leandro Lanzieri
e5aca465bd
cpu/stm32/kconfig: fix rtt:rtc error symbol
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It only exists conflict between the usage of RTC and RTT on the F1
family, but the error symbol was being set for all of them. This fixes
the issue.
2021-01-23 09:59:03 +01:00
benpicco
46337efd93
Merge pull request #15783 from maribu/stm32_eth_fix_error_handling
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cpu/stm32/periph_eth: fix error handling in send()
2021-01-22 20:25:25 +01:00
b1f7fd3905
cpu/stm32: fix wrong max clock for stm32f423xx line
2021-01-21 18:31:15 +01:00
Marian Buschsieweke
21264b80cf
cpu/stm32/periph_eth: improve debugging output
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Add ENABLE_DEBUG_VERBOSE flag, so that the noise during debugging can be
reduced. This is super helpful when testing under load, as otherwise there is
just too much noise in the output.
2021-01-20 10:36:59 +01:00
Marian Buschsieweke
788f997452
cpu/stm32/periph_eth: fix error handling
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An earlier version of periph_eth used to always pack the first chunk of the
outgoing frame to the first DMA descriptor by telling the DMA to jump back
to the first descriptor within the last descriptor. This worked fine unless
the frame was send in one chunk (as e.g. lwip does), which resulted due to a
hardware bug in a frame being send out twice. For that reason, the behavior was
changed to cycle throw the linked DMA descriptor list in round-robin fashion.
However, the error checking was not updated accordingly. Hence, the error
check might run over (parts of) unrelated frames and fail to detect errors
correctly.
This commit fixes the issue and also provides proper return codes for errors.
Additionally, an DMA reset is performed on detected errors during RX/TX. I'm
not sure if/when this is needed, as error conditions are neigh impossible to
produce. But better be safe than sorry.
2021-01-20 10:35:05 +01:00
e1941d8976
cpu/stm32f2f4f7: expose clock settings in Kconfig
2021-01-19 22:09:16 +01:00
Francisco Molina
7c12ea7416
cpu/stm32/rtc: add unlock/lock to rtc_clear_alarm
2021-01-19 13:33:17 +01:00
Sebastiaan de Schaetzen
6e90111eb9
stm32/periph/uart: set flow control bits before enabling uart
2021-01-12 07:37:19 +01:00
b13598cdc4
cpu/stm32: fix ENABLE_DEBUG definition
2021-01-08 14:37:33 +01:00
d027454ad4
cpu/stm32/kconfig: use depends on instead of if
2021-01-07 16:07:04 +01:00
e8a5493080
cpu/stm32: model MCO in Kconfig for l4/wb
2021-01-07 16:02:30 +01:00
0e39c2ba17
cpu/stm32: model MCO in Kconfig for l0/l1
2021-01-07 16:02:29 +01:00
a9b154b4ac
cpu/stm32: model MCO in Kconfig for g0/g4
2021-01-07 16:02:29 +01:00
1f0e6c1057
cpu/stm32: model MCO in Kconfig for f0/f1/f3
2021-01-07 16:02:29 +01:00
5e719816d2
cpu/stm32/kconfigs: select cpu fam/lines without mco prescaler
2021-01-07 16:02:29 +01:00
048e8446ef
cpu/stm32f0: remove old clock configuration header
2020-12-17 08:38:40 +01:00
45c2b19f25
cpu/stm32: merge f0f1f3 clock configuration headers
2020-12-17 08:38:40 +01:00
8f6005b26e
boards: cpu: stm32f1: use .config for specific iotlab PLL_PREDIV
2020-12-08 18:02:57 +01:00
c68f63b318
cpu/stm32f1f3: handle custom pll prediv/mul at cpu level
2020-12-08 17:36:52 +01:00
0f23c875a2
cpu/stm32: adapt Kconfig clock configuration for f1/f3
2020-12-08 17:36:51 +01:00
benpicco
a80631a297
Merge pull request #15074 from maribu/ptp-clock
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drivers/periph/ptp_clock
2020-12-03 09:59:07 +01:00
Marian Buschsieweke
ea3752db77
cpu/stm32: Added PTP clock implementation
2020-12-02 17:53:00 +01:00
b0b19203a7
Merge pull request #15190 from benpicco/boards/wefun-f401cc
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boards/common/weact-f4x1cx: create common WeAct boards
2020-12-01 12:03:38 +01:00
Benjamin Valentin
0ed34cdb4d
cpu/stm32: periph_eth: drop addr from eth_conf_t
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MAC address is now supplied by EUI provider, no need to hard-code
it for the board.
2020-11-29 23:11:14 +01:00
Benjamin Valentin
a28a60f16c
cpu/stm32: periph_eth: register with netdev
2020-11-29 23:10:37 +01:00
3f0ea86963
cpu/stm32/include/periph_cpu.h: add missing limits.h include
2020-11-23 16:56:34 +01:00
81c270dc1b
stm32/flashpage: Remove page address casts from erase
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This removes the redefinitions of the page address in the erase
function.
2020-11-18 12:30:40 +01:00
aebf6f06d8
stm32/flashpage: Add common stm32_flashpage_block_t type
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This commits adds a common type for the block writes to the flash of the
stm32. Depending on the family, the type has a different size. This
allows the removal of a number of ifdefs to track the differences
between families, simplifying the flashpage code
2020-11-18 12:04:57 +01:00
Leandro Lanzieri
5a04f94b63
Merge pull request #14967 from aabadie/pr/boards/stm32f0_clock_kconfig_only
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boards/stm32f0: add Kconfig for clock configuration
2020-11-17 12:14:10 +01:00
Gilles DOFFE
e4fa203db4
cpu/stm32: STM32MP1 family has no flash
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Then CPU_FLASH_BASE cannot be defined as FLASH_BASE does not exist.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
5ec5b335f1
cpu/stm32: add Kconfig files for STM32MP157CAC model
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Note that Kconfig.models was not generated with gen_kconfig.py tool
due to lack of ProductsList.xlsx file for STM32MP1 family.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
ce0ef8939c
cpu/stm32: disable periph_wdt for mp1 family
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In STM32MP1 family, independant watchdogs (IWDG1 and IWDG2) are
dedicated to the MPU (Cortex-A7). Thus simply disable the feature
for STM32MP1 family.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
2ac0467807
cpu/stm32: configure timer2 for stm32mp1 boards
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This timer will be used by RIOT-OS as the scheduling timer for
stm32mp157c-dk2 board.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
504fba61b8
cpu/stm32: add uart support for stm32mp1
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stm32mp1 family uart driver is the same than for other stm32 families.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
ec97eb8447
cpu/stm32: set CPU_LINE for stm32mp157c
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Set CPU_LINE variable according to informations extracted from
stm32_info.mk.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
7b7a75c3ca
cpu/stm32: setup memory length for stm32mp157x
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The stm32mp157c has the particularity to not having flash memory but
only SRAM.
Thus a part of SRAM must be considered as a ROM to flash the firmware
into.
In case of the stm32mp157c, the RETRAM (64kB) is used as ROM and the
4 banks of SRAM (384kB) are used as RAM.
However, as ROM_LEN, RAM_LEN, ROM_START_ADDRESS, RAM_START_ADDRESS and
ROM_OFFSET could be overloaded by user, set them with "?=" operator.
If the ROM_START_ADDRESS and the RAM_START_ADDRESS are not set at the
end of that file, it is a classic stm32 MCU with flash, thus set this
variables with common memory addresses for stm32 MCU family:
ROM_START_ADDR ?= 0x08000000
RAM_START_ADDR ?= 0x20000000
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
4bfbb75578
cpu/stm32: add stm32mp1_eng_mode pseudomodule
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In Engineering mode (BOOT0 off and BOOT2 on), only the Cortex-M4
core is running. It means that all clocks have to be setup
by the Cortex-M4 core.
In other modes, the clocks are setup by the Cortex-A7 and then should
not be setup by Cortex-M4.
stm32mp1_eng_mode pseudomodule have to be used in Engineering mode
to ensure clocks configuration with IS_USED(MODULE_STM32MP1_ENG_MODE)
macro.
This macro can also be used in periph_conf.h to define clock source
for each peripheral.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
3008574d0e
cpu/stm32: remove uneeded pm macro tests
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STM32_PM_STOP and STM32_PM_STANDBY are always defined in periph_cpu.h,
Thus it is not needed to test them.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
6bac94fb6d
cpu/stm32: setup power management for stm32mp1
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According to stm32mp157 documentation:
* "The CStop mode is entered for MCU when the SLEEPDEEP bit in the Cortex®-M4 System Control
register is set." Thus set PM_STOP_CONFIG to 0.
* "The CStandby mode applies only to the MPU sub-system."
Set PM_STANDBY_CONFIG to (0) and do not enter standby mode for
stm32mp1.
As PM_STOP_CONFIG is already defined before for CPU_FAM_STM32WB, replace
it with CPU_FAM_STM32MP1.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
e9a6b448cf
cpu/stm32: add gpio support for stm32mp1 family
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stm32mp1 is configuring gpio slightly differently that common stm32:
* port_num is computed differently, thus test MCU family to apply
the good calculation.
* Rising and falling edge state on interrupts. Do not test if falling
or rising edge, just launch the callback in all cases.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
be2c0ae179
cpu/stm32: define CPU_IRQ_NUMOF for stm32mp157cac
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This MCU has 150 interrupt vectors.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
91a12c200c
cpu/stm32: do not retrieve cmsis headers
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Normally, CMSIS headers are retrieved as package from ST git repository
for each stm32.
However stm32mp1 family does not have a CMSIS headers repository but
have been included into RIOT source code in a previous commit.
For stm32mp1, CMSIS headers package must then not be retrieved and
vectors have to be generated from already in-source CMSIS headers.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
d6400c77de
cpu/stm32: include stm32mp1 vendor headers
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Include stm32mp1 vendors header. CORE_CM4 must be defined to include
Cortex-M4 core headers.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
169097ac21
cpu/stm32: add stm32mp157x vendor headers
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Add vendor CMSIS headers from STMicroelectronics:
https://wiki.st.com/stm32mpu/wiki/STM32CubeMP1_architecture#CMSIS
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
e6aef8f626
cpu/stm32: get info from stm32mp1 cpu model
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stm32mp1 ordering informations are not the same than classical
single MCU.
And as stm32mp1 has no flash, just extract second part of model name
and pincount.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
c3e29bb1fa
cpu/stm32: setup clocks for stm32mp1
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As stm32mp1 clocks are not configured like for other stm32, do not use
stmclk_common.c
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
d173097d7f
cpu/stm32: do not build bootloader for mp1
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The stm32mp1 family has no flash. The firmware is loaded directly in
RAM by stlink programmer or by Cortex-A7 bootloader/OS.
Thus bootloader is useless for this family, disable it.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
4f0fd9cf95
cpu/stm32: add GPIO_PIN macro for stm32mp1 family
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As stm32mp1 family accesses gpio pins with a different
offset than other stm32, create a specific macro.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
bdc1cce04d
cpu/stm32: enable MPU for stm32mp1
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stm32mp1 family has a MPU (Memory Processing Unit).
Thus adds the feature.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
8279e54272
cpu/stm32: add clock configuration for stm32mp1
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Configure stm32mp1 Cortex-M4 MCU core clock according to board
configuration.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
d78e13e906
cpu/stm32: add stm32mp1 support to clk_conf
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clk_conf is a useful tool to produce clock headers for new boards.
But it only supports STM32Fx families.
This commits add the definition of a new family: STM32MP1.
Only the STM32MP157 is supported for now.
First build clk_conf:
$ make -C cpu/stm32/dist/clk_conf/
Clock header can be generated with the following command once clk_conf is
built:
$ cpu/stm32/dist/clk_conf/clk_conf stm32mp157 208000000 24000000 1
This command line will produce a core clock of 208MHz with a 24MHz HSE
oscillator and will use LSE clock which corresponds to the STM32MP157C-DK2
board configuration.
The command will output the header to copy paste into the periph_conf.h of
the board:
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 209MHz */
#define CLOCK_CORECLOCK (208000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (24000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_MCU_DIV RCC_MCUDIVR_MCUDIV_1 /* max 209MHz */
#define CLOCK_MCU (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_APB1DIVR_APB1DIV_2 /* max 104MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_APB2DIVR_APB2DIV_2 /* max 104MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB3_DIV RCC_APB3DIVR_APB3DIV_2 /* max 104MHz */
#define CLOCK_APB3 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (2)
#define CLOCK_PLL_N (52)
#define CLOCK_PLL_P (3)
#define CLOCK_PLL_Q (13)
/** @} */
This result has been verified with STM32CubeMX, the official ST tool.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
5e30e60fec
cpu/stm32: avoid configuring stm32mp1 APB1 clock
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APB1 bus clock is always enabled is not manageable by RCC register.
So avoid enabling it.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
7a2550da9b
cpu/stm32: add stm32mp1 peripheral busses
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Add stm32mp1 peripheral busses AHB1, AHB2, AHB3 and AHB4 with
enable/disable functions.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
67f37950a0
cpu/stm32: default i2c configuration
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* Setup i2c speed to I2C_SPEED_LOW by default
* enable i2c_write_regs() function.
* i2c frequency needs to be specified into board periph_conf.h
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
f39aa979af
cpu/stm32: setup CLOCK_LSI for stm32mp1
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Set stm32mp1 family LSI clock frequency to 32KHz as specified in datasheet.
STM32MP157C example:
https://www.st.com/resource/en/datasheet/stm32mp157c.pdf
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
ba5f8e1cda
cpu/stm32: consider starting white spaces in gen_vectors.py
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In some CMSIS headers, "typedef enum" could be preceded by white
spaces. Thus consider them when parsing the line.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
1c063a74ea
stm32: Adapt to flashpage/flashpage_pagewise API
2020-11-11 23:16:42 +01:00
9d13c07e92
cpu/stm32f0: handle custom pll prediv/mul at cpu level
2020-11-10 15:55:38 +01:00
5d77b7d90d
cpu/stm32: show PLL params in menuconfig with CUSTOM_PLL_PARAMS
2020-11-10 14:53:37 +01:00
03ee0c938f
cpu/stm32: adapt Kconfig clock configuration for f0
2020-11-10 14:53:12 +01:00
2f2622c76f
cpu/stm32: move stm32l5 default PLL N to cpu
2020-11-10 09:34:07 +01:00
36d33d38f7
cpu/stm32: move stm32l4+ default PLL N to cpu
2020-11-10 09:34:07 +01:00
ef5897775d
cpu/stm32l4wb: add missing define for PLL HSI source
2020-11-10 09:34:07 +01:00
934028c114
cpu/stm32: fix l4l5wb clock configuration
...
Default values were wrong for WB when using HSE 32MHz as PLL input source
Default PLL input source was wrong when not using HSE and the board
provides an HSE
2020-11-10 09:34:07 +01:00
f111fd8447
cpu/stm32/kconfig.clk: adapt for l4/l5/wb
2020-11-10 09:34:06 +01:00
d2a46f58c2
stm32/flashpage: use void pointer for flash address
2020-11-09 14:28:42 +01:00
Francisco
aa79f4da17
Merge pull request #15078 from aabadie/pr/cpu/stm32f0f1f3_mco
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cpu/stm32f0f1f3: add MCO configuration and initialization
2020-11-06 08:56:43 +01:00
afba298bc1
cpu/stm32f0f1f3: configure and initialize MCO
2020-11-05 21:59:00 +01:00
565242f67e
Merge pull request #15073 from aabadie/pr/cpu/stm32l0l1_mco
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cpu/stm32l0l1: add MCO configuration and initialization
2020-11-05 17:03:32 +01:00
f98f5f5b49
Merge pull request #15084 from aabadie/pr/cpu/stm32gx_mco
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cpu/stm32gx: add MCO configuration and initialization
2020-11-05 16:46:04 +01:00
Benjamin Valentin
a90016740c
cpu/stm32/clk/f2f4f7: add config for 25 MHz HSE
2020-11-05 15:46:11 +01:00
5a2409557f
cpu/stm32gx: configure and initialize MCO
2020-11-05 13:39:19 +01:00
4b316c593a
cpu/stm32l0l1: configure MCO
2020-11-05 13:37:34 +01:00
18b5f417d1
cpu/stm32l4: implement MCO configuration
2020-11-05 13:34:45 +01:00
daa7ed54cd
Merge pull request #15000 from aabadie/pr/boards/stm32l0l1_clock_kconfig_only
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boards/stm32l0l1: model clock configuration in kconfig
2020-11-03 17:20:00 +01:00
fb35edd22d
cpu/stm32: adapt clock configuration for l0/l1
2020-11-03 14:23:46 +01:00
Leandro Lanzieri
500cf238b8
cpu/stm32/vendor: use submake to fetch CMSIS headers
2020-11-03 13:33:16 +01:00
Marian Buschsieweke
125c892c03
drivers/periph/timer: Use uint32_t for frequency
...
For all currently supported platforms `unsigned long` is 32 bit in width. But
better use `uint32_t` to be safe.
2020-10-30 22:02:12 +01:00
7fbfb92f03
boards/stm32gx: move Kconfig clock config to cpu
2020-10-29 23:00:44 +01:00
Marian Buschsieweke
45dc86acce
cpu/stm32: Fix reception bug in periph_eth
...
The reception code hands RX DMA descriptors back to the DMA right after its
contents were copied into the network stack internal buffer. This increases
the odds that the DMA never runs out of DMA descriptors to fill, even under
high load. However, the loop fetching the Ethernet frame stops to iterate at the
end of the frame. If the DMA used one more descriptor to store the FCS, this
was not returned back to the DMA. This commit fixes it.
2020-10-28 14:23:25 +01:00
Marian Buschsieweke
7ced6a8ac8
cpu/stm32: Improve debug output for periph_eth
2020-10-28 14:22:54 +01:00
benpicco
2050193030
Merge pull request #15273 from aabadie/pr/cpu/stm32_clk_cfg_in_cpu
...
boards/stm32: cpu/stm32: move clock configuration from boards to cpu
2020-10-27 10:04:01 +01:00
0bd70a46bc
cpu/stm32: rework clock configuration documentation
2020-10-27 08:54:09 +01:00
ec5b47fc61
cpu/stm32l4+/wb: centralize max core clock define, adapt related boards
2020-10-27 08:44:55 +01:00
05f67a0a00
cpu/stm32: remove useless include in clock configuration
2020-10-26 11:21:07 +01:00
d6d85a3370
cpu/stm32: add common clock configuration header
2020-10-26 11:21:07 +01:00
f2e2c89424
cpu/stm32: move clock configuration headers to cpu
2020-10-26 11:16:23 +01:00
4e50feb4a8
cpu/stm32: adapt Kconfig for stm32l5
2020-10-23 18:28:27 +02:00
bd24a71fe0
cpu/stm32/kconfig: create family directory if not exist
2020-10-23 18:21:51 +02:00
7f26d5c389
cpu/stm32l5: adapt flashpage periph
2020-10-23 18:21:50 +02:00
a416b2793f
cpu/stm32: add basic support for stm32l5
2020-10-23 18:21:50 +02:00
b1b6c33104
cpu/stm32/dist/irqs: adapt for stm32l5
2020-10-23 18:13:07 +02:00
02c4b05a5a
cpu/stm32: configure stm32l5 cmsis repository version
2020-10-23 18:13:07 +02:00
benpicco
ad294aa340
Merge pull request #15203 from maribu/stm32-eth-negotiate
...
cpu/stm32: periph_eth: Use auto-negotation
2020-10-23 14:22:56 +02:00
Bas Stottelaar
7eb3414cff
cpu/*: remove unneeded ENABLE_DEBUG
2020-10-23 11:29:57 +02:00
Bas Stottelaar
22243aec7a
cpu/*: realign ENABLE_DEBUG
2020-10-23 00:46:26 +02:00
Bas Stottelaar
bd34cf8fc0
cpu/*: reorder ENABLE_DEBUG after last include
2020-10-23 00:45:55 +02:00
Marian Buschsieweke
5f9b55a182
cpu/stm32: Add stm32_eth_auto for auto-negotiation
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Expose the auto-negotiation feature of the Ethernet device via the
pseudo-module stm32_eth_auto. With this enabled, the static speed configuration
set in the boards periph_conf.h will only be used if the PHY lacks
auto-negotiation capabilities - which is unlikely to ever happen.
2020-10-22 12:37:23 +02:00
Bas Stottelaar
ab6188cea3
cpu/*: add missing include of assert.h
2020-10-22 11:13:08 +02:00
72c17588b9
boards/stm32: remove unused CLOCK_LSE define
2020-10-21 12:11:17 +02:00
9f985e8e56
cpu/stm32: use CONFIG_BOARD_HAS_LSE instead of CLOCK_LSE
2020-10-21 12:10:53 +02:00
fed1c4dbbe
Merge pull request #15259 from aabadie/pr/cpu/stm32_cleanup_disable_hsi
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cpu/stm32: simplify stmclk_disable_hsi function
2020-10-21 11:19:30 +02:00
84306f1122
cpu/stm32: remove unused CLOCK_HSE define
2020-10-21 10:11:46 +02:00
0480490a2b
cpu/stm32/dist: adapt gen_kconfig.py with new directory
2020-10-21 09:18:30 +02:00
2720c5526c
cpu/stm32: rename kconfig directory to kconfigs
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The kconfig directory names clashes with Kconfig file on non case sensitive filesystems
2020-10-21 09:18:24 +02:00
42f71914a5
cpu/stm32: simplify stmclk_disable_hsi function
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There is no need to check for CLOCK_HSE or to check if HSI is used as SYSCLK, this is already checked at compile time in the clock initialization code
2020-10-20 22:13:50 +02:00
2f053c90bd
cpu/stm32gx: improve clock initialization sequence
2020-10-20 15:47:21 +02:00
e2ae50258a
cpu/stm32gx: factorize HSE clock activation
2020-10-20 14:29:22 +02:00
2d603269dd
cpu/stm32gx: disable hsi only if unused
2020-10-20 14:29:11 +02:00
20894e47a6
cpu: boards: stm32gx: use IS_ACTIVE macro for clock config
2020-10-20 14:29:11 +02:00
a96ca57f66
cpu/stm32gx: remove useless LSE clock initialization
2020-10-20 14:29:11 +02:00
d78a316139
cpu: boards: stm32gx: compile code for all possible clock modes
2020-10-20 14:29:11 +02:00
d1724d6718
cpu/stm32l4: correctly handle clock freq > 80MHz
2020-10-20 11:37:46 +02:00
00ea7ffa55
cpu/stm32l4wb: cleanup clock initialization
2020-10-20 11:37:46 +02:00
d7d5d9d651
boards/stm32l4: extend clock configuration
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- add PLLQ default value
- better tune default PLLM value depending on HSE value
- ensure CLOCK_PLL_SRC is always defined
2020-10-20 11:37:45 +02:00
b11d65ab70
cpu/stm32l4: enable PLLQ as 48MHz source if possible
2020-10-20 11:37:45 +02:00
58ad0168e7
cpu/stm32: stm32l011 lines doesn't provide hwrng
2020-10-15 16:24:33 +02:00
2e2b87dda5
cpu/stm32: define EEPROM size for stm32l011k4
2020-10-15 16:24:33 +02:00
e51279b228
cpu/stm32l0: fix clk control register reset
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on stm32l011, RCC_CR_CSSON is not defined
2020-10-15 16:24:33 +02:00
044acf1175
cpu/stm32: enable power overdrive on f4 and f7
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This is only enabled if the HCLK clock is above 168MHz on F4 and 180MHz on f7
2020-10-14 13:36:20 +02:00
Cenk Gündoğan
0741f161ae
Merge pull request #15198 from leandrolanzieri/pr/kconfig/add_error_symbols
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Kconfig: add error symbols and makefile check
2020-10-13 13:09:42 +02:00
Marian Buschsieweke
d84caa50d2
cpu/stm32: Fix link status in periph_eth
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Previously, only an link-up event was triggered, not an link down event. And
additionally, once the link-up event was sent, the link status was no longer
monitored. As a result, once a link-up was sent, no further link event were
triggered.
2020-10-12 14:53:41 +02:00
Marian Buschsieweke
6294382627
cpu/stm32: Use mii.h for periph_eth
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Use shared MII definitions and utilities instead own definitions.
2020-10-12 08:46:20 +02:00
benpicco
94e78cd1dd
Merge pull request #15193 from maribu/stm32_eth_fix
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cpu/stm32: Fix & cleanup periph_eth
2020-10-11 21:40:36 +02:00
Marian Buschsieweke
0e43c927b1
cpu/stm32: Fix/cleanup periph_eth
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The methods to read from / write to MII registers had an address argument to
allow specifying the PHY to communicate with. However, only a single PHY is
available on all boards supported and the driver is not able to operate with
multiple PHYs anyway - thus, drop this parameter for ease of use.
This fixes a bug in the _get_link_status() function, which used hard coded the
address 0; which might not be correct for all boards.
2020-10-09 20:20:54 +02:00
Leandro Lanzieri
fe6d66d92a
kconfig: add ERROR symbol for conflicting modules
2020-10-09 18:04:17 +02:00
42067b0091
cpu/stm32/kconfig: restore features provided at cpu lines level
2020-10-09 12:39:22 +02:00
87f2f7ab99
cpu/stm32wb: extend Kconfig cpu lines and models
2020-10-09 12:39:22 +02:00
85a3167e4f
cpu/stm32l4: extend Kconfig cpu lines and models
2020-10-09 12:39:22 +02:00
841f500477
cpu/stm32l1: extend Kconfig cpu lines and models
2020-10-09 12:39:22 +02:00
11f3f2de74
cpu/stm32l0: extend Kconfig cpu lines and models
2020-10-09 12:39:22 +02:00
e8479b8cb5
cpu/stm32g4: extend Kconfig cpu lines and models
2020-10-09 12:39:22 +02:00
f223516a39
cpu/stm32g0: extend Kconfig cpu lines and models
2020-10-09 12:39:22 +02:00
7a510c08ff
cpu/stm32f7: extend Kconfig cpu lines and models
2020-10-09 12:39:22 +02:00
1c63b79a6d
cpu/stm32f4: extend Kconfig cpu lines and models
2020-10-09 12:39:21 +02:00
2c0930a3e7
cpu/stm32f3: extend Kconfig cpu lines and models
2020-10-09 12:39:21 +02:00
3d0c91d486
cpu/stm32f2: extend Kconfig cpu lines and models
2020-10-09 12:39:21 +02:00
3c08d564eb
cpu/stm32f1: extend Kconfig cpu lines and models
2020-10-09 12:39:21 +02:00
2490e01445
cpu/stm32f0: extend Kconfig cpu lines and models
2020-10-09 12:39:21 +02:00
06c3361a15
cpu/stm32/dist: add generator for kconfig cpu lines and models
2020-10-09 12:39:21 +02:00
Marian Buschsieweke
7b4d4c198b
cpu/stm32/periph_eth: Code style
2020-10-08 11:46:39 +02:00
Marian Buschsieweke
ab30865a08
cpu/stm32: Cleanup periph_eth
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Cleanup functions _rw_phy(), _phy_read(), and _phy_write() and rename them to
_mii_reg_{access,read,write}().
2020-10-08 11:46:39 +02:00
3e1fa30c2f
cpu/stm32/irqs: fix vectors generator script
2020-10-08 08:09:31 +02:00
benpicco
2289a188ed
Merge pull request #15164 from maribu/stm32-eth-fix-link-status
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cpu/stm32: Fix periph_eth link status
2020-10-06 23:46:34 +02:00
4613f840f4
cpu/stm32: put GPIO in ain before initializing the clocks
2020-10-06 16:10:05 +02:00
0d786e3dbb
cpu: boards: stm32f2/f4/f7: rework clock configuration and init
2020-10-06 16:10:05 +02:00
Marian Buschsieweke
7b738a66c4
cpu/stm32: Fix periph_eth link status
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The link status was previously not returned via the value parameter, as required
by the netdev_driver_t API. As a result, e.g. the `ifconfig` shell command
showed garbage.
2020-10-06 10:29:38 +02:00
Marian Buschsieweke
7920d32e32
cpu/stm32: Clean up periph_eth
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Use `addr` instead of `mac` when referring to L2 address.
2020-10-05 16:03:47 +02:00
7159fa03fc
Merge pull request #15119 from hugueslarrive/adc_f3
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cpu/stm32/periph/adc_f3: add ADC3 and ADC4 management
2020-10-01 17:00:00 +02:00
hugues
3d6b473cd7
cpu/stm32/adc_f3: improve peripheral driver
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- fix clock enable/disable bitfields
- add management for ADC3 and ADC4
- improve calibration
2020-10-01 11:08:45 +02:00
Francisco
b5c51d244e
Merge pull request #14909 from OTAkeys/pr/conn_can_clean_up
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can: add proper checks for ifnum validity
2020-10-01 09:22:28 +02:00
Vincent Dupont
590f07b38a
stm32/can: fix features dependency
2020-09-30 12:59:03 +02:00
40262c1b7a
cpu/stm32: reorganize Kconfig files per families
2020-09-30 10:31:38 +02:00
1e6a336227
cpu/stm32/Kconfig: move features declared in models to lines
2020-09-30 10:31:29 +02:00
8738bd5e5c
cpu/stm32: select lines from models in Kconfig
2020-09-30 10:31:29 +02:00
d1bab4a25f
cpu/stm32: add Kconfig config for all cpu lines
2020-09-30 10:31:29 +02:00
ba4edb3c63
cpu/stm32: split main Kconfig
2020-09-30 10:31:29 +02:00
e8c79e7a41
cpu/stm32: extend CPU_LINES for G4 and L1
2020-09-30 10:31:29 +02:00
cada451383
cpu/stm32: document info extracted from CPU model name
2020-09-30 10:31:28 +02:00
d407878bc5
Merge pull request #15112 from aabadie/pr/boards/nucleo64-g431kb
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boards/nucleo-g431rb: add initial support
2020-09-29 15:26:39 +02:00
Francisco
109012b194
Merge pull request #14923 from aabadie/pr/boards/stm32f0f1f3_clock_kconfig
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boards/stm32f1/f3: rework clock initialization and configuration
2020-09-29 14:30:58 +02:00
ef742cddb2
cpu/stm32: add support for stm32g431rb
2020-09-29 12:26:26 +02:00
2c6693d68e
Merge pull request #14863 from hugueslarrive/nucleo-f302r8
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boards/nucleo-f302r8: add ADC feature
2020-09-29 10:45:40 +02:00
2d80bbf7b9
Merge pull request #15109 from aabadie/pr/make/features_bootloader_stm32_cleanup
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cpu/stm32: cleanup bootloader_stm32 build system management
2020-09-29 10:45:27 +02:00
ef864bba39
cpu/stm32: only build bootloader when the module is loaded
2020-09-28 21:07:01 +02:00
1259a89acf
cpu/stm32: remove useless bootloader dependency resolution
2020-09-28 21:07:01 +02:00
42728db45b
cpu/stm32: fix logical bug when getting l0/g0 CPU_CORE
2020-09-28 17:04:54 +02:00
hugues
9c41e25fff
cpu/stm32/periph/adc_f3: fix for devices which have only one ADC
2020-09-28 10:29:53 +02:00
84f1a70b7f
cpu/stm32/rtt: adapt for stm32g0
2020-09-25 15:20:14 +02:00
25e1fec90c
cpu/stm32: add support for stm32g071rb
2020-09-25 13:08:07 +02:00
da9168c652
cpu/stm32: rename stmclk_fx to stmclk_f2f4f7
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This commit also removes all f0/f1/f3 specific code from this file
2020-09-24 11:27:24 +02:00
042a550f0d
boards: cpu: stm32f1/f3: rework clock configuration and init
2020-09-24 11:27:24 +02:00
c14d7ec7db
cpu/stm32l0l1: refactor clock initialization sequence
2020-09-22 22:30:20 +02:00
425a2f69a2
cpu/stm32l0l1: ensure PLL is enabled when required
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PLL is required for the 48MHz output used by HWRNG and also when it's used as system clock
2020-09-22 22:30:20 +02:00
