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Merge pull request #15657 from aabadie/pr/cpu/stm32_merge_clock_headers

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cpu/stm32: merge clock source selection headers
This commit is contained in:
Alexandre Abadie 2021-01-25 13:57:05 +01:00 committed by GitHub
commit 87cd41a6d1
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GPG Key ID: 4AEE18F83AFDEB23
23 changed files with 296 additions and 716 deletions
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2
boards/nucleo-f722ze/include/periph_conf.h
View File

@ -30,7 +30,7 @@
#endif
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_216.h"
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

2
boards/nucleo-f746zg/include/periph_conf.h
View File

@ -30,7 +30,7 @@
#endif
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_216.h"
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

2
boards/stm32f723e-disco/include/periph_conf.h
View File

@ -33,7 +33,7 @@
#define CLOCK_HSE MHZ(25)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_216.h"
#include "clk_conf.h"
#include "cfg_rtt_default.h"
#include "cfg_usb_otg_fs.h"

2
boards/stm32f769i-disco/include/periph_conf.h
View File

@ -33,7 +33,7 @@
#define CLOCK_HSE MHZ(25)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_216.h"
#include "clk_conf.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
#include "cfg_usb_otg_fs.h"

37
cpu/stm32/include/clk/f2f4f7/cfg_clock_common.h → cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1.h
View File

@ -13,22 +13,22 @@
* @{
*
* @file
* @brief Base STM32F4 clock configuration
* @brief Base STM32Fx/Gx/MP1 clock configuration
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef CLK_F2F4F7_CFG_CLOCK_COMMON_H
#define CLK_F2F4F7_CFG_CLOCK_COMMON_H
#ifndef CLK_CFG_CLOCK_COMMON_FX_GX_MP1_H
#define CLK_CFG_CLOCK_COMMON_FX_GX_MP1_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock common configuration
* @name Clock common configuration (F0/F1/F2/F3/F4/F7/G0/G4/MP1)
* @{
*/
/* Select the desired system clock source between PLL, HSE or HSI */
@ -40,14 +40,6 @@ extern "C" {
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
@ -63,23 +55,28 @@ extern "C" {
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32MP1)
#define CLOCK_HSE MHZ(24)
#else
#define CLOCK_HSE MHZ(8)
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 0
#endif
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
#define CLOCK_HSI MHZ(8)
#elif defined(CPU_FAM_STM32MP1)
#define CLOCK_HSI MHZ(64)
#else
#define CLOCK_HSI MHZ(16)
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CLK_F2F4F7_CFG_CLOCK_COMMON_H */
#endif /* CLK_CFG_CLOCK_COMMON_FX_GX_MP1_H */
/** @} */

91
cpu/stm32/include/clk/cfg_clock_common_lx_wb.h Normal file
View File

@ -0,0 +1,91 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief Base STM32Lx/WB clock configuration
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef CLK_CFG_CLOCK_COMMON_LX_WB_H
#define CLK_CFG_CLOCK_COMMON_LX_WB_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration (L0/L1/L4/L5/WB)
* @{
*/
/* Select the desired system clock source between PLL, HSE or HSI */
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use MSI as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CLOCK_HSE
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#define CLOCK_HSE MHZ(24)
#else
#define CLOCK_HSE MHZ(8)
#endif
#endif
#define CLOCK_HSI MHZ(16)
#ifndef CONFIG_CLOCK_MSI
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#define CONFIG_CLOCK_MSI KHZ(4194)
#else
#define CONFIG_CLOCK_MSI MHZ(48)
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* CLK_CFG_CLOCK_COMMON_LX_WB_H */
/** @} */

17
cpu/stm32/include/clk/clk_conf.h
View File

@ -22,16 +22,25 @@
#include "kernel_defines.h"
#include "macros/units.h"
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32MP1)
#include "cfg_clock_common_fx_gx_mp1.h"
#else /* CPU_FAM_STM32L0 || CPU_FAM_STM32L1 || CPU_FAM_STM32L4 ||
* CPU_FAM_STM32L5 || CPU_FAM_STM32WB */
#include "cfg_clock_common_lx_wb.h"
#endif
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
#include "f0f1f3/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7)
#include "f2f4f7/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32G0)
#include "g0/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32G4)
#include "g4/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4)
#include "g0g4/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#include "l0l1/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \

47
cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h
View File

@ -31,58 +31,13 @@ extern "C" {
#endif
/**
* @name Clock settings
* @name F0/F1/F3 clock settings
* @{
*/
/* Select the desired system clock source between PLL, HSE or HSI */
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(8)
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(32))
#error "HSE clock frequency must be between 4MHz and 32MHz"
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 0
#endif
#define CLOCK_HSI MHZ(8)
/* The following parameters configure:
- on F0: a 48MHz system clock with HSI (or default HSE) as input clock
On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is

30
cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h
View File

@ -46,6 +46,36 @@
#error "No clock configuration available for this family"
#endif
/**
* @name Clock values
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q)
#define CLOCK_AHB CLOCK_CORECLOCK
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV)
#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV)
/** @} */
#ifdef __cplusplus
extern "C" {
#endif

12
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
View File

@ -23,8 +23,6 @@
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -86,15 +84,13 @@ extern "C" {
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(100)
#error "SYSCLK cannot exceed 100MHz"
#endif
#ifdef __cplusplus
}
#endif
#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H */
/** @} */

12
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h
View File

@ -23,8 +23,6 @@
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -64,15 +62,13 @@ extern "C" {
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(120)
#error "SYSCLK cannot exceed 120MHz"
#endif
#ifdef __cplusplus
}
#endif
#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H */
/** @} */

12
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
View File

@ -23,8 +23,6 @@
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -98,15 +96,13 @@ extern "C" {
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(180)
#error "SYSCLK cannot exceed 180MHz"
#endif
#ifdef __cplusplus
}
#endif
#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H */
/** @} */

12
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h
View File

@ -23,8 +23,6 @@
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -73,15 +71,13 @@ extern "C" {
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(216)
#error "SYSCLK cannot exceed 216MHz"
#endif
#ifdef __cplusplus
}
#endif
#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H */
/** @} */

12
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h
View File

@ -23,8 +23,6 @@
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -73,15 +71,13 @@ extern "C" {
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(84)
#error "SYSCLK cannot exceed 84MHz"
#endif
#ifdef __cplusplus
}
#endif
#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H */
/** @} */

66
cpu/stm32/include/clk/f2f4f7/cfg_clock_values.h
View File

@ -1,66 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief STM32F4 clock values definitions
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef CLK_F2F4F7_CFG_CLOCK_VALUES_H
#define CLK_F2F4F7_CFG_CLOCK_VALUES_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock values
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q)
#define CLOCK_AHB CLOCK_CORECLOCK
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV)
#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CLK_F2F4F7_CFG_CLOCK_VALUES_H */
/** @} */

89
cpu/stm32/include/clk/g0/cfg_clock_default.h → cpu/stm32/include/clk/g0g4/cfg_clock_default.h
View File

@ -11,7 +11,7 @@
* @{
*
* @file
* @brief Configure STM32G0 clock
* @brief Configure STM32G0/G4 clock
*
* CORECLOCK cannot exceeds 64MHz core clock. LSE is 32768Hz.
* Default configuration use PLL clock as system clock. PLL input clock is HSI
@ -20,70 +20,27 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef CLK_G0_CFG_CLOCK_DEFAULT_H
#define CLK_G0_CFG_CLOCK_DEFAULT_H
#ifndef CLK_G0G4_CFG_CLOCK_DEFAULT_H
#define CLK_G0G4_CFG_CLOCK_DEFAULT_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
* @name G0/G4 clock settings
*
* @{
*/
/* Select the desired system clock source between PLL, HSE or HSI */
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(24)
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#error "HSE clock frequency must be between 4MHz and 48MHz"
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 0
#endif
#define CLOCK_HSI MHZ(16)
#ifdef CPU_FAM_STM32G0
#ifndef CONFIG_CLOCK_HSISYS_DIV
#define CONFIG_CLOCK_HSISYS_DIV (1)
#endif
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
@ -93,17 +50,33 @@ extern "C" {
/* The following parameters configure a 64MHz system clock with HSI as input clock */
#ifndef CONFIG_CLOCK_PLL_M
#ifdef CPU_FAM_STM32G0
#define CONFIG_CLOCK_PLL_M (1)
#else
#define CONFIG_CLOCK_PLL_M (4)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#ifdef CPU_FAM_STM32G0
#define CONFIG_CLOCK_PLL_N (20)
#else
#define CONFIG_CLOCK_PLL_N (85)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_R
#ifdef CPU_FAM_STM32G0
#define CONFIG_CLOCK_PLL_R (5)
#else
#define CONFIG_CLOCK_PLL_R (2)
#endif
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#ifdef CPU_FAM_STM32G0
#define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV)
#else
#define CLOCK_CORECLOCK (CLOCK_HSI)
#endif
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
@ -114,22 +87,34 @@ extern "C" {
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK \
((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
#ifdef CPU_FAM_STM32G0
#if CLOCK_CORECLOCK > MHZ(64)
#error "SYSCLK cannot exceed 64MHz"
#endif
#else /* CPU_FAM_STM32G4 */
#if CLOCK_CORECLOCK > MHZ(170)
#error "SYSCLK cannot exceed 170MHz"
#endif
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_AHB CLOCK_CORECLOCK /* max: 64MHz */
#define CLOCK_AHB CLOCK_CORECLOCK /* max: 64MHz (G0), 170MHZ (G4) */
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (1)
#endif
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz (G0), 170MHZ (G4) */
#ifdef CPU_FAM_STM32G4
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1)
#endif
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz (only on G4) */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CLK_G0_CFG_CLOCK_DEFAULT_H */
#endif /* CLK_G0G4_CFG_CLOCK_DEFAULT_H */
/** @} */

127
cpu/stm32/include/clk/g4/cfg_clock_default.h
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@ -1,127 +0,0 @@
/*
* Copyright (C) 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief Configure STM32G4 clock
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef CLK_G4_CFG_CLOCK_DEFAULT_H
#define CLK_G4_CFG_CLOCK_DEFAULT_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
* @{
*/
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(24)
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#error "HSE clock frequency must be between 4MHz and 48MHz"
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 0
#endif
#define CLOCK_HSI MHZ(16)
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
/* The following parameters configure a 170MHz system clock with HSI16 as input clock */
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (4)
#endif
#ifndef CONFIG_CLOCK_PLL_N
#define CONFIG_CLOCK_PLL_N (85)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (2)
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK \
((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
#if CLOCK_CORECLOCK > MHZ(170)
#error "SYSCLK cannot exceed 170MHz"
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_AHB CLOCK_CORECLOCK /* max: 170MHz */
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (1)
#endif
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* max: 170MHz */
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1)
#endif
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz */
#ifdef __cplusplus
}
#endif
#endif /* CLK_G4_CFG_CLOCK_DEFAULT_H */
/** @} */

65
cpu/stm32/include/clk/l0l1/cfg_clock_default.h
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@ -26,76 +26,13 @@ extern "C" {
#endif
/**
* @name Clock system configuration
* @name L0/L1 clock system configuration
* @{
*/
/* Select the desired system clock source between PLL, HSE or HSI */
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_MSI
#define CONFIG_USE_CLOCK_MSI 0
#endif /* CONFIG_USE_CLOCK_MSI */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use MSI as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(24)
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24))
#error "HSE clock frequency must be between 1MHz and 24MHz"
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 0
#endif
#define CLOCK_HSI MHZ(16)
#ifndef CONFIG_CLOCK_MSI
#define CONFIG_CLOCK_MSI KHZ(4194)
#endif
/* The following parameters configure a 32MHz system clock with HSI as input clock */
#ifndef CONFIG_CLOCK_PLL_DIV
#define CONFIG_CLOCK_PLL_DIV (2)

63
cpu/stm32/include/clk/l4l5wb/cfg_clock_default.h
View File

@ -26,74 +26,13 @@ extern "C" {
#endif
/**
* @name Clock system configuration
* @name L4/L5/WB clock system configuration
* @{
*/
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_MSI
#define CONFIG_USE_CLOCK_MSI 0
#endif /* CONFIG_USE_CLOCK_MSI */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use MSI as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(8)
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#error "HSE clock frequency must be between 4MHz and 48MHz"
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 0
#endif
#define CLOCK_HSI MHZ(16)
#ifndef CONFIG_CLOCK_MSI
#define CONFIG_CLOCK_MSI MHZ(48)
#endif
/* The following parameters configure a 80MHz system clock with PLL as input clock */
#ifndef CONFIG_CLOCK_PLL_SRC_MSI
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \

77
cpu/stm32/include/clk/mp1/cfg_clock_common.h
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@ -1,77 +0,0 @@
/*
* Copyright (C) 2020 Savoir-faire Linux
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Base STM32MP1 clock configuration
*
* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
*/
#ifndef CLK_MP1_CFG_CLOCK_COMMON_H
#define CLK_MP1_CFG_CLOCK_COMMON_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock common configuration
* @{
*/
/* Select the desired system clock source between PLL, HSE or HSI */
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(24)
#endif
#define CLOCK_HSI MHZ(64)
#ifdef __cplusplus
}
#endif
#endif /* CLK_MP1_CFG_CLOCK_COMMON_H */
/** @} */

85
cpu/stm32/include/clk/mp1/cfg_clock_default.h
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@ -20,11 +20,88 @@
#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_H
#define CLK_MP1_CFG_CLOCK_DEFAULT_H
#if defined(CPU_LINE_STM32MP157Cxx)
#include "mp1/cfg_clock_default_208.h"
#else
#error "No clock configuration available for this family"
/**
* @name MP1 clock PLL settings (208MHz)
* @{
*/
/* The following parameters configure a 208MHz system clock with HSE (24MHz)
* or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (2)
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(24))
#ifndef CONFIG_CLOCK_PLL_N
#define CONFIG_CLOCK_PLL_N (52)
#endif
#else /* HSI */
#ifndef CONFIG_CLOCK_PLL_N
#define CONFIG_CLOCK_PLL_N (78)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (3)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (13)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (3)
#endif
/** @} */
/**
* @name MP1 clock bus settings (MCU, APB1, APB2 and APB3)
*/
#ifndef CONFIG_CLOCK_MCU_DIV
#define CONFIG_CLOCK_MCU_DIV (1) /* max 208MHz */
#endif
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (2) /* max 104MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (2) /* max 104MHz */
#endif
#ifndef CONFIG_CLOCK_APB3_DIV
#define CONFIG_CLOCK_APB3_DIV (2) /* max 104MHz */
#endif
/** @} */
#if CLOCK_CORECLOCK > MHZ(208)
#error "SYSCLK cannot exceed 208MHz"
#endif
/**
* @name MP1 clock values
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \
* CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \
* CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q)
#define CLOCK_APB1 (CLOCK_CORECLOCK \
/ CONFIG_CLOCK_APB1_DIV)
#define CLOCK_APB2 (CLOCK_CORECLOCK \
/ CONFIG_CLOCK_APB2_DIV)
/** @} */
#ifdef __cplusplus
extern "C" {

85
cpu/stm32/include/clk/mp1/cfg_clock_default_208.h
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@ -1,85 +0,0 @@
/*
* Copyright (C) 2020 Savoir-faire Linux
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default STM32MP1 clock configuration for 208MHz boards
*
* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
*/
#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_208_H
#define CLK_MP1_CFG_CLOCK_DEFAULT_208_H
#include "mp1/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock PLL settings (208MHz)
* @{
*/
/* The following parameters configure a 208MHz system clock with HSE (24MHz)
* or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (2)
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(24))
#ifndef CONFIG_CLOCK_PLL_N
#define CONFIG_CLOCK_PLL_N (52)
#endif
#else /* HSI */
#ifndef CONFIG_CLOCK_PLL_N
#define CONFIG_CLOCK_PLL_N (78)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (3)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (13)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (3)
#endif
/** @} */
/**
* @name Clock bus settings (MCU, APB1, APB2 and APB3)
*/
#ifndef CONFIG_CLOCK_MCU_DIV
#define CONFIG_CLOCK_MCU_DIV (1) /* max 208MHz */
#endif
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (2) /* max 104MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (2) /* max 104MHz */
#endif
#ifndef CONFIG_CLOCK_APB3_DIV
#define CONFIG_CLOCK_APB3_DIV (2) /* max 104MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "mp1/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(208)
#error "SYSCLK cannot exceed 208MHz"
#endif
#endif /* CLK_MP1_CFG_CLOCK_DEFAULT_208_H */
/** @} */

65
cpu/stm32/include/clk/mp1/cfg_clock_values.h
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@ -1,65 +0,0 @@
/*
* Copyright (C) 2020 Savoir-faire Linux
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief STM32MP1 clock values definitions
*
* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
*/
#ifndef CLK_MP1_CFG_CLOCK_VALUES_H
#define CLK_MP1_CFG_CLOCK_VALUES_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock values
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \
* CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \
* CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q)
#define CLOCK_APB1 (CLOCK_CORECLOCK \
/ CONFIG_CLOCK_APB1_DIV)
#define CLOCK_APB2 (CLOCK_CORECLOCK \
/ CONFIG_CLOCK_APB2_DIV)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CLK_MP1_CFG_CLOCK_VALUES_H */
/** @} */