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cpu/stm32/wl: common subghz debug pin initialization

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This commit is contained in:
Francisco Molina 2021-07-21 11:26:17 +02:00
parent f2995240d4
commit 8a8e023d04
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GPG Key ID: 3E94EAC3DBDEEDA8
3 changed files with 9 additions and 8 deletions
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7
boards/nucleo-wl55jc/include/periph_conf.h
View File

@ -78,6 +78,7 @@ static const uart_conf_t uart_config[] = {
#define UART_NUMOF ARRAY_SIZE(uart_config)
/** @} */
/**
* @name SPI configuration
* @{
@ -95,10 +96,10 @@ static const spi_conf_t spi_config[] = {
.cs_af = GPIO_AF_UNDEF,
.rccmask = RCC_APB3ENR_SUBGHZSPIEN,
.apbbus = APB3,
}
},
/* SUBGHZ DEBUG PINS use the SPI1 pins */
#if !IS_ACTIVE(CONFIG_STM32_WL55JC_SUBGHZ_DEBUG)
,{
#if !IS_ACTIVE(CONFIG_STM32_WLX5XX_SUBGHZ_DEBUG)
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),

8
cpu/stm32/cpu_init.c
View File

@ -155,9 +155,9 @@ static void _gpio_init_ain(void)
/**
* @brief Initialize HW debug pins for Sub-GHz Radio
*/
void _wl55jc_init_subghz_debug_pins(void)
void _wlx5xx_init_subghz_debug_pins(void)
{
#if IS_ACTIVE(CONFIG_STM32_WL55JC_SUBGHZ_DEBUG)
#if IS_ACTIVE(CONFIG_STM32_WLX5XX_SUBGHZ_DEBUG)
/* SUBGHZSPI Debug */
gpio_init(CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT, GPIO_OUT);
gpio_init_af(CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT,
@ -232,7 +232,7 @@ void cpu_init(void)
/* trigger static peripheral initialization */
periph_init();
if (IS_ACTIVE(CONFIG_STM32_WL55JC_SUBGHZ_DEBUG)) {
_wl55jc_init_subghz_debug_pins();
if (IS_ACTIVE(CONFIG_STM32_WLX5XX_SUBGHZ_DEBUG)) {
_wlx5xx_init_subghz_debug_pins();
}
}

2
cpu/stm32/include/periph/wl/periph_cpu.h
View File

@ -119,7 +119,7 @@ extern "C" {
* @brief Set this to 1 to enable hardware debugging.
*/
#ifdef DOXYGEN
#define CONFIG_STM32_WL55JC_SUBGHZ_DEBUG
#define CONFIG_STM32_WLX5XX_SUBGHZ_DEBUG
#endif
/** @} */