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cpu/stm32: add stm32wl

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This commit is contained in:
Akshai M 2021-03-05 01:00:00 +01:00
parent b6c4f9a610
commit c485c774cf
15 changed files with 65 additions and 34 deletions
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3
boards/common/stm32/dist/stm32wl.cfg vendored Normal file
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@ -0,0 +1,3 @@
source [find target/stm32wlx.cfg]
reset_config srst_only
$_TARGETNAME configure -rtos auto

16
cpu/stm32/cpu_common.c
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@ -68,7 +68,8 @@ void periph_clk_en(bus_t bus, uint32_t mask)
switch (bus) {
case APB1:
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL)
RCC->APB1ENR1 |= mask;
#elif defined(CPU_FAM_STM32G0)
RCC->APBENR1 |= mask;
@ -87,8 +88,14 @@ void periph_clk_en(bus_t bus, uint32_t mask)
#endif
break;
#endif
#if defined(CPU_FAM_STM32WL)
case APB3:
RCC->APB3ENR |= mask;
break;
#endif
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL)
case APB12:
RCC->APB1ENR2 |= mask;
break;
@ -112,7 +119,7 @@ void periph_clk_en(bus_t bus, uint32_t mask)
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
case AHB1:
RCC->AHB1ENR |= mask;
break;
@ -144,7 +151,8 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
switch (bus) {
case APB1:
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL)
RCC->APB1ENR1 &= ~(mask);
#elif defined(CPU_FAM_STM32G0)
RCC->APBENR1 &= ~(mask);

7
cpu/stm32/cpu_init.c
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@ -63,6 +63,10 @@
#define GPIO_CLK (AHB)
#define GPIO_CLK_ENR (RCC->AHBENR)
#define GPIO_CLK_ENR_MASK (0xFFFF0000)
#elif defined(CPU_FAM_STM32WL)
#define GPIO_CLK (AHB2)
#define GPIO_CLK_ENR (RCC->AHB2ENR)
#define GPIO_CLK_ENR_MASK (0x00000087)
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7)
#define GPIO_CLK (AHB1)
@ -152,7 +156,8 @@ void cpu_init(void)
/* initialize the Cortex-M core */
cortexm_init();
/* enable PWR module */
#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1)
#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) && \
!defined(CPU_FAM_STM32WL)
periph_clk_en(APB1, BIT_APB_PWREN);
#endif
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \

2
cpu/stm32/include/clk/clk_conf.h
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@ -44,7 +44,7 @@
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#include "l0l1/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
#include "l4l5wb/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32MP1)
#include "mp1/cfg_clock_default.h"

3
cpu/stm32/include/cpu_conf.h
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@ -67,6 +67,9 @@
#elif CPU_FAM_STM32WB
#include "stm32wbxx.h"
#include "irqs/wb/irqs.h"
#elif CPU_FAM_STM32WL
#include "stm32wlxx.h"
#include "irqs/wl/irqs.h"
#else
#error Not supported CPU family
#endif

12
cpu/stm32/include/periph_cpu.h
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@ -70,7 +70,7 @@ extern "C" {
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32MP1)
defined(CPU_FAM_STM32MP1) || defined(CPU_FAM_STM32WL)
#define CLOCK_LSI (32000U)
#else
#error "error: LSI clock speed not defined for your target CPU"
@ -170,9 +170,12 @@ extern "C" {
typedef enum {
APB1, /**< APB1 bus */
APB2, /**< APB2 bus */
#if defined(CPU_FAM_STM32WL)
APB3,
#endif
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
APB12, /**< AHB1 bus, second register */
#endif
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
@ -184,7 +187,7 @@ typedef enum {
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
AHB1, /**< AHB1 bus */
AHB2, /**< AHB2 bus */
AHB3, /**< AHB3 bus */
@ -681,7 +684,8 @@ typedef struct {
#endif
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32MP1)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32MP1) || \
defined(CPU_FAM_STM32WL)
uart_type_t type; /**< hardware module type (USART or LPUART) */
uint32_t clk_src; /**< clock source used for UART */
#endif

1
cpu/stm32/include/vendor/Makefile vendored
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@ -16,6 +16,7 @@ PKG_VERSION_l1=4a2f3cd6ea4bbc8e36daff0c7574b0fc1dfb7df7 # v2.3.0
PKG_VERSION_l4=e442c72651e8d4757f6562acc14da949644944ce # v1.6.1
PKG_VERSION_l5=d922865fc0326a102c26211c44b8e42f52c1e53d # v1.0.3
PKG_VERSION_wb=44490652c88a513ec9a892c328db0246cf113987 # v1.4.0
PKG_VERSION_wl=35631ff4d3a3cc361241af5f62190d0ea43bd65b # v1.0.0
PKG_VERSION=$(PKG_VERSION_$(CPU_FAM))
PKG_LICENSE=Apache-2

10
cpu/stm32/periph/gpio_all.c
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@ -46,7 +46,7 @@ static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF];
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
#define EXTI_REG_RTSR (EXTI->RTSR1)
#define EXTI_REG_FTSR (EXTI->FTSR1)
#define EXTI_REG_PR (EXTI->PR1)
@ -102,7 +102,8 @@ static inline void port_init_clock(GPIO_TypeDef *port, gpio_t pin)
#elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined (CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
defined (CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined (CPU_FAM_STM32WL)
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
#ifdef PWR_CR2_IOSV
if (port == GPIOG) {
@ -170,7 +171,8 @@ void gpio_init_analog(gpio_t pin)
#elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined (CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
defined (CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
defined (CPU_FAM_STM32WL)
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
#elif defined(CPU_FAM_STM32MP1)
periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin)));
@ -236,7 +238,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
isr_ctx[pin_num].arg = arg;
/* enable clock of the SYSCFG module for EXTI configuration */
#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1)
#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) && !defined(CPU_FAM_STM32WL)
#ifdef CPU_FAM_STM32F0
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN);
#elif defined(CPU_FAM_STM32G0)

6
cpu/stm32/periph/pm.c
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@ -49,7 +49,7 @@
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5)
#define PM_STOP_CONFIG (PWR_CR1_LPMS_STOP1)
#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0)
#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32WL)
#define PM_STOP_CONFIG (PWR_CR1_LPMS_0)
#elif defined(CPU_FAM_STM32F7)
#define PM_STOP_CONFIG (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS)
@ -71,7 +71,7 @@
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5)
#define PM_STANDBY_CONFIG (PWR_CR1_LPMS_STANDBY)
#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0)
#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32WL)
#define PM_STANDBY_CONFIG (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
#elif defined(CPU_FAM_STM32F7)
#define PM_STANDBY_CONFIG (PWR_CR1_PDDS | PWR_CR1_CSBF)
@ -84,7 +84,7 @@
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
#define PWR_CR_REG PWR->CR1
#define PWR_WUP_REG PWR->CR3
/* Allow overridable SRAM2 retention mode using CFLAGS */

10
cpu/stm32/periph/uart.c
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@ -35,7 +35,7 @@
#include "pm_layered.h"
#if defined(CPU_LINE_STM32L4R5xx) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
#define ISR_REG ISR
#define ISR_TXE USART_ISR_TXE_TXFNF
#define ISR_RXNE USART_ISR_RXNE_RXFNE
@ -62,7 +62,7 @@
#endif
#if defined(CPU_LINE_STM32L4R5xx) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
#define RXENABLE (USART_CR1_RE | USART_CR1_RXNEIE_RXFNEIE)
#else
#define RXENABLE (USART_CR1_RE | USART_CR1_RXNEIE)
@ -98,7 +98,7 @@ static inline USART_TypeDef *dev(uart_t uart)
static inline void uart_init_usart(uart_t uart, uint32_t baudrate);
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
#ifdef MODULE_PERIPH_LPUART
static inline void uart_init_lpuart(uart_t uart, uint32_t baudrate);
#endif
@ -192,7 +192,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
switch (uart_config[uart].type) {
case STM32_USART:
uart_init_usart(uart, baudrate);
@ -322,7 +322,7 @@ static inline void uart_init_usart(uart_t uart, uint32_t baudrate)
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
#ifdef CPU_FAM_STM32L5
#define RCC_CCIPR_LPUART1SEL_0 RCC_CCIPR1_LPUART1SEL_0
#define RCC_CCIPR_LPUART1SEL_1 RCC_CCIPR1_LPUART1SEL_1

4
cpu/stm32/stm32_info.mk
View File

@ -8,7 +8,7 @@
# - STM32_PINCOUNT: R (64)
# - STM32_ROMSIZE: G (1024K)
CPU_MODEL_UPPERCASE = $(call uppercase,$(CPU_MODEL))
STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G|MP)([0-7]|B)([A-Z0-9])([0-9])(.)(.)?(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/')
STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G|MP)([0-7]|B|L)([A-Z0-9])([0-9])(.)(.)?(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/')
STM32_TYPE = $(word 1, $(STM32_INFO))
STM32_FAMILY = $(word 2, $(STM32_INFO))
STM32_MODEL = $(word 3, $(STM32_INFO))
@ -31,7 +31,7 @@ else ifneq (,$(filter $(CPU_FAM),f1 f2 l1))
CPU_CORE = cortex-m3
else ifneq (,$(filter $(CPU_FAM),f3 f4 l4 mp1))
CPU_CORE = cortex-m4f
else ifneq (,$(filter $(CPU_FAM),g4 wb))
else ifneq (,$(filter $(CPU_FAM),g4 wb wl))
CPU_CORE = cortex-m4
else ifeq (f7,$(CPU_FAM))
CPU_CORE = cortex-m7

2
cpu/stm32/stm32_mem_lengths.mk
View File

@ -273,6 +273,8 @@ else ifeq ($(STM32_TYPE), W)
RAM_LEN = 256K
endif
endif
else ifeq ($(STM32_FAMILY), L)
RAM_LEN = 64K
endif
else ifeq ($(STM32_TYPE), MP)
ifeq ($(STM32_FAMILY), 1)

4
cpu/stm32/stmclk/Makefile
View File

@ -10,8 +10,8 @@ else ifneq (,$(filter $(CPU_FAM),f0 f1 f3))
SRC += stmclk_f0f1f3.c
else ifneq (,$(filter $(CPU_FAM),l0 l1))
SRC += stmclk_l0l1.c
else ifneq (,$(filter $(CPU_FAM),l4 wb))
SRC += stmclk_l4wb.c
else ifneq (,$(filter $(CPU_FAM),l4 wb wl))
SRC += stmclk_l4wbwl.c
else ifneq (,$(filter $(CPU_FAM),l5))
SRC += stmclk_l5.c
else ifneq (,$(filter $(CPU_FAM),g0 g4))

3
cpu/stm32/stmclk/stmclk_common.c
View File

@ -25,7 +25,8 @@
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5)
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WL)
#define REG_PWR_CR CR1
#define BIT_CR_DBP PWR_CR1_DBP
#else

16
cpu/stm32/stmclk/stmclk_l4wb.c → cpu/stm32/stmclk/stmclk_l4wbwl.c
View File

@ -29,7 +29,7 @@
#include "periph/gpio.h"
/* map CMSIS defines not present in stm32wb55xx.h */
#if defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
#define RCC_PLLCFGR_PLLSRC_HSE (RCC_PLLCFGR_PLLSRC_0 | RCC_PLLCFGR_PLLSRC_1)
#define RCC_PLLCFGR_PLLSRC_HSI (RCC_PLLCFGR_PLLSRC_1)
#define RCC_PLLCFGR_PLLSRC_MSI (RCC_PLLCFGR_PLLSRC_0)
@ -67,7 +67,7 @@
#endif
#define PLL_N (CONFIG_CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
#if defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
#if (CONFIG_CLOCK_PLL_R < 1 || CONFIG_CLOCK_PLL_R > 8)
#error "PLL configuration: PLL R value is invalid"
#else
@ -87,7 +87,7 @@
#endif
#endif
#if defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
#if (CONFIG_CLOCK_PLL_Q < 1 || CONFIG_CLOCK_PLL_Q > 8)
#error "PLL configuration: PLL Q value is invalid"
#else
@ -249,7 +249,7 @@
#define CONFIG_CLOCK_MCO_PRE (1)
#endif
#ifdef CPU_FAM_STM32WB
#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
/* Define bitfields for MCO prescaler for compatibility with L4*/
#define RCC_CFGR_MCOPRE_DIV1 (0)
#define RCC_CFGR_MCOPRE_DIV2 (RCC_CFGR_MCOPRE_0)
@ -273,7 +273,7 @@
#endif
/* Configure main and peripheral bus clock prescalers */
#if defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
#define CLOCK_AHB_DIV (0)
#if CONFIG_CLOCK_APB1_DIV == 1
@ -339,7 +339,9 @@
#define CLOCK48MHZ_USE_MSI 0
#endif
#if IS_ACTIVE(CLOCK48MHZ_USE_PLLQ)
#if defined(CPU_FAM_STM32WL)
#define CLOCK48MHZ_SELECT (0)
#elif IS_ACTIVE(CLOCK48MHZ_USE_PLLQ)
#define CLOCK48MHZ_SELECT (RCC_CCIPR_CLK48SEL_1)
#elif IS_ACTIVE(CLOCK48MHZ_USE_MSI)
#define CLOCK48MHZ_SELECT (RCC_CCIPR_CLK48SEL_1 | RCC_CCIPR_CLK48SEL_0)
@ -431,7 +433,7 @@
* @name Deduct the needed flash wait states from the core clock frequency
* @{
*/
#if defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
#if (CLOCK_AHB <= 64000000)
#define FLASH_WAITSTATES ((CLOCK_AHB - 1) / 18000000U)
#else