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cpu/stm32: fix doxygen grouping warnings

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Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
This commit is contained in:
Jean-Pierre De Jesus DIAZ 2021-09-05 20:39:15 +02:00
parent 1759014134
commit 9d1cff3b55
9 changed files with 12 additions and 5 deletions
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9
cpu/stm32/dist/clk_conf/clk_conf.h vendored
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@ -11,8 +11,7 @@
*
*
* @author Vincent Dupont <vincent@otakeys.com>
*
* @}
* @{
*/
#ifndef CLK_CONF_H
@ -26,7 +25,7 @@ extern "C" {
/**
* @name STM32 families
* @ {
* @{
*/
enum fam {
STM32F0,
@ -115,7 +114,6 @@ enum {
MODEL_MP_MAX,
};
/** @} */
/**
@ -631,7 +629,7 @@ static const clk_cfg_t stm32_f_clk_cfg[] = {
},
};
/**
/**
* @brief Clock config for supported cpu
*/
static const clk_cfg_t stm32_mp_clk_cfg[] = {
@ -658,3 +656,4 @@ static const clk_cfg_t stm32_mp_clk_cfg[] = {
#endif
#endif /* CLK_CONF_H */
/** @} */

1
cpu/stm32/include/clk/cfg_clock_common_lx_wx.h
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@ -40,6 +40,7 @@ extern "C" {
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
/** @} */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \

1
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
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@ -75,6 +75,7 @@ extern "C" {
/**
* @name Clock bus settings (APB1 and APB2)
* @{
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (2) /* max 50MHz */

1
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h
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@ -53,6 +53,7 @@ extern "C" {
/**
* @name Clock bus settings (APB1 and APB2)
* @{
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4) /* max 30MHz */

1
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
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@ -87,6 +87,7 @@ extern "C" {
/**
* @name Clock bus settings (APB1 and APB2)
* @{
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */

1
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h
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@ -62,6 +62,7 @@ extern "C" {
/**
* @name Clock bus settings (APB1 and APB2)
* @{
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4) /* max 54MHz */

1
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h
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@ -62,6 +62,7 @@ extern "C" {
/**
* @name Clock bus settings (APB1 and APB2)
* @{
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (2) /* max 42MHz */

1
cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h
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@ -175,6 +175,7 @@ extern "C" {
#define CONFIG_CLOCK_APB2_DIV (2)
#endif
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 48/64/80/120MHz */
/** @} */
#ifdef __cplusplus
}

1
cpu/stm32/include/clk/mp1/cfg_clock_default.h
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@ -50,6 +50,7 @@
/**
* @name MP1 clock bus settings (MCU, APB1, APB2 and APB3)
* @{
*/
#ifndef CONFIG_CLOCK_MCU_DIV
#define CONFIG_CLOCK_MCU_DIV (1) /* max 208MHz */