The current ATxmega clock_init enable DFLL to improve the accuracy of
the 2MHz and 32MHz internal oscillators. In some ATxmega revisions,
after started DFLL the clock become unstable. Add another sync point
for 32MHz internal oscilator.
Note: If clock is not stable, system won't switch from 2MHz to 32MHz
as main clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Fix compilation with module `stm32_eth_link_up` when `stm32_eth_auto`
is not used by relying on the compiler to optimize unused functions
and variables out, rather than using the preprocessor.
- Clear the PTP timer interrupt *after* the user callback is executed
- Otherwise it would be possible that the ISR sets another super
short timeout that triggers during ISR, which also gets cleared
- This is a pretty nasty race condition :-/
- The debug output was a bit too verbose to be generally useful. Some
noise is now silenced unless `DEBUG_VERBOSE` is `#define`d to 1
Atmel AVR-8 CPU was reworked to accomodate variants like ATxmega.
This rename to atmega.inc.mk to avr8.inc.mk to be compliant with
new directory structure.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
ATxmega have many clock options. This introduce clk_init into cpu_init
to allow user select between a default configuration or perform fine
clock tune.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The XMEGA CPU have a Programmable Multilevel Interrupt Controller.
This enables all three PMIC levels. By default, all interrupts are
preconfigured as LOW Level without Round Robin queue. This works
as any MCU with interrupt enabled.
In order to get benefit from Multilevel Interrupts user need increase
the interrupt level by own.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Current there is no way to split code between ATmega and ATxmega in
drivers. This differentiate AVR8 cores into MEGAs and XMEGAs.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current context switch and thread stack init don't have a generic
way to save/restore registers for all AVR-8 variations. This add
defines to check flash/data sizes and rework:
- thread_stack_init
- avr8_context_save
- avr8_context_restore
The new implementation add missing RAMP D/X/Y registers that are used
by XMEGA variations.
The rules to add EIND, RAMP(D,X,Y,Z) register are:
- EIND must be added if device have more than 128k flash. This means,
device can access more than 64k words in flash.
- RAMP D/X/Y must be added if device have or can address more than
64k data.
- RAMPZ must be added if device can address more than 64k bytes of
flash or data.
With above rules there is no necessity to check by device because it is
mandatory the registers for those MCU variations.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add ATxmega common files and cpu definitions.
This works was originally developed by @Josar. The 2018 version
were port to 2021 mainline.
This version changes original port to have only the atxmega CPU
definition. With that, all family can be accomodated.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some mega boards enabling global irq at board_init. This moves that
responsability to cpu/avr8_common to create a common point to all
variants.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The ATxmega can have up to 8 UARTs. This increase from 2 up to 7 to
keep avr8_state flags with 8 bits wide.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
Some periph_rtt implementations do not provide `rtt_set_counter()`. This
adds `periph_rtt_set_counter` as feature to allow testing for its
availability. The feature is provided at CPU level if periph_rtt is
provided by the board for all CPUs implementing `rtt_set_counter()`.
Found and fixed the issue for the kinetis-based boards: The kinetis
code is using some macros to map some IRQ names, that differ in
some versions of vendor headers, to a RIOT wide unique name. The
doxygen of this mapping states, that this mapping must be done before
any vendor header is included. Unfortunately, the mapping was so far
placed in cpu/kinetis/vectors.c, before any other include statement.
In some cases, the vendor headers might be included before the
mapping macros in vectors.c, leading to the compilation errors down
the line. To fix this, the adaption defines are moved into
cpu/kinetis/cpu_conf.h, which is the file that actually includes
the vendor headers. This way it is ensured, that these adaption
macros are always defined before any vendor header is included,
and therefore preventing this kind of error for good.
- Adds capabilities for each PHY mode. Converts the uint16_t caps field to an
uint32_t in order to hold all capability bits, size of the structure remains
unchanged due to alignment.
- Modifies the test application to configure the PHY mode using the shell
command. Also adds the PHY modes to the capabilities shell command.
- Updates the nrf802154 and cc2538 radio drivers to specify the PHY mode
supported.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
If there is an event to be handled by _esp_eth_isr(), don't
overwrite it if a new packet has been received.
In my testing, all SYSTEM_EVENT_ETH_CONNECTED events except the first
are immediately followed by at least one SYSTEM_EVENT_ETH_RX_DONE event.
This causes the SYSTEM_EVENT_ETH_CONNECTED to not get handled, and the
IP stack will not be notified of the new link state.
Protect the other events by dropping the packet instead. If an earlier
unhandled SYSTEM_EVENT_ETH_RX_DONE event exists, overwrite it with the
newer packet.
I only saw this happen with lwIP and not with GNRC - I am not sure why.
But it still is a race waiting to happen. The nice long term solution
is probably to have a queue of unhandled events, allowing them all to
be processed once there is time.
The ADC SYNCBUSY.SWTRIG gets stuck to '1' after wake-up from Standby Sleep mode.
Ignore the ADC `SYNCBUSY.SWTRIG` status bit, this functionality is not used by
the driver anyway.
The global core/ldscripts/xfa.ld doesn't match our cortexm_base.ld.
This commit directly adds the two XFA lines to cortexm_base.ld.
In addition to that, a dummy (empty) xfa.ld is added, which the linker will pick
instead of core/ldscripts/xfa.ld, effectingly not using it.
nRF52833 has POWER_MAINREGSTATUS_MAINREGSTATUS_High, but no POWER->DCDCEN0
register.
This breaks all builds on this MCU.
Fix the ifdef to fix the build.
This allows using the macro inside the periph_conf.h board files since the
periph/gpio.h header can't be included on the peripheral configuration.
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
Deep-sleep was based on using rx pin as external interrupt to be able to
wake up from stop mode. If rx pin cannot be used as interrupt or user
does not need to wake up from stop from the CAN, an option is now
present. If en_deep_sleep_wake_up is set to false, setting the device to
sleep simply unblock stop mode. Otherwise the behavior is unchanged.
In case a non-gpio EXTI (>= 16) is pending, the isr_exti() used to clear
the flag and try to call a callback, which was out-of-bouds, thus
generating a hard fault.
This fixes it by masking the pending_isr variables with 0xFFFF.
The ram size is exposed as macro value and available for use in code.
For the stm32 it has a value in kilobytes suffixed with 'k'. This is
less than optimal for usage in arithmetic. This commit modifies the
value to bytes so that it can be used in preprocessor magic
This patch implements the basic support the last of the FLEXCOMM modes,
Serial Peripheral Interface, in a simple blocking mode with busy wait,
which is enough to test all the SPI functionality end-to-end.
Tested reading and writing registers on a SPI peripheral, and checked
with the oscilloscope that the frequencies were as expected.
Results from `tests/periph_spi`:
```
> init 0 0 2 -1 0
SPI_DEV(0) initialized: mode: 0, clk: 2, cs_port: -1, cs_pin: 0
> bench
1 - write 1000 times 1 byte: 16002 16009
2 - write 1000 times 2 byte: 18001 18008
3 - write 1000 times 100 byte: 802000 802007
4 - write 1000 times 1 byte to register: 24003 24010
5 - write 1000 times 2 byte to register: 26001 26008
6 - write 1000 times 100 byte to register: 810001 810008
7 - read 1000 times 2 byte: 23003 23009
8 - read 1000 times 100 byte: 807002 807009
9 - read 1000 times 2 byte from register: 32002 32009
10 - read 1000 times 100 byte from register: 816002 816009
11 - transfer 1000 times 2 byte: 23003 23009
12 - transfer 1000 times 100 byte: 807003 807010
13 - transfer 1000 times 2 byte to register: 32003 32009
14 - transfer 1000 times 100 byte to register:816002 816009
15 - acquire/release 1000 times: 7222 7228
-- - SUM: 5059250 5059351
```
The macro was moved from Kconfig to the periph_cpu.h which means that
the macro name needed to be updated to BOARD_HAS_ADC_PA06_CAP instead
of CONFIG_BOARD_HAS_ADC_PA06_CAP.
The ADC in the QN908x cpu offers multiple options for ADC conversion
using up to 8 external pins, one external reference pin and some
internal signals like a 1.2V reference, Vss, Vcc and an internal
temperature monitor.
This patch implements support for sampling ADC values from the ADC lines
defined in the board configuration. Some configurations are really
always present and don't require a board configuration, like the Vcc or
internal temperature monitor but to coexist with other board ADC line
options they are only set as part of the board configuration.
The mv instruction (which is usually implemented as `add rd, x0, r1`) is
changed to `add rd, x0, %input`. This can either be used as a load
immediate or as an move.
The code size grows by two bytes. This because GCC does not compress the
li instruction to the compressed version (even though this is possible).
Add ENABLE_DEBUG_VERBOSE flag, so that the noise during debugging can be
reduced. This is super helpful when testing under load, as otherwise there is
just too much noise in the output.
An earlier version of periph_eth used to always pack the first chunk of the
outgoing frame to the first DMA descriptor by telling the DMA to jump back
to the first descriptor within the last descriptor. This worked fine unless
the frame was send in one chunk (as e.g. lwip does), which resulted due to a
hardware bug in a frame being send out twice. For that reason, the behavior was
changed to cycle throw the linked DMA descriptor list in round-robin fashion.
However, the error checking was not updated accordingly. Hence, the error
check might run over (parts of) unrelated frames and fail to detect errors
correctly.
This commit fixes the issue and also provides proper return codes for errors.
Additionally, an DMA reset is performed on detected errors during RX/TX. I'm
not sure if/when this is needed, as error conditions are neigh impossible to
produce. But better be safe than sorry.
CPU_HAS_SRAM_BITBAND can be used to check whether bit-banding is supported for
all of SRAM. With partially supported bit-banding, this feature is more of a
foot gun that a valuable tool.
This commit fixes the CCA threshold range for set_cca_threshold.
Without this commit the threshold overflows when using values below
the receiver sensitivity.
This commit turns off the transceiver immediately after sending an ACK
frame in order to avoid unwanted emissions (see ERRATA ID 204).
When the radio stays in TX_ON without an explicit transition, the radio
keeps sending a spurious signal for some milliseconds.
This commit sets the correct value to the MCU_CTRL bit for the
cc2538_rf. This variable is used to detect when the radio is doing
transmission with CCA. Since this was not set to 1 when sending without
CCA, the `confirm_transmit` function returned -EAGAIN after the TX_DONE
event (which violates the HAL API).
This error was discovered using some Radio HAL riotctrl scripts by @LarsKowoll.
`gnrc_netif_hdr_build()` calls internally `gnrc_netif_hdr_init()`, which does
initialize `gnrc_netif_hdr_t::rssi` and `gnrc_netif_hdr_t::lqi`. So no need to
do this twice.
Errate 2.17.4 says:
> Upon enabling the RTC tamper detection feature, a false tamper
> detection *can* be reported by the RTC.
It turns out that this spurious event is not always generated.
If RTC alarm is used and the CPU was previously woken from hibernate
by RTC, it *can* happen that the false tamper event is *not* generated.
In this case, we will block indefinitely on the mutex.
To solve this, add a timeout to the event.
Also poll the event instead of using a mutex, as we have already set
`PM->SLEEPCFG.bit.SLEEPMODE` at this point.
Split atmega_common code into avr8_common folder. This moves common
avr8 code to be used for all avr8 variants: tiny, mega and xmega.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Split cpu.c file into cpu.c and atmega_cpu.c files. This extract mega
specific code from common code.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The module cpu_atmega_common_cxx seems to be non-existing and not used. It is
unclear whether this slipped in by accident or if this was actually useful at
some point in time. In any case, the module is not present (anymore) and cannot
be used, so let's clean up the Makefile.
This initial I2C support allows to use the I2C bus in controller mode to
interact with multiple peripherals in blocking mode. The CPU will
perform a busy wait when transferring data over I2C.
Split out Gunar Schorcht's clever approach to provide thread safe malloc for
AVR into a system module and make AVR depend on this. This allows other
platforms to also use this.
If the same callback function is used for multiple interfaces
(`NETDEV_INDEX_ANY`), it is necessary to also provide the index of
the interface to hand out and address.
The DAC can have some start-up delay.
If we try to write to it before it's ready, it will get stuck.
This happens now that `tests/driver_dac_dds` immediately sets a DAC
value after init.
The samd2x class of MCUs doesn't have this bit, but a quick test on
samd10 shows that it might not be nececary there - the DAC does not
get stuck when writing to it immediately after init.
Add periph_uart_nonblocking. Since cc2538 has a transmit FIFO write
to the FIFO first and to a tsrb buffer only when the transmit FIFO
is full.
Rely on the FIFO TXIFLSEL condition to fill up FIFO as space becomes
available.
The bit access functions are not tied to Cortex-M CPUs, here they only
provide optimisations via bit-banding.
But the functions are generally useful - so move them to an arch independent
location.
This patch implements the real time clock module for the QN908X cpus.
This module is very straightforward with only the one notable drawback
that it doesn't have a match register like the CTIMER block to implement
the alarm function. Instead, this driver can only use the interrupt
generated ever 1 second to implement the alarm match comparison in
software.
The IRQ for each GPIO port needs to be enabled in the NVIC on top of
enabling the corresponding bit in the GPIO port.
This was not caught in tests before because I was testing with a larger
stack of commits (including UART and timers) which also had this fix.
Manually poking the GPIOs while using tests/periph_gpio now properly
fires the interrupts.
The QN908x CPU has several timer modules: one RTC (Real-Time Clock) that
can count from the 32kHz internal clock or 32.768 kHz external clock,
four CTIMER that use the APB clock and have four channels each and one
SCT timer with up to 10 channels running on the AHB clock.
This patch implements a timer driver for the CTIMER blocks only, which
is enough to make the xtimer module work. Future patches should improve
on this module to support using the RTC CNT2 32-bit free-running
counter unit and/or the SCT timer.
GPIO_BOTH gpio_flank_t; UART_PARTY_MARK and UART_PARTY_SPACE in
uart_parity_t; and UART_DATA_BITS_5 and UART_DATA_BITS_6
uart_data_bits_t enum values where missing from the periph_cpu.h header
since they are not supported by the CPU. This was causing some tests to
fail to compile, but only after adding the periph_timer module.
This patch adds those missing macros and makes the corresponding
functions fail when trying to use them.
A minor fix to the NWDT_TIME_LOWER_LIMIT value setting it to 1U to avoid
a -Werror=type-limits error in the tests/periph_wdt test. In theory 0
is a totally valid value although a bit useless since it will trigger
the WDT right away.
The QN908x has four FLEXCOMM interfaces that support a subset of UART,
SPI or I2C each one. This patch adds generic support for dealing with
the FLEXCOMM initialization and interrupts and adds a driver for
RX/TX support in UART.
With this patch is now possible to use a shell on the device over UART.
The NXP QN908x CPU family is a Cortex-M4F CPU with integrated USB,
Bluetooth Low Energy and in some variants NFC. This patch implements the
first steps for having support for this CPU.
While the QN908x can be considered the successor of similar chips from
NXP like the KW41Z when looking at the feature set, the internal
architecture, boot image format and CPU peripherals don't match those
in the Kinetis line. Therefore, this patch creates a new directory for
just the QN908x chip under cpu/qn908x.
The minimal set of peripherals are implemented in this patch to allow
the device to boot and enable a GPIO: the gpio and wdt peripheral
modules only.
The wdt driver is required to boot and disable the wdt. On reset, the
wdt is disabled by the chip, however the QN908x bootloader stored in
the internal ROM enables the wdt and sets a timer to reboot after 10
seconds, therefore it is needed to disable the wdt in RIOT OS soon
after booting. This patch sets it up such that when no periph_wdt module
is used the Watchdog is disabled, but if the periph_wdt is used it must
be configured (initialized) within the first 10 seconds.
Tests performed:
Defined a custom board for this CPU and compiled a simple application
that blinks some LEDs. Manually tested with periph_wdt and with
periph_wdt_cb as well.
In preparation for adding support for the QN908x cpus, this patch adds
a pristine copy of the vendor SDK files needed for initial support.
The only modification to these files is to add '#ifdef __cplusplus'
guards to all the header files, even if not needed or already
present as '#if defined(__cplusplus)', to make sure
./dist/tools/externc/check.sh check passes.
These files are located under vendor/ directories (both
cpu/qn908x/include/vendor/ and cpu/qn908x/vendor/) and are part of NXP's
SDK for the QN908x family available for download from:
https://mcuxpresso.nxp.com/en/builder
The files included in these vendor/ directories are released by NXP
under an Open Source license as described in each file, but only the
files used by the next patch are included here.
The basic nrf802154 driver lacks ACK handling and retransmissions,
which degrades it's usefulness.
The 802.15.4 Sub-MAC fixes all those issues.
Enable it by default for this driver to make it better behaved.
This commits adds a common type for the block writes to the flash of the
stm32. Depending on the family, the type has a different size. This
allows the removal of a number of ifdefs to track the differences
between families, simplifying the flashpage code
- Add `WORD_ALIGNED` attribute to potentially unaligned allocations
- Use intermediate cast to `uintptr_t` to silence false positives of
`-Wcast-align`
`flashpage_write_raw()` got renamed to `flashpage_write()`.
Now `sam0_flashpage_aux_write_raw()` is the only remaining 'raw'
function, even though it behaves just like `flashpage_write()`.
So let's also rename that for consistency.
