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https://github.com/RIOT-OS/RIOT.git
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Merge pull request #15689 from iosabi/qn908x_spi
cpu/qn908x: Implement blocking SPI support
This commit is contained in:
benpicco
GitHub
commit
e87874ae54
@ -19,6 +19,7 @@ config BOARD_QN9080DK
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select BOARD_HAS_XTAL_32M
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select HAS_PERIPH_ADC
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select HAS_PERIPH_I2C
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select HAS_PERIPH_SPI
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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select HAS_PERIPH_UART_MODECFG
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@ -2,3 +2,8 @@ ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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USEMODULE += mma8x5x
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endif
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# For MX25R2035F on SPI_DEV(0).
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ifneq (,$(filter mtd,$(USEMODULE)))
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USEMODULE += mtd_spi_nor
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endif
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@ -5,6 +5,7 @@ CPU_MODEL = qn9080xhn
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart periph_uart_modecfg
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@ -21,8 +21,44 @@
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#include "cpu.h"
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#include "board.h"
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#include "mtd.h"
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#include "mtd_spi_nor.h"
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#include "timex.h"
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#include "periph/gpio.h"
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#ifdef MODULE_MTD
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/* MX25R2035F */
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static const mtd_spi_nor_params_t _mtd_nor_params = {
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.opcode = &mtd_spi_nor_opcode_default,
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.wait_chip_erase = 15000LU * US_PER_MS,
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.wait_64k_erase = 3500LU * US_PER_MS,
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.wait_32k_erase = 1750LU * US_PER_MS,
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.wait_sector_erase = 240LU * US_PER_MS,
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.wait_chip_wake_up = 1LU * US_PER_MS,
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.clk = CLOCK_CORECLOCK, /* Max fR and fC is 33 MHz, max core is 32 MHz. */
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.flag = SPI_NOR_F_SECT_4K | SPI_NOR_F_SECT_32K | SPI_NOR_F_SECT_64K,
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.spi = SPI_DEV(0),
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.mode = SPI_MODE_0,
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.cs = SPI_HWCS(0), /* GPIO(PORT_A, 3) is used for HWCS(0) on FC2 */
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.wp = GPIO_UNDEF,
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.hold = GPIO_UNDEF,
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.addr_width = 3, /* 24-bit addresses */
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};
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static mtd_spi_nor_t mtd_nor_dev = {
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.base = {
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.driver = &mtd_spi_nor_driver,
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.page_size = 256,
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.pages_per_sector = 16, /* 4 KiB sectors */
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.sector_count = 64,
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},
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.params = &_mtd_nor_params,
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};
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mtd_dev_t *mtd0 = (mtd_dev_t *)&mtd_nor_dev;
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#endif /* MODULE_MTD */
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void board_init(void)
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{
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/* Initialize LEDs and Buttons. */
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@ -20,6 +20,7 @@
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#define BOARD_H
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#include "cpu.h"
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#include "mtd.h"
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#include "periph_conf.h"
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#include "periph_cpu.h"
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@ -68,6 +69,14 @@ extern "C" {
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#define MMA8X5X_PARAM_TYPE (MMA8X5X_TYPE_MMA8652)
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/** @} */
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/**
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* @name MTD configuration
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* @{
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*/
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extern mtd_dev_t *mtd0;
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#define MTD_0 mtd0
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/** @} */
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/**
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* @brief Initialize board specific hardware
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*/
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@ -66,6 +66,28 @@ static const i2c_conf_t i2c_config[] = {
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI0, /* Flexcomm 2 */
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.cipo_pin = GPIO_PIN(PORT_A, 5),
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.copi_pin = GPIO_PIN(PORT_A, 4),
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.clk_pin = GPIO_PIN(PORT_A, 30),
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.cs_pin = {
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GPIO_PIN(PORT_A, 3), /* MX25R2035F CS# connected here. */
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF
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},
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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@ -15,6 +15,7 @@ config CPU_FAM_QN908X
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select HAS_PERIPH_GPIO_IRQ
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select HAS_PERIPH_I2C_RECONFIGURE
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select HAS_PERIPH_RTC
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select HAS_PERIPH_SPI_RECONFIGURE
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select HAS_PERIPH_WDT
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select HAS_PERIPH_WDT_CB
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@ -6,6 +6,7 @@ FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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FEATURES_PROVIDED += periph_i2c_reconfigure
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi_reconfigure
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FEATURES_PROVIDED += periph_wdt periph_wdt_cb
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include $(RIOTCPU)/cortexm_common/Makefile.features
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@ -137,6 +137,55 @@ same time since they are both the same FLEXCOMM1 interface.
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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@defgroup cpu_qn908x_spi NXP QN908x Serial Peripheral Interface (SPI)
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@ingroup cpu_qn908x
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@brief NXP QN908x timer driver
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Two of the FLEXCOMM interfaces in this chip can be used as SPI interfaces named
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SPI0 and SPI1, which correspond to FLEXCOMM2 and FLEXCOMM3. Note that FLEXCOMM2
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(SPI0) is also shared with the I2C peripheral I2C1 and both can't be used at
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the same time.
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The SPI flexcomm clock is directly driven from the AHB bus, so its clock is
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limited by the core CPU clock and the AHB divisor on the higher side with an
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optional frequency divider of up to 65536 to generate lower clock frequencies.
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Multiple peripherals can be connected to the same SPI bus, using different CS
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pins, with a maximum of 4 hardware CS peripherals per bus and any number of
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software CS peripherals.
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This driver uses the [OSHA SPI Signal Names](
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https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/) and while it
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only implements the Controller mode, the hardware is capable of operating in
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Peripheral mode as well so we use the COPI/CIPO names.
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### SPI configuration example (for periph_conf.h) ###
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The following example uses only one hardware CS (number 0) and leaves the rest
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unused. Check the user manual for the full list of CS pins available.
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When configuring the CS line on a driver, you should pass a @ref SPI_HWCS to use
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the hardware CS mode defined in this configuration. To use any other GPIO as a
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CS line selected by software it is also possible to pass a @ref GPIO_PIN pin.
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@code
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI0,
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.cipo_pin = GPIO_PIN(PORT_A, 5),
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.copi_pin = GPIO_PIN(PORT_A, 4),
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.clk_pin = GPIO_PIN(PORT_A, 30),
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.cs_pin = {
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GPIO_PIN(PORT_A, 3), /* Use as SPI_HWCS(0) */
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF
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},
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},
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};
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@endcode
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@defgroup cpu_qn908x_timer NXP QN908x Standard counter/timers (CTIMER)
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@ingroup cpu_qn908x
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@brief NXP QN908x timer driver
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@ -56,6 +56,16 @@ extern "C" {
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#error "GPIO_T_ADDR(GPIO_PIN(1, x)) must be the GPIOB address"
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#endif
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/**
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* @brief Return whether the given pin is a CSHW pin.
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*/
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#define GPIO_T_IS_HWCS(pin) (((pin) & 0xff00u) == 0x8000)
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/**
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* @brief Return the given CSHW number from the gpio_t pin.
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*/
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#define GPIO_T_HWCS(pin) ((pin) & 0x0003u)
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/**
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* @brief Configure the pin mux to the given function.
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*
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@ -384,6 +384,92 @@ typedef struct {
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#define i2c_pin_scl(dev) i2c_config[dev].pin_scl
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/** @} */
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/**
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* @brief Use some common SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/** @} */
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#ifndef DOXYGEN
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/**
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* @brief Define a CPU specific SPI hardware chip select line macro
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*
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* GPIO numbers use the lower 5 bits and the bit 12. We define the CS numbers
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* to have the bit 15 set.
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*/
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#define SPI_HWCS(x) (1u << 15u | (x))
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/**
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* @brief Number of HW CS pins supported
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*/
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#define SPI_HWCS_NUMOF 4
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/**
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* @brief SPI mode select helper macro
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*
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* The polarity is determined by the bits CPOL and CPHA in the SPI CFG register.
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*/
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#define SPI_MODE_SEL(pol, pha) (SPI_CFG_CPOL(pol) | SPI_CFG_CPHA(pha))
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/**
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* @name Override the SPI mode bitmask
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*
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* Override the SPI mode value so we can use it directly as a bitmask to CFG.
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* @{
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*/
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#define HAVE_SPI_MODE_T
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typedef enum {
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SPI_MODE_0 = SPI_MODE_SEL(0, 0), /**< mode 0 */
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SPI_MODE_1 = SPI_MODE_SEL(0, 1), /**< mode 1 */
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SPI_MODE_2 = SPI_MODE_SEL(1, 0), /**< mode 2 */
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SPI_MODE_3 = SPI_MODE_SEL(1, 1) /**< mode 3 */
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} spi_mode_t;
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/** @} */
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/**
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* @name Override SPI speed values
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*
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* The speed is configured at run time based on the AHB clock speed using an
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* arbitrary divider between /1 and /65536. The standard macro values just map
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* to the frequency in Hz. The maximum possible speed is 32 MHz assuming a
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* core clock and AHB bus clock of 32 MHz.
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* @{
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = 100000u, /**< drive the SPI bus with 100KHz */
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SPI_CLK_400KHZ = 400000u, /**< drive the SPI bus with 400KHz */
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SPI_CLK_1MHZ = 1000000u, /**< drive the SPI bus with 1MHz */
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SPI_CLK_5MHZ = 5000000u, /**< drive the SPI bus with 5MHz */
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SPI_CLK_10MHZ = 10000000u /**< drive the SPI bus with 10MHz */
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} spi_clk_t;
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/** @} */
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/**
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* @brief SPI pin getters
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* @{
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*/
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#define spi_pin_mosi(bus) spi_config[bus].copi_pin
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#define spi_pin_miso(bus) spi_config[bus].cipo_pin
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#define spi_pin_clk(bus) spi_config[bus].clk_pin
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/** @} */
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/**
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* @brief SPI module configuration options
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*/
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typedef struct {
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SPI_Type *dev; /**< SPI device to use */
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gpio_t cipo_pin; /**< Controller Input Peripheral Output */
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gpio_t copi_pin; /**< Controller Output Peripheral Input */
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gpio_t clk_pin; /**< CLK pin */
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gpio_t cs_pin[SPI_HWCS_NUMOF]; /**< pins used for HW cs lines */
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} spi_conf_t;
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#endif /* ifndef DOXYGEN */
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/**
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* @brief UART module configuration options
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*
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341
cpu/qn908x/periph/spi.c
Normal file
341
cpu/qn908x/periph/spi.c
Normal file
@ -0,0 +1,341 @@
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/*
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* Copyright (C) 2020 iosabi
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_qn908x
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* @ingroup drivers_periph_spi
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*
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* @{
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*
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* @file
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* @brief Low-level SPI driver implementation
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*
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* @author iosabi <iosabi@protonmail.com>
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*
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* @}
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*/
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#include "assert.h"
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#include "bitarithm.h"
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#include "mutex.h"
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#include "cpu.h"
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#include "periph_conf.h"
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#include "periph/spi.h"
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#include "vendor/drivers/fsl_clock.h"
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#include "flexcomm.h"
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#include "gpio_mux.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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typedef struct {
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uint8_t *in; /**< The RX buffer pointer or NULL if unused. */
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uint32_t in_len; /**< The remaining bytes to receive or 0 if unused. */
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const uint8_t *out; /**< The TX buffer pointer or NULL if unused. */
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/**
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* @brief The remaining transfer length.
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*
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* This value is set even if we are not transferring any data, in which case
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* it indicates the remaining 8-bit clock pulses needed to be sent to the
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* FIFO to finish the transfer.
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*/
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uint32_t tr_len;
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uint32_t tx_mask; /** FIFOWR mask used when transmitting. */
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} spi_pending_transfer_t;
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/**
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* @brief Mutex for accessing each SPI bus.
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*/
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static mutex_t locks[SPI_NUMOF];
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/**
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* @brief Bitmask of Port A pins that use Function 4 for the FLEXCOMM2.
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*
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* SPI pins are either function 4 or 5 depending on the pin and flexcomm.
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* All FLEXCOMM3 possible pins are mapped to function 5, while in the
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* case of FLEXCOMM2 some are in function 4. Some pins can act as a function
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* in FLEXCOMM2 (function 4) while act as another function in FLEXCOM3 (function
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* 5)
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*/
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static const uint32_t _spi_func5_mask_fc2 =
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(1u << 0) | /* FC2_SSEL3 */
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(1u << 1) | /* FC2_SSEL2 */
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(1u << 2) | /* FC2_SSEL1 */
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(1u << 3) | /* FC2_SSEL0 */
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(1u << 4) | /* FC2_COPI */
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(1u << 5); /* FC2_CIPO */
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/**
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* @brief Set the clock divided for the target frequency.
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*/
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static void _spi_controller_set_speed(SPI_Type *spi_bus, uint32_t speed_hz)
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{
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/* The SPI clock source is based on the FLEXCOMM clock with a simple
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* frequency divider between /1 and /65536. */
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const uint32_t bus_freq = CLOCK_GetFreq(kCLOCK_BusClk);
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uint32_t divider = (bus_freq + speed_hz / 2) / speed_hz;
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if (divider == 0) {
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divider = 1;
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}
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else if (divider > (1u << 16)) {
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divider = 1u << 16;
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}
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DEBUG("[spi] clock requested: %" PRIu32 " Hz, actual: %" PRIu32
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" Hz, divider: /%" PRIu32 "\n", speed_hz, bus_freq / divider,
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divider);
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/* The value stored in DIV is always (divider - 1), meaning that a value of
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* 0 divides by 1. */
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spi_bus->DIV = divider - 1;
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}
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void spi_init(spi_t bus)
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{
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assert(bus < SPI_NUMOF);
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const spi_conf_t *const conf = &spi_config[bus];
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SPI_Type *const spi_bus = conf->dev;
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int flexcomm_num = flexcomm_init((FLEXCOMM_Type *)spi_bus, FLEXCOMM_ID_SPI);
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DEBUG("[spi] init: bus=%u, flexcomm=%d\n", (unsigned)bus, flexcomm_num);
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assert(flexcomm_num >= 0);
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/* Set controller mode, but don't enable it. All CS are active low. MSB
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* first bit order (standard). */
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spi_bus->CFG = SPI_CFG_MASTER_MASK;
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/* Configure to use the RX and TX FIFO. */
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spi_bus->FIFOCFG = SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK;
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locks[bus] = (mutex_t)MUTEX_INIT_LOCKED;
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spi_init_pins(bus);
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}
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void spi_init_pins(spi_t bus)
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{
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assert(bus < SPI_NUMOF);
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const spi_conf_t *const conf = &spi_config[bus];
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const uint32_t mask = conf->dev == (SPI_Type *)FLEXCOMM2_BASE
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? _spi_func5_mask_fc2
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: 0xffffffff;
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gpio_init_mux(conf->copi_pin,
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((1u << GPIO_T_PIN(conf->copi_pin)) & mask) ? 5 : 4);
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gpio_init_mux(conf->cipo_pin,
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((1u << GPIO_T_PIN(conf->cipo_pin)) & mask) ? 5 : 4);
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gpio_init_mux(conf->clk_pin,
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((1u << GPIO_T_PIN(conf->clk_pin)) & mask) ? 5 : 4);
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/* Enables the SPI block and sets it to idle. */
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conf->dev->CFG |= SPI_CFG_ENABLE_MASK;
|
||||
mutex_unlock(&locks[bus]);
|
||||
}
|
||||
|
||||
int spi_init_cs(spi_t bus, spi_cs_t cs)
|
||||
{
|
||||
/* Initializing the CS pin doesn't require to acquire the mutex since each
|
||||
* peripheral has its own independent CS pin. */
|
||||
if (bus >= SPI_NUMOF) {
|
||||
return SPI_NODEV;
|
||||
}
|
||||
const spi_conf_t *const conf = &spi_config[bus];
|
||||
gpio_t pin = cs;
|
||||
|
||||
if (GPIO_T_IS_HWCS(cs)) {
|
||||
/* The gpio_t value comes from the board config rather than the cs
|
||||
* variable itself when a HWCS number is passed. */
|
||||
pin = conf->cs_pin[GPIO_T_HWCS(cs)];
|
||||
}
|
||||
if (!gpio_is_valid(pin)) {
|
||||
return SPI_NOCS;
|
||||
}
|
||||
DEBUG("[spi] init_cs: cs=0x%.4" PRIx16 " pin=0x%.4" PRIx16 "\n", cs, pin);
|
||||
|
||||
if (GPIO_T_IS_HWCS(cs)) {
|
||||
const uint32_t mask = conf->dev == (SPI_Type *)FLEXCOMM2_BASE
|
||||
? _spi_func5_mask_fc2
|
||||
: 0xffffffff;
|
||||
gpio_init_mux(pin, ((1u << GPIO_T_PIN(pin)) & mask) ? 5 : 4);
|
||||
}
|
||||
else {
|
||||
gpio_init(pin, GPIO_OUT);
|
||||
gpio_set(pin);
|
||||
}
|
||||
|
||||
return SPI_OK;
|
||||
}
|
||||
|
||||
#ifdef MODULE_PERIPH_SPI_RECONFIGURE
|
||||
void spi_deinit_pins(spi_t bus)
|
||||
{
|
||||
assert(bus < SPI_NUMOF);
|
||||
mutex_lock(&locks[bus]);
|
||||
const spi_conf_t *const conf = &spi_config[bus];
|
||||
|
||||
/* Disables the SPI block. It must be already idle. */
|
||||
conf->dev->CFG &= ~SPI_CFG_ENABLE_MASK;
|
||||
|
||||
gpio_init(conf->copi_pin, GPIO_IN);
|
||||
gpio_init(conf->cipo_pin, GPIO_IN);
|
||||
gpio_init(conf->clk_pin, GPIO_IN);
|
||||
}
|
||||
#endif /* MODULE_PERIPH_SPI_RECONFIGURE */
|
||||
|
||||
int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
|
||||
{
|
||||
const spi_conf_t *const conf = &spi_config[bus];
|
||||
|
||||
mutex_lock(&locks[bus]);
|
||||
|
||||
/* Set SPI clock speed. This silently chooses the closest frequency, no
|
||||
* matter how far it is from the requested one. */
|
||||
_spi_controller_set_speed(conf->dev, clk);
|
||||
|
||||
if ((mode & ~(SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK)) != 0) {
|
||||
return SPI_NOMODE;
|
||||
}
|
||||
|
||||
DEBUG("[spi] acquire: mode CPHA=%d CPOL=%d, cs=0x%" PRIx32 "\n",
|
||||
!!(mode & SPI_CFG_CPHA_MASK), !!(mode & SPI_CFG_CPOL_MASK),
|
||||
(uint32_t)cs);
|
||||
|
||||
conf->dev->CFG =
|
||||
(conf->dev->CFG & ~(SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK)) | mode;
|
||||
|
||||
return SPI_OK;
|
||||
}
|
||||
|
||||
void spi_release(spi_t bus)
|
||||
{
|
||||
assert(bus < SPI_NUMOF);
|
||||
DEBUG("[spi] release\n");
|
||||
mutex_unlock(&locks[bus]);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief: Wait for the FIFO to be empty.
|
||||
*/
|
||||
static void _spi_wait_txempty(SPI_Type *spi_bus)
|
||||
{
|
||||
while (!(spi_bus->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) {}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Bitmask for the FIFOWR register with all the HWCS deasserted.
|
||||
*/
|
||||
#define SPI_HWCS_DEASSERT_ALL \
|
||||
(((1u << SPI_HWCS_NUMOF) - 1) << SPI_FIFOWR_TXSSEL0_N_SHIFT)
|
||||
|
||||
/**
|
||||
* @brief Initialize a SPI transfer given the transfer parameters.
|
||||
*/
|
||||
static void _spi_config_transfer(spi_pending_transfer_t *tr, spi_cs_t cs,
|
||||
bool cont, const void *out, void *in,
|
||||
size_t len)
|
||||
{
|
||||
tr->in = in;
|
||||
tr->in_len = in ? len : 0;
|
||||
tr->out = out;
|
||||
tr->tr_len = len;
|
||||
tr->tx_mask = SPI_HWCS_DEASSERT_ALL;
|
||||
if (GPIO_T_IS_HWCS(cs)) {
|
||||
/* Flag that the TX should assert this HWCS by clearing the bit. */
|
||||
tr->tx_mask &= ~(1u << (SPI_FIFOWR_TXSSEL0_N_SHIFT + GPIO_T_HWCS(cs)));
|
||||
if (!cont) {
|
||||
/* Flag the End of Transfer (EOT) in the mask. This will only be
|
||||
* used in the last byte. */
|
||||
tr->tx_mask |= SPI_FIFOWR_EOT_MASK;
|
||||
}
|
||||
}
|
||||
if (!in) {
|
||||
/* Ignores the RX side when the @p in is NULL so we don't need to read
|
||||
* the FIFO at all. */
|
||||
tr->tx_mask |= SPI_FIFOWR_RXIGNORE_MASK;
|
||||
}
|
||||
tr->tx_mask |= SPI_FIFOWR_LEN(7); /* Data transfers of 8 bits. */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform a blocking SPI transfer.
|
||||
*/
|
||||
static void _spi_transfer_blocking(spi_t bus, spi_pending_transfer_t *tr)
|
||||
{
|
||||
SPI_Type *const spi_bus = spi_config[bus].dev;
|
||||
|
||||
/* Configure to use the RX and TX fifo, and empty them. */
|
||||
spi_bus->FIFOCFG = SPI_FIFOCFG_ENABLETX_MASK
|
||||
| SPI_FIFOCFG_ENABLERX_MASK
|
||||
| SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
|
||||
spi_bus->FIFOSTAT = SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
|
||||
|
||||
while (tr->in_len || tr->tr_len) {
|
||||
/* Read from RX FIFO if possible. */
|
||||
if (spi_bus->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) {
|
||||
uint32_t rd = spi_bus->FIFORD;
|
||||
if (tr->in_len) {
|
||||
*(tr->in++) = (uint8_t)rd;
|
||||
tr->in_len--;
|
||||
}
|
||||
}
|
||||
|
||||
/* Write when able to write and we have data to send or bogus (0) bytes
|
||||
* to send when in receive-only mode. */
|
||||
if ((spi_bus->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && tr->tr_len) {
|
||||
uint32_t wr = tr->tx_mask;
|
||||
if (tr->out) {
|
||||
wr |= *(tr->out++);
|
||||
}
|
||||
|
||||
/* If this is *not* the last byte, remove the EOT flag if any. */
|
||||
tr->tr_len--;
|
||||
if (tr->tr_len) {
|
||||
wr &= ~SPI_FIFOWR_EOT_MASK;
|
||||
}
|
||||
/* Push the data to the FIFO. */
|
||||
spi_bus->FIFOWR = wr;
|
||||
}
|
||||
}
|
||||
_spi_wait_txempty(spi_bus);
|
||||
}
|
||||
|
||||
void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
|
||||
const void *out, void *in, size_t len)
|
||||
{
|
||||
spi_pending_transfer_t tr;
|
||||
|
||||
_spi_config_transfer(&tr, cs, cont, out, in, len);
|
||||
|
||||
/* At least one of input or one output buffer is given */
|
||||
assert(bus < SPI_NUMOF);
|
||||
|
||||
if (!GPIO_T_IS_HWCS(cs)) {
|
||||
/* Assert CS using a gpio. */
|
||||
gpio_clear((gpio_t)cs);
|
||||
}
|
||||
|
||||
DEBUG("[spi] transfer: cs=0x%.4" PRIx16 " cont=%d len=%" PRIu32 "\n",
|
||||
cs, cont, (uint32_t)len);
|
||||
_spi_transfer_blocking(bus, &tr);
|
||||
|
||||
/* Deassert the CS only in gpio mode. HWCS deassert are handled by the
|
||||
* hardware when EOT is set in the mask. */
|
||||
if (!cont && !GPIO_T_IS_HWCS(cs)) {
|
||||
gpio_set((gpio_t)cs);
|
||||
}
|
||||
}
|
||||
|
||||
/* ISR routine called for FLEXCOMM devices configured as SPI. */
|
||||
void isr_flexcomm_spi(USART_Type *dev, uint32_t flexcomm_num)
|
||||
{
|
||||
// TODO: Set up async mode with interrupts.
|
||||
(void)dev;
|
||||
(void)flexcomm_num;
|
||||
|
||||
cortexm_isr_end();
|
||||
}
|
||||
@ -30,11 +30,11 @@
|
||||
|
||||
/* SPI bus speed and mode */
|
||||
#define BUS_CLK SPI_CLK_5MHZ
|
||||
#define MODE SPI_MODE_0
|
||||
#define BUS_MODE SPI_MODE_0
|
||||
#define BUS_OK SPI_OK
|
||||
/* shortcuts for SPI bus parameters */
|
||||
#define BUS (dev->p->spi)
|
||||
#define CS (dev->p->cs)
|
||||
#define BUS_CS (dev->p->cs)
|
||||
/* flag to set when reading from the device */
|
||||
#define FLAG_READ (0x80)
|
||||
/* flag to enable address auto incrementation on read or write */
|
||||
@ -43,7 +43,7 @@
|
||||
static int _init_bus(const lis2dh12_t *dev)
|
||||
{
|
||||
/* for SPI, we only need to initialize the chip select pin */
|
||||
if (spi_init_cs(BUS, CS) != SPI_OK) {
|
||||
if (spi_init_cs(BUS, BUS_CS) != SPI_OK) {
|
||||
return LIS2DH12_NOBUS;
|
||||
}
|
||||
return LIS2DH12_OK;
|
||||
@ -51,7 +51,7 @@ static int _init_bus(const lis2dh12_t *dev)
|
||||
|
||||
static int _acquire(const lis2dh12_t *dev)
|
||||
{
|
||||
return spi_acquire(BUS, CS, MODE, BUS_CLK);
|
||||
return spi_acquire(BUS, BUS_CS, BUS_MODE, BUS_CLK);
|
||||
}
|
||||
|
||||
static void _release(const lis2dh12_t *dev)
|
||||
@ -61,19 +61,19 @@ static void _release(const lis2dh12_t *dev)
|
||||
|
||||
static uint8_t _read(const lis2dh12_t *dev, uint8_t reg)
|
||||
{
|
||||
return spi_transfer_reg(BUS, CS, (FLAG_READ | reg), 0);
|
||||
return spi_transfer_reg(BUS, BUS_CS, (FLAG_READ | reg), 0);
|
||||
}
|
||||
|
||||
static void _read_burst(const lis2dh12_t *dev, uint8_t reg,
|
||||
void *data, size_t len)
|
||||
{
|
||||
spi_transfer_regs(BUS, CS, (FLAG_READ | FLAG_AINC | reg), NULL, data, len);
|
||||
static void _read_burst(const lis2dh12_t *dev, uint8_t reg, void *data,
|
||||
size_t len) {
|
||||
spi_transfer_regs(BUS, BUS_CS, (FLAG_READ | FLAG_AINC | reg), NULL, data,
|
||||
len);
|
||||
}
|
||||
|
||||
static void _write(const lis2dh12_t *dev, uint8_t reg, uint8_t data)
|
||||
{
|
||||
DEBUG("[lis2dh12] write: reg 0x%02x, val 0x%02x\n", (int)reg, (int)data);
|
||||
spi_transfer_reg(BUS, CS, reg, data);
|
||||
spi_transfer_reg(BUS, BUS_CS, reg, data);
|
||||
}
|
||||
|
||||
/* and now the I2C specific part of the driver */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user