cpu/efm32: add support for efm32hg family

cpu/efm32/Makefile

@@ -7,6 +7,9 @@ DIRS += $(RIOTCPU)/cortexm_common
 ifneq (,$(filter cpu_efm32gg,$(USEMODULE)))
   DIRS += families/efm32gg
 endif
+ifneq (,$(filter cpu_efm32hg,$(USEMODULE)))
+  DIRS += families/efm32hg
+endif
 ifneq (,$(filter cpu_efm32lg,$(USEMODULE)))
   DIRS += families/efm32lg
 endif

cpu/efm32/doc.txt

@@ -76,6 +76,12 @@
  * @brief           Silicon Labs's EFM32GG MCUs family implementation
  */
 
+/**
+ * @defgroup        cpu_efm32hg Silicon Labs EFM32HG family
+ * @ingroup         cpu_efm32
+ * @brief           Silicon Labs's EFM32HG MCUs family implementation
+ */
+
 /**
  * @defgroup        cpu_efm32lg Silicon Labs EFM32LG family
  * @ingroup         cpu_efm32

cpu/efm32/families/efm32hg/Kconfig

@@ -0,0 +1,118 @@
+# Copyright (c) 2020 HAW Hamburg
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+
+config CPU_FAM_EFM32HG
+    bool
+    select CPU_CORE_CORTEX_M0PLUS
+    select CPU_COMMON_EFM32
+    select CPU_EFM32_SERIES0
+
+## CPU Models
+config CPU_MODEL_EFM32HG210F32
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG322F32
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG110F64
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG350F64
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG310F64
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG222F64
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG308F32
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG321F64
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG309F32
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG108F32
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG222F32
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG310F32
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG322F64
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG110F32
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG350F32
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG210F64
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG309F64
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG108F64
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG321F32
+    bool
+    select CPU_FAM_EFM32HG
+
+config CPU_MODEL_EFM32HG308F64
+    bool
+    select CPU_FAM_EFM32HG
+
+## Common CPU symbols
+config CPU_FAM
+    default "efm32hg" if CPU_FAM_EFM32HG
+
+config CPU_MODEL
+    default "efm32hg210f32" if CPU_MODEL_EFM32HG210F32
+    default "efm32hg322f32" if CPU_MODEL_EFM32HG322F32
+    default "efm32hg110f64" if CPU_MODEL_EFM32HG110F64
+    default "efm32hg350f64" if CPU_MODEL_EFM32HG350F64
+    default "efm32hg310f64" if CPU_MODEL_EFM32HG310F64
+    default "efm32hg222f64" if CPU_MODEL_EFM32HG222F64
+    default "efm32hg308f32" if CPU_MODEL_EFM32HG308F32
+    default "efm32hg321f64" if CPU_MODEL_EFM32HG321F64
+    default "efm32hg309f32" if CPU_MODEL_EFM32HG309F32
+    default "efm32hg108f32" if CPU_MODEL_EFM32HG108F32
+    default "efm32hg222f32" if CPU_MODEL_EFM32HG222F32
+    default "efm32hg310f32" if CPU_MODEL_EFM32HG310F32
+    default "efm32hg322f64" if CPU_MODEL_EFM32HG322F64
+    default "efm32hg110f32" if CPU_MODEL_EFM32HG110F32
+    default "efm32hg350f32" if CPU_MODEL_EFM32HG350F32
+    default "efm32hg210f64" if CPU_MODEL_EFM32HG210F64
+    default "efm32hg309f64" if CPU_MODEL_EFM32HG309F64
+    default "efm32hg108f64" if CPU_MODEL_EFM32HG108F64
+    default "efm32hg321f32" if CPU_MODEL_EFM32HG321F32
+    default "efm32hg308f64" if CPU_MODEL_EFM32HG308F64

cpu/efm32/families/efm32hg/Makefile

@@ -0,0 +1,6 @@
+MODULE = cpu_efm32hg
+
+# (file triggers compiler bug. see #5775)
+SRC_NOLTO += vectors.c
+
+include $(RIOTBASE)/Makefile.base

cpu/efm32/families/efm32hg/Makefile.include

@@ -0,0 +1,7 @@
+# Find the header file that should exist if the CPU is supported. Only headers
+# for supported boards are included, but to support another CPU, it should be
+# as easy as adding the header file only.
+EFM32_HEADER = $(wildcard $(RIOTCPU)/efm32/families/efm32hg/include/vendor/$(CPU_MODEL).h)
+
+# include vendor device headers
+INCLUDES += -I$(RIOTCPU)/efm32/families/efm32hg/include/vendor

cpu/efm32/families/efm32hg/efm32-info.mk

@@ -0,0 +1,25 @@
+# This file is automatically generated, and should not be changed. There is
+# probably little reason to edit this file anyway, since it should already
+# contain all information for the EFM32HG family of CPUs.
+
+# Series - Architecture - Flash base - Flash size - SRAM base - SRAM size - Crypto? - TRNG? - Radio?
+EFM32_INFO_efm32hg210f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00001000 0 0 0
+EFM32_INFO_efm32hg322f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg110f64 = 0 cortex-m0plus 0x00000000 0x00010000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg350f64 = 0 cortex-m0plus 0x00000000 0x00010000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg310f64 = 0 cortex-m0plus 0x00000000 0x00010000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg222f64 = 0 cortex-m0plus 0x00000000 0x00010000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg308f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg321f64 = 0 cortex-m0plus 0x00000000 0x00010000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg309f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg108f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00001000 0 0 0
+EFM32_INFO_efm32hg222f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00001000 0 0 0
+EFM32_INFO_efm32hg310f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg322f64 = 0 cortex-m0plus 0x00000000 0x00010000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg110f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00001000 0 0 0
+EFM32_INFO_efm32hg350f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg210f64 = 0 cortex-m0plus 0x00000000 0x00010000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg309f64 = 0 cortex-m0plus 0x00000000 0x00010000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg108f64 = 0 cortex-m0plus 0x00000000 0x00010000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg321f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00002000 0 0 0
+EFM32_INFO_efm32hg308f64 = 0 cortex-m0plus 0x00000000 0x00010000 0x20000000 0x00002000 0 0 0

cpu/efm32/families/efm32hg/include/vendor/efm32hg309f32.h

@@ -0,0 +1,410 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32HG309F32
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+#ifndef EFM32HG309F32_H
+#define EFM32HG309F32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F32 EFM32HG309F32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
+  NonMaskableInt_IRQn = -14,                /*!< -14 Cortex-M0+ Non Maskable Interrupt   */
+  HardFault_IRQn      = -13,                /*!< -13 Cortex-M0+ Hard Fault Interrupt     */
+  SVCall_IRQn         = -5,                 /*!< -5  Cortex-M0+ SV Call Interrupt        */
+  PendSV_IRQn         = -2,                 /*!< -2  Cortex-M0+ Pend SV Interrupt        */
+  SysTick_IRQn        = -1,                 /*!< -1  Cortex-M0+ System Tick Interrupt    */
+
+/******  EFM32HG Peripheral Interrupt Numbers ********************************************/
+  DMA_IRQn            = 0,  /*!< 0 EFM32 DMA Interrupt */
+  GPIO_EVEN_IRQn      = 1,  /*!< 1 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn         = 2,  /*!< 2 EFM32 TIMER0 Interrupt */
+  ACMP0_IRQn          = 3,  /*!< 3 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn           = 4,  /*!< 4 EFM32 ADC0 Interrupt */
+  I2C0_IRQn           = 5,  /*!< 5 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn       = 6,  /*!< 6 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn         = 7,  /*!< 7 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn      = 8,  /*!< 8 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn      = 9,  /*!< 9 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn        = 10, /*!< 10 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn          = 11, /*!< 11 EFM32 PCNT0 Interrupt */
+  RTC_IRQn            = 12, /*!< 12 EFM32 RTC Interrupt */
+  CMU_IRQn            = 13, /*!< 13 EFM32 CMU Interrupt */
+  VCMP_IRQn           = 14, /*!< 14 EFM32 VCMP Interrupt */
+  MSC_IRQn            = 15, /*!< 15 EFM32 MSC Interrupt */
+  AES_IRQn            = 16, /*!< 16 EFM32 AES Interrupt */
+  USART0_RX_IRQn      = 17, /*!< 17 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn      = 18, /*!< 18 EFM32 USART0_TX Interrupt */
+  USB_IRQn            = 19, /*!< 19 EFM32 USB Interrupt */
+  TIMER2_IRQn         = 20, /*!< 20 EFM32 TIMER2 Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F32_Core EFM32HG309F32 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT             0U /**< MPU not present */
+#define __VTOR_PRESENT            1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS          2U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32HG309F32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F32_Part EFM32HG309F32 Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFM32_HAPPY_FAMILY                     1  /**< Happy Gecko EFM32HG MCU Family */
+#define _EFM_DEVICE                                /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_SERIES_0                 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES                0  /**< Silicon Labs series number */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID       77 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_77       /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_PLATFORM_1               /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM              1  /**< @deprecated Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32HG309F32)
+#define EFM32HG309F32    1 /**< Happy Gecko Part  */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER          "EFM32HG309F32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define RAM_MEM_BASE         (0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE         (0x40000UL)    /**< RAM available address space  */
+#define RAM_MEM_END          (0x2003FFFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS         (0x18UL)       /**< RAM used bits  */
+#define DEVICE_MEM_BASE      (0xF0040000UL) /**< DEVICE base address  */
+#define DEVICE_MEM_SIZE      (0x1000UL)     /**< DEVICE available address space  */
+#define DEVICE_MEM_END       (0xF0040FFFUL) /**< DEVICE end address  */
+#define DEVICE_MEM_BITS      (0x12UL)       /**< DEVICE used bits  */
+#define USBC_MEM_BASE        (0x40100000UL) /**< USBC base address  */
+#define USBC_MEM_SIZE        (0x40000UL)    /**< USBC available address space  */
+#define USBC_MEM_END         (0x4013FFFFUL) /**< USBC end address  */
+#define USBC_MEM_BITS        (0x18UL)       /**< USBC used bits  */
+#define RAM_CODE_MEM_BASE    (0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE    (0x20000UL)    /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END     (0x1001FFFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS    (0x17UL)       /**< RAM_CODE used bits  */
+#define PER_MEM_BASE         (0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE         (0xE0000UL)    /**< PER available address space  */
+#define PER_MEM_END          (0x400DFFFFUL) /**< PER end address  */
+#define PER_MEM_BITS         (0x20UL)       /**< PER used bits  */
+#define FLASH_MEM_BASE       (0x0UL)        /**< FLASH base address  */
+#define FLASH_MEM_SIZE       (0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END        (0xFFFFFFFUL)  /**< FLASH end address  */
+#define FLASH_MEM_BITS       (0x28UL)       /**< FLASH used bits  */
+#define AES_MEM_BASE         (0x400E0000UL) /**< AES base address  */
+#define AES_MEM_SIZE         (0x400UL)      /**< AES available address space  */
+#define AES_MEM_END          (0x400E03FFUL) /**< AES end address  */
+#define AES_MEM_BITS         (0x10UL)       /**< AES used bits  */
+
+/** Flash and SRAM limits for EFM32HG309F32 */
+#define FLASH_BASE           (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE           (0x00008000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE      1024U          /**< Flash Memory page size */
+#define SRAM_BASE            (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE            (0x00002000UL) /**< Available SRAM Memory */
+#define __CM0PLUS_REV        0x0001U        /**< Cortex-M0+ Core revision r0p1 */
+#define PRS_CHAN_COUNT       6              /**< Number of PRS channels */
+#define DMA_CHAN_COUNT       6              /**< Number of DMA channels */
+#define EXT_IRQ_COUNT        21             /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX           42U
+#define AFCHANLOC_MAX        7U
+/** Analog AF channels */
+#define AFACHAN_MAX          27U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT           /**< TIMER is available in this part */
+#define TIMER_COUNT           3 /**< 3 TIMERs available  */
+#define ACMP_PRESENT            /**< ACMP is available in this part */
+#define ACMP_COUNT            1 /**< 1 ACMPs available  */
+#define USART_PRESENT           /**< USART is available in this part */
+#define USART_COUNT           2 /**< 2 USARTs available  */
+#define IDAC_PRESENT            /**< IDAC is available in this part */
+#define IDAC_COUNT            1 /**< 1 IDACs available  */
+#define ADC_PRESENT             /**< ADC is available in this part */
+#define ADC_COUNT             1 /**< 1 ADCs available  */
+#define LEUART_PRESENT          /**< LEUART is available in this part */
+#define LEUART_COUNT          1 /**< 1 LEUARTs available  */
+#define PCNT_PRESENT            /**< PCNT is available in this part */
+#define PCNT_COUNT            1 /**< 1 PCNTs available  */
+#define I2C_PRESENT             /**< I2C is available in this part */
+#define I2C_COUNT             1 /**< 1 I2Cs available  */
+#define AES_PRESENT             /**< AES is available in this part */
+#define AES_COUNT             1 /**< 1 AES available */
+#define DMA_PRESENT             /**< DMA is available in this part */
+#define DMA_COUNT             1 /**< 1 DMA available */
+#define LE_PRESENT              /**< LE is available in this part */
+#define LE_COUNT              1 /**< 1 LE available */
+#define USBC_PRESENT            /**< USBC is available in this part */
+#define USBC_COUNT            1 /**< 1 USBC available */
+#define USBLE_PRESENT           /**< USBLE is available in this part */
+#define USBLE_COUNT           1 /**< 1 USBLE available */
+#define USB_PRESENT             /**< USB is available in this part */
+#define USB_COUNT             1 /**< 1 USB available */
+#define MSC_PRESENT             /**< MSC is available in this part */
+#define MSC_COUNT             1 /**< 1 MSC available */
+#define EMU_PRESENT             /**< EMU is available in this part */
+#define EMU_COUNT             1 /**< 1 EMU available */
+#define RMU_PRESENT             /**< RMU is available in this part */
+#define RMU_COUNT             1 /**< 1 RMU available */
+#define CMU_PRESENT             /**< CMU is available in this part */
+#define CMU_COUNT             1 /**< 1 CMU available */
+#define PRS_PRESENT             /**< PRS is available in this part */
+#define PRS_COUNT             1 /**< 1 PRS available */
+#define GPIO_PRESENT            /**< GPIO is available in this part */
+#define GPIO_COUNT            1 /**< 1 GPIO available */
+#define VCMP_PRESENT            /**< VCMP is available in this part */
+#define VCMP_COUNT            1 /**< 1 VCMP available */
+#define RTC_PRESENT             /**< RTC is available in this part */
+#define RTC_COUNT             1 /**< 1 RTC available */
+#define HFXTAL_PRESENT          /**< HFXTAL is available in this part */
+#define HFXTAL_COUNT          1 /**< 1 HFXTAL available */
+#define LFXTAL_PRESENT          /**< LFXTAL is available in this part */
+#define LFXTAL_COUNT          1 /**< 1 LFXTAL available */
+#define USHFRCO_PRESENT         /**< USHFRCO is available in this part */
+#define USHFRCO_COUNT         1 /**< 1 USHFRCO available */
+#define WDOG_PRESENT            /**< WDOG is available in this part */
+#define WDOG_COUNT            1 /**< 1 WDOG available */
+#define DBG_PRESENT             /**< DBG is available in this part */
+#define DBG_COUNT             1 /**< 1 DBG available */
+#define MTB_PRESENT             /**< MTB is available in this part */
+#define MTB_COUNT             1 /**< 1 MTB available */
+#define BOOTLOADER_PRESENT      /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT      1 /**< 1 BOOTLOADER available */
+#define ANALOG_PRESENT          /**< ANALOG is available in this part */
+#define ANALOG_COUNT          1 /**< 1 ANALOG available */
+
+/** @} End of group EFM32HG309F32_Part */
+
+#ifndef ARM_MATH_CM0PLUS
+#define ARM_MATH_CM0PLUS
+#endif
+#include "arm_math.h"     /* To get __CLZ definitions etc. */
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_efm32hg.h" /* System Header */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F32_Peripheral_TypeDefs EFM32HG309F32 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efm32hg_aes.h"
+#include "efm32hg_dma_ch.h"
+#include "efm32hg_dma.h"
+#include "efm32hg_usb_diep.h"
+#include "efm32hg_usb_doep.h"
+#include "efm32hg_usb.h"
+#include "efm32hg_msc.h"
+#include "efm32hg_emu.h"
+#include "efm32hg_rmu.h"
+#include "efm32hg_cmu.h"
+#include "efm32hg_timer_cc.h"
+#include "efm32hg_timer.h"
+#include "efm32hg_acmp.h"
+#include "efm32hg_usart.h"
+#include "efm32hg_prs_ch.h"
+#include "efm32hg_prs.h"
+#include "efm32hg_idac.h"
+#include "efm32hg_gpio_p.h"
+#include "efm32hg_gpio.h"
+#include "efm32hg_vcmp.h"
+#include "efm32hg_adc.h"
+#include "efm32hg_leuart.h"
+#include "efm32hg_pcnt.h"
+#include "efm32hg_i2c.h"
+#include "efm32hg_rtc.h"
+#include "efm32hg_wdog.h"
+#include "efm32hg_mtb.h"
+#include "efm32hg_dma_descriptor.h"
+#include "efm32hg_devinfo.h"
+#include "efm32hg_romtable.h"
+#include "efm32hg_calibrate.h"
+
+/** @} End of group EFM32HG309F32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F32_Peripheral_Base EFM32HG309F32 Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define AES_BASE          (0x400E0000UL) /**< AES base address  */
+#define DMA_BASE          (0x400C2000UL) /**< DMA base address  */
+#define USB_BASE          (0x400C4000UL) /**< USB base address  */
+#define MSC_BASE          (0x400C0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400C6000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400CA000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400C8000UL) /**< CMU base address  */
+#define TIMER0_BASE       (0x40010000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40010400UL) /**< TIMER1 base address  */
+#define TIMER2_BASE       (0x40010800UL) /**< TIMER2 base address  */
+#define ACMP0_BASE        (0x40001000UL) /**< ACMP0 base address  */
+#define USART0_BASE       (0x4000C000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x4000C400UL) /**< USART1 base address  */
+#define PRS_BASE          (0x400CC000UL) /**< PRS base address  */
+#define IDAC0_BASE        (0x40004000UL) /**< IDAC0 base address  */
+#define GPIO_BASE         (0x40006000UL) /**< GPIO base address  */
+#define VCMP_BASE         (0x40000000UL) /**< VCMP base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define LEUART0_BASE      (0x40084000UL) /**< LEUART0 base address  */
+#define PCNT0_BASE        (0x40086000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000A000UL) /**< I2C0 base address  */
+#define RTC_BASE          (0x40080000UL) /**< RTC base address  */
+#define WDOG_BASE         (0x40088000UL) /**< WDOG base address  */
+#define MTB_BASE          (0xF0040000UL) /**< MTB base address  */
+#define CALIBRATE_BASE    (0x0FE08000UL) /**< CALIBRATE base address */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xF00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32HG309F32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F32_Peripheral_Declaration  EFM32HG309F32 Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define AES          ((AES_TypeDef *) AES_BASE)             /**< AES base pointer */
+#define DMA          ((DMA_TypeDef *) DMA_BASE)             /**< DMA base pointer */
+#define USB          ((USB_TypeDef *) USB_BASE)             /**< USB base pointer */
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        /**< TIMER2 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           /**< VCMP base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define RTC          ((RTC_TypeDef *) RTC_BASE)             /**< RTC base pointer */
+#define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           /**< WDOG base pointer */
+#define MTB          ((MTB_TypeDef *) MTB_BASE)             /**< MTB base pointer */
+#define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32HG309F32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F32_BitFields EFM32HG309F32 Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_prs_signals.h"
+#include "efm32hg_dmareq.h"
+#include "efm32hg_dmactrl.h"
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F32_UNLOCK EFM32HG309F32 Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+
+/** @} End of group EFM32HG309F32_UNLOCK */
+
+/** @} End of group EFM32HG309F32_BitFields */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F32_Alternate_Function EFM32HG309F32 Alternate Function
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_af_ports.h"
+#include "efm32hg_af_pins.h"
+
+/** @} End of group EFM32HG309F32_Alternate_Function */
+
+/***************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32HG309F32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFM32HG309F32_H */

cpu/efm32/families/efm32hg/include/vendor/efm32hg309f64.h

@@ -0,0 +1,410 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32HG309F64
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+#ifndef EFM32HG309F64_H
+#define EFM32HG309F64_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F64 EFM32HG309F64
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
+  NonMaskableInt_IRQn = -14,                /*!< -14 Cortex-M0+ Non Maskable Interrupt   */
+  HardFault_IRQn      = -13,                /*!< -13 Cortex-M0+ Hard Fault Interrupt     */
+  SVCall_IRQn         = -5,                 /*!< -5  Cortex-M0+ SV Call Interrupt        */
+  PendSV_IRQn         = -2,                 /*!< -2  Cortex-M0+ Pend SV Interrupt        */
+  SysTick_IRQn        = -1,                 /*!< -1  Cortex-M0+ System Tick Interrupt    */
+
+/******  EFM32HG Peripheral Interrupt Numbers ********************************************/
+  DMA_IRQn            = 0,  /*!< 0 EFM32 DMA Interrupt */
+  GPIO_EVEN_IRQn      = 1,  /*!< 1 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn         = 2,  /*!< 2 EFM32 TIMER0 Interrupt */
+  ACMP0_IRQn          = 3,  /*!< 3 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn           = 4,  /*!< 4 EFM32 ADC0 Interrupt */
+  I2C0_IRQn           = 5,  /*!< 5 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn       = 6,  /*!< 6 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn         = 7,  /*!< 7 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn      = 8,  /*!< 8 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn      = 9,  /*!< 9 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn        = 10, /*!< 10 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn          = 11, /*!< 11 EFM32 PCNT0 Interrupt */
+  RTC_IRQn            = 12, /*!< 12 EFM32 RTC Interrupt */
+  CMU_IRQn            = 13, /*!< 13 EFM32 CMU Interrupt */
+  VCMP_IRQn           = 14, /*!< 14 EFM32 VCMP Interrupt */
+  MSC_IRQn            = 15, /*!< 15 EFM32 MSC Interrupt */
+  AES_IRQn            = 16, /*!< 16 EFM32 AES Interrupt */
+  USART0_RX_IRQn      = 17, /*!< 17 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn      = 18, /*!< 18 EFM32 USART0_TX Interrupt */
+  USB_IRQn            = 19, /*!< 19 EFM32 USB Interrupt */
+  TIMER2_IRQn         = 20, /*!< 20 EFM32 TIMER2 Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F64_Core EFM32HG309F64 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT             0U /**< MPU not present */
+#define __VTOR_PRESENT            1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS          2U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32HG309F64_Core */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F64_Part EFM32HG309F64 Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFM32_HAPPY_FAMILY                     1  /**< Happy Gecko EFM32HG MCU Family */
+#define _EFM_DEVICE                                /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_SERIES_0                 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES                0  /**< Silicon Labs series number */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID       77 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_77       /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_PLATFORM_1               /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM              1  /**< @deprecated Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32HG309F64)
+#define EFM32HG309F64    1 /**< Happy Gecko Part  */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER          "EFM32HG309F64" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define RAM_MEM_BASE         (0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE         (0x40000UL)    /**< RAM available address space  */
+#define RAM_MEM_END          (0x2003FFFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS         (0x18UL)       /**< RAM used bits  */
+#define DEVICE_MEM_BASE      (0xF0040000UL) /**< DEVICE base address  */
+#define DEVICE_MEM_SIZE      (0x1000UL)     /**< DEVICE available address space  */
+#define DEVICE_MEM_END       (0xF0040FFFUL) /**< DEVICE end address  */
+#define DEVICE_MEM_BITS      (0x12UL)       /**< DEVICE used bits  */
+#define USBC_MEM_BASE        (0x40100000UL) /**< USBC base address  */
+#define USBC_MEM_SIZE        (0x40000UL)    /**< USBC available address space  */
+#define USBC_MEM_END         (0x4013FFFFUL) /**< USBC end address  */
+#define USBC_MEM_BITS        (0x18UL)       /**< USBC used bits  */
+#define RAM_CODE_MEM_BASE    (0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE    (0x20000UL)    /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END     (0x1001FFFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS    (0x17UL)       /**< RAM_CODE used bits  */
+#define PER_MEM_BASE         (0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE         (0xE0000UL)    /**< PER available address space  */
+#define PER_MEM_END          (0x400DFFFFUL) /**< PER end address  */
+#define PER_MEM_BITS         (0x20UL)       /**< PER used bits  */
+#define FLASH_MEM_BASE       (0x0UL)        /**< FLASH base address  */
+#define FLASH_MEM_SIZE       (0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END        (0xFFFFFFFUL)  /**< FLASH end address  */
+#define FLASH_MEM_BITS       (0x28UL)       /**< FLASH used bits  */
+#define AES_MEM_BASE         (0x400E0000UL) /**< AES base address  */
+#define AES_MEM_SIZE         (0x400UL)      /**< AES available address space  */
+#define AES_MEM_END          (0x400E03FFUL) /**< AES end address  */
+#define AES_MEM_BITS         (0x10UL)       /**< AES used bits  */
+
+/** Flash and SRAM limits for EFM32HG309F64 */
+#define FLASH_BASE           (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE           (0x00010000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE      1024U          /**< Flash Memory page size */
+#define SRAM_BASE            (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE            (0x00002000UL) /**< Available SRAM Memory */
+#define __CM0PLUS_REV        0x0001U        /**< Cortex-M0+ Core revision r0p1 */
+#define PRS_CHAN_COUNT       6              /**< Number of PRS channels */
+#define DMA_CHAN_COUNT       6              /**< Number of DMA channels */
+#define EXT_IRQ_COUNT        21             /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX           42U
+#define AFCHANLOC_MAX        7U
+/** Analog AF channels */
+#define AFACHAN_MAX          27U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT           /**< TIMER is available in this part */
+#define TIMER_COUNT           3 /**< 3 TIMERs available  */
+#define ACMP_PRESENT            /**< ACMP is available in this part */
+#define ACMP_COUNT            1 /**< 1 ACMPs available  */
+#define USART_PRESENT           /**< USART is available in this part */
+#define USART_COUNT           2 /**< 2 USARTs available  */
+#define IDAC_PRESENT            /**< IDAC is available in this part */
+#define IDAC_COUNT            1 /**< 1 IDACs available  */
+#define ADC_PRESENT             /**< ADC is available in this part */
+#define ADC_COUNT             1 /**< 1 ADCs available  */
+#define LEUART_PRESENT          /**< LEUART is available in this part */
+#define LEUART_COUNT          1 /**< 1 LEUARTs available  */
+#define PCNT_PRESENT            /**< PCNT is available in this part */
+#define PCNT_COUNT            1 /**< 1 PCNTs available  */
+#define I2C_PRESENT             /**< I2C is available in this part */
+#define I2C_COUNT             1 /**< 1 I2Cs available  */
+#define AES_PRESENT             /**< AES is available in this part */
+#define AES_COUNT             1 /**< 1 AES available */
+#define DMA_PRESENT             /**< DMA is available in this part */
+#define DMA_COUNT             1 /**< 1 DMA available */
+#define LE_PRESENT              /**< LE is available in this part */
+#define LE_COUNT              1 /**< 1 LE available */
+#define USBC_PRESENT            /**< USBC is available in this part */
+#define USBC_COUNT            1 /**< 1 USBC available */
+#define USBLE_PRESENT           /**< USBLE is available in this part */
+#define USBLE_COUNT           1 /**< 1 USBLE available */
+#define USB_PRESENT             /**< USB is available in this part */
+#define USB_COUNT             1 /**< 1 USB available */
+#define MSC_PRESENT             /**< MSC is available in this part */
+#define MSC_COUNT             1 /**< 1 MSC available */
+#define EMU_PRESENT             /**< EMU is available in this part */
+#define EMU_COUNT             1 /**< 1 EMU available */
+#define RMU_PRESENT             /**< RMU is available in this part */
+#define RMU_COUNT             1 /**< 1 RMU available */
+#define CMU_PRESENT             /**< CMU is available in this part */
+#define CMU_COUNT             1 /**< 1 CMU available */
+#define PRS_PRESENT             /**< PRS is available in this part */
+#define PRS_COUNT             1 /**< 1 PRS available */
+#define GPIO_PRESENT            /**< GPIO is available in this part */
+#define GPIO_COUNT            1 /**< 1 GPIO available */
+#define VCMP_PRESENT            /**< VCMP is available in this part */
+#define VCMP_COUNT            1 /**< 1 VCMP available */
+#define RTC_PRESENT             /**< RTC is available in this part */
+#define RTC_COUNT             1 /**< 1 RTC available */
+#define HFXTAL_PRESENT          /**< HFXTAL is available in this part */
+#define HFXTAL_COUNT          1 /**< 1 HFXTAL available */
+#define LFXTAL_PRESENT          /**< LFXTAL is available in this part */
+#define LFXTAL_COUNT          1 /**< 1 LFXTAL available */
+#define USHFRCO_PRESENT         /**< USHFRCO is available in this part */
+#define USHFRCO_COUNT         1 /**< 1 USHFRCO available */
+#define WDOG_PRESENT            /**< WDOG is available in this part */
+#define WDOG_COUNT            1 /**< 1 WDOG available */
+#define DBG_PRESENT             /**< DBG is available in this part */
+#define DBG_COUNT             1 /**< 1 DBG available */
+#define MTB_PRESENT             /**< MTB is available in this part */
+#define MTB_COUNT             1 /**< 1 MTB available */
+#define BOOTLOADER_PRESENT      /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT      1 /**< 1 BOOTLOADER available */
+#define ANALOG_PRESENT          /**< ANALOG is available in this part */
+#define ANALOG_COUNT          1 /**< 1 ANALOG available */
+
+/** @} End of group EFM32HG309F64_Part */
+
+#ifndef ARM_MATH_CM0PLUS
+#define ARM_MATH_CM0PLUS
+#endif
+#include "arm_math.h"     /* To get __CLZ definitions etc. */
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_efm32hg.h" /* System Header */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F64_Peripheral_TypeDefs EFM32HG309F64 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efm32hg_aes.h"
+#include "efm32hg_dma_ch.h"
+#include "efm32hg_dma.h"
+#include "efm32hg_usb_diep.h"
+#include "efm32hg_usb_doep.h"
+#include "efm32hg_usb.h"
+#include "efm32hg_msc.h"
+#include "efm32hg_emu.h"
+#include "efm32hg_rmu.h"
+#include "efm32hg_cmu.h"
+#include "efm32hg_timer_cc.h"
+#include "efm32hg_timer.h"
+#include "efm32hg_acmp.h"
+#include "efm32hg_usart.h"
+#include "efm32hg_prs_ch.h"
+#include "efm32hg_prs.h"
+#include "efm32hg_idac.h"
+#include "efm32hg_gpio_p.h"
+#include "efm32hg_gpio.h"
+#include "efm32hg_vcmp.h"
+#include "efm32hg_adc.h"
+#include "efm32hg_leuart.h"
+#include "efm32hg_pcnt.h"
+#include "efm32hg_i2c.h"
+#include "efm32hg_rtc.h"
+#include "efm32hg_wdog.h"
+#include "efm32hg_mtb.h"
+#include "efm32hg_dma_descriptor.h"
+#include "efm32hg_devinfo.h"
+#include "efm32hg_romtable.h"
+#include "efm32hg_calibrate.h"
+
+/** @} End of group EFM32HG309F64_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F64_Peripheral_Base EFM32HG309F64 Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define AES_BASE          (0x400E0000UL) /**< AES base address  */
+#define DMA_BASE          (0x400C2000UL) /**< DMA base address  */
+#define USB_BASE          (0x400C4000UL) /**< USB base address  */
+#define MSC_BASE          (0x400C0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400C6000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400CA000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400C8000UL) /**< CMU base address  */
+#define TIMER0_BASE       (0x40010000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40010400UL) /**< TIMER1 base address  */
+#define TIMER2_BASE       (0x40010800UL) /**< TIMER2 base address  */
+#define ACMP0_BASE        (0x40001000UL) /**< ACMP0 base address  */
+#define USART0_BASE       (0x4000C000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x4000C400UL) /**< USART1 base address  */
+#define PRS_BASE          (0x400CC000UL) /**< PRS base address  */
+#define IDAC0_BASE        (0x40004000UL) /**< IDAC0 base address  */
+#define GPIO_BASE         (0x40006000UL) /**< GPIO base address  */
+#define VCMP_BASE         (0x40000000UL) /**< VCMP base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define LEUART0_BASE      (0x40084000UL) /**< LEUART0 base address  */
+#define PCNT0_BASE        (0x40086000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000A000UL) /**< I2C0 base address  */
+#define RTC_BASE          (0x40080000UL) /**< RTC base address  */
+#define WDOG_BASE         (0x40088000UL) /**< WDOG base address  */
+#define MTB_BASE          (0xF0040000UL) /**< MTB base address  */
+#define CALIBRATE_BASE    (0x0FE08000UL) /**< CALIBRATE base address */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xF00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32HG309F64_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F64_Peripheral_Declaration  EFM32HG309F64 Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define AES          ((AES_TypeDef *) AES_BASE)             /**< AES base pointer */
+#define DMA          ((DMA_TypeDef *) DMA_BASE)             /**< DMA base pointer */
+#define USB          ((USB_TypeDef *) USB_BASE)             /**< USB base pointer */
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        /**< TIMER2 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           /**< VCMP base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define RTC          ((RTC_TypeDef *) RTC_BASE)             /**< RTC base pointer */
+#define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           /**< WDOG base pointer */
+#define MTB          ((MTB_TypeDef *) MTB_BASE)             /**< MTB base pointer */
+#define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32HG309F64_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F64_BitFields EFM32HG309F64 Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_prs_signals.h"
+#include "efm32hg_dmareq.h"
+#include "efm32hg_dmactrl.h"
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F64_UNLOCK EFM32HG309F64 Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+
+/** @} End of group EFM32HG309F64_UNLOCK */
+
+/** @} End of group EFM32HG309F64_BitFields */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG309F64_Alternate_Function EFM32HG309F64 Alternate Function
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_af_ports.h"
+#include "efm32hg_af_pins.h"
+
+/** @} End of group EFM32HG309F64_Alternate_Function */
+
+/***************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32HG309F64 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFM32HG309F64_H */

cpu/efm32/families/efm32hg/include/vendor/efm32hg310f32.h

@@ -0,0 +1,410 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32HG310F32
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+#ifndef EFM32HG310F32_H
+#define EFM32HG310F32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F32 EFM32HG310F32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
+  NonMaskableInt_IRQn = -14,                /*!< -14 Cortex-M0+ Non Maskable Interrupt   */
+  HardFault_IRQn      = -13,                /*!< -13 Cortex-M0+ Hard Fault Interrupt     */
+  SVCall_IRQn         = -5,                 /*!< -5  Cortex-M0+ SV Call Interrupt        */
+  PendSV_IRQn         = -2,                 /*!< -2  Cortex-M0+ Pend SV Interrupt        */
+  SysTick_IRQn        = -1,                 /*!< -1  Cortex-M0+ System Tick Interrupt    */
+
+/******  EFM32HG Peripheral Interrupt Numbers ********************************************/
+  DMA_IRQn            = 0,  /*!< 0 EFM32 DMA Interrupt */
+  GPIO_EVEN_IRQn      = 1,  /*!< 1 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn         = 2,  /*!< 2 EFM32 TIMER0 Interrupt */
+  ACMP0_IRQn          = 3,  /*!< 3 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn           = 4,  /*!< 4 EFM32 ADC0 Interrupt */
+  I2C0_IRQn           = 5,  /*!< 5 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn       = 6,  /*!< 6 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn         = 7,  /*!< 7 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn      = 8,  /*!< 8 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn      = 9,  /*!< 9 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn        = 10, /*!< 10 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn          = 11, /*!< 11 EFM32 PCNT0 Interrupt */
+  RTC_IRQn            = 12, /*!< 12 EFM32 RTC Interrupt */
+  CMU_IRQn            = 13, /*!< 13 EFM32 CMU Interrupt */
+  VCMP_IRQn           = 14, /*!< 14 EFM32 VCMP Interrupt */
+  MSC_IRQn            = 15, /*!< 15 EFM32 MSC Interrupt */
+  AES_IRQn            = 16, /*!< 16 EFM32 AES Interrupt */
+  USART0_RX_IRQn      = 17, /*!< 17 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn      = 18, /*!< 18 EFM32 USART0_TX Interrupt */
+  USB_IRQn            = 19, /*!< 19 EFM32 USB Interrupt */
+  TIMER2_IRQn         = 20, /*!< 20 EFM32 TIMER2 Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F32_Core EFM32HG310F32 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT             0U /**< MPU not present */
+#define __VTOR_PRESENT            1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS          2U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32HG310F32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F32_Part EFM32HG310F32 Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFM32_HAPPY_FAMILY                     1  /**< Happy Gecko EFM32HG MCU Family */
+#define _EFM_DEVICE                                /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_SERIES_0                 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES                0  /**< Silicon Labs series number */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID       77 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_77       /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_PLATFORM_1               /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM              1  /**< @deprecated Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32HG310F32)
+#define EFM32HG310F32    1 /**< Happy Gecko Part  */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER          "EFM32HG310F32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define RAM_MEM_BASE         (0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE         (0x40000UL)    /**< RAM available address space  */
+#define RAM_MEM_END          (0x2003FFFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS         (0x18UL)       /**< RAM used bits  */
+#define DEVICE_MEM_BASE      (0xF0040000UL) /**< DEVICE base address  */
+#define DEVICE_MEM_SIZE      (0x1000UL)     /**< DEVICE available address space  */
+#define DEVICE_MEM_END       (0xF0040FFFUL) /**< DEVICE end address  */
+#define DEVICE_MEM_BITS      (0x12UL)       /**< DEVICE used bits  */
+#define USBC_MEM_BASE        (0x40100000UL) /**< USBC base address  */
+#define USBC_MEM_SIZE        (0x40000UL)    /**< USBC available address space  */
+#define USBC_MEM_END         (0x4013FFFFUL) /**< USBC end address  */
+#define USBC_MEM_BITS        (0x18UL)       /**< USBC used bits  */
+#define RAM_CODE_MEM_BASE    (0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE    (0x20000UL)    /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END     (0x1001FFFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS    (0x17UL)       /**< RAM_CODE used bits  */
+#define PER_MEM_BASE         (0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE         (0xE0000UL)    /**< PER available address space  */
+#define PER_MEM_END          (0x400DFFFFUL) /**< PER end address  */
+#define PER_MEM_BITS         (0x20UL)       /**< PER used bits  */
+#define FLASH_MEM_BASE       (0x0UL)        /**< FLASH base address  */
+#define FLASH_MEM_SIZE       (0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END        (0xFFFFFFFUL)  /**< FLASH end address  */
+#define FLASH_MEM_BITS       (0x28UL)       /**< FLASH used bits  */
+#define AES_MEM_BASE         (0x400E0000UL) /**< AES base address  */
+#define AES_MEM_SIZE         (0x400UL)      /**< AES available address space  */
+#define AES_MEM_END          (0x400E03FFUL) /**< AES end address  */
+#define AES_MEM_BITS         (0x10UL)       /**< AES used bits  */
+
+/** Flash and SRAM limits for EFM32HG310F32 */
+#define FLASH_BASE           (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE           (0x00008000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE      1024U          /**< Flash Memory page size */
+#define SRAM_BASE            (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE            (0x00002000UL) /**< Available SRAM Memory */
+#define __CM0PLUS_REV        0x0001U        /**< Cortex-M0+ Core revision r0p1 */
+#define PRS_CHAN_COUNT       6              /**< Number of PRS channels */
+#define DMA_CHAN_COUNT       6              /**< Number of DMA channels */
+#define EXT_IRQ_COUNT        21             /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX           42U
+#define AFCHANLOC_MAX        7U
+/** Analog AF channels */
+#define AFACHAN_MAX          27U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT           /**< TIMER is available in this part */
+#define TIMER_COUNT           3 /**< 3 TIMERs available  */
+#define ACMP_PRESENT            /**< ACMP is available in this part */
+#define ACMP_COUNT            1 /**< 1 ACMPs available  */
+#define USART_PRESENT           /**< USART is available in this part */
+#define USART_COUNT           2 /**< 2 USARTs available  */
+#define IDAC_PRESENT            /**< IDAC is available in this part */
+#define IDAC_COUNT            1 /**< 1 IDACs available  */
+#define ADC_PRESENT             /**< ADC is available in this part */
+#define ADC_COUNT             1 /**< 1 ADCs available  */
+#define LEUART_PRESENT          /**< LEUART is available in this part */
+#define LEUART_COUNT          1 /**< 1 LEUARTs available  */
+#define PCNT_PRESENT            /**< PCNT is available in this part */
+#define PCNT_COUNT            1 /**< 1 PCNTs available  */
+#define I2C_PRESENT             /**< I2C is available in this part */
+#define I2C_COUNT             1 /**< 1 I2Cs available  */
+#define AES_PRESENT             /**< AES is available in this part */
+#define AES_COUNT             1 /**< 1 AES available */
+#define DMA_PRESENT             /**< DMA is available in this part */
+#define DMA_COUNT             1 /**< 1 DMA available */
+#define LE_PRESENT              /**< LE is available in this part */
+#define LE_COUNT              1 /**< 1 LE available */
+#define USBC_PRESENT            /**< USBC is available in this part */
+#define USBC_COUNT            1 /**< 1 USBC available */
+#define USBLE_PRESENT           /**< USBLE is available in this part */
+#define USBLE_COUNT           1 /**< 1 USBLE available */
+#define USB_PRESENT             /**< USB is available in this part */
+#define USB_COUNT             1 /**< 1 USB available */
+#define MSC_PRESENT             /**< MSC is available in this part */
+#define MSC_COUNT             1 /**< 1 MSC available */
+#define EMU_PRESENT             /**< EMU is available in this part */
+#define EMU_COUNT             1 /**< 1 EMU available */
+#define RMU_PRESENT             /**< RMU is available in this part */
+#define RMU_COUNT             1 /**< 1 RMU available */
+#define CMU_PRESENT             /**< CMU is available in this part */
+#define CMU_COUNT             1 /**< 1 CMU available */
+#define PRS_PRESENT             /**< PRS is available in this part */
+#define PRS_COUNT             1 /**< 1 PRS available */
+#define GPIO_PRESENT            /**< GPIO is available in this part */
+#define GPIO_COUNT            1 /**< 1 GPIO available */
+#define VCMP_PRESENT            /**< VCMP is available in this part */
+#define VCMP_COUNT            1 /**< 1 VCMP available */
+#define RTC_PRESENT             /**< RTC is available in this part */
+#define RTC_COUNT             1 /**< 1 RTC available */
+#define HFXTAL_PRESENT          /**< HFXTAL is available in this part */
+#define HFXTAL_COUNT          1 /**< 1 HFXTAL available */
+#define LFXTAL_PRESENT          /**< LFXTAL is available in this part */
+#define LFXTAL_COUNT          1 /**< 1 LFXTAL available */
+#define USHFRCO_PRESENT         /**< USHFRCO is available in this part */
+#define USHFRCO_COUNT         1 /**< 1 USHFRCO available */
+#define WDOG_PRESENT            /**< WDOG is available in this part */
+#define WDOG_COUNT            1 /**< 1 WDOG available */
+#define DBG_PRESENT             /**< DBG is available in this part */
+#define DBG_COUNT             1 /**< 1 DBG available */
+#define MTB_PRESENT             /**< MTB is available in this part */
+#define MTB_COUNT             1 /**< 1 MTB available */
+#define BOOTLOADER_PRESENT      /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT      1 /**< 1 BOOTLOADER available */
+#define ANALOG_PRESENT          /**< ANALOG is available in this part */
+#define ANALOG_COUNT          1 /**< 1 ANALOG available */
+
+/** @} End of group EFM32HG310F32_Part */
+
+#ifndef ARM_MATH_CM0PLUS
+#define ARM_MATH_CM0PLUS
+#endif
+#include "arm_math.h"     /* To get __CLZ definitions etc. */
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_efm32hg.h" /* System Header */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F32_Peripheral_TypeDefs EFM32HG310F32 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efm32hg_aes.h"
+#include "efm32hg_dma_ch.h"
+#include "efm32hg_dma.h"
+#include "efm32hg_usb_diep.h"
+#include "efm32hg_usb_doep.h"
+#include "efm32hg_usb.h"
+#include "efm32hg_msc.h"
+#include "efm32hg_emu.h"
+#include "efm32hg_rmu.h"
+#include "efm32hg_cmu.h"
+#include "efm32hg_timer_cc.h"
+#include "efm32hg_timer.h"
+#include "efm32hg_acmp.h"
+#include "efm32hg_usart.h"
+#include "efm32hg_prs_ch.h"
+#include "efm32hg_prs.h"
+#include "efm32hg_idac.h"
+#include "efm32hg_gpio_p.h"
+#include "efm32hg_gpio.h"
+#include "efm32hg_vcmp.h"
+#include "efm32hg_adc.h"
+#include "efm32hg_leuart.h"
+#include "efm32hg_pcnt.h"
+#include "efm32hg_i2c.h"
+#include "efm32hg_rtc.h"
+#include "efm32hg_wdog.h"
+#include "efm32hg_mtb.h"
+#include "efm32hg_dma_descriptor.h"
+#include "efm32hg_devinfo.h"
+#include "efm32hg_romtable.h"
+#include "efm32hg_calibrate.h"
+
+/** @} End of group EFM32HG310F32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F32_Peripheral_Base EFM32HG310F32 Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define AES_BASE          (0x400E0000UL) /**< AES base address  */
+#define DMA_BASE          (0x400C2000UL) /**< DMA base address  */
+#define USB_BASE          (0x400C4000UL) /**< USB base address  */
+#define MSC_BASE          (0x400C0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400C6000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400CA000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400C8000UL) /**< CMU base address  */
+#define TIMER0_BASE       (0x40010000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40010400UL) /**< TIMER1 base address  */
+#define TIMER2_BASE       (0x40010800UL) /**< TIMER2 base address  */
+#define ACMP0_BASE        (0x40001000UL) /**< ACMP0 base address  */
+#define USART0_BASE       (0x4000C000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x4000C400UL) /**< USART1 base address  */
+#define PRS_BASE          (0x400CC000UL) /**< PRS base address  */
+#define IDAC0_BASE        (0x40004000UL) /**< IDAC0 base address  */
+#define GPIO_BASE         (0x40006000UL) /**< GPIO base address  */
+#define VCMP_BASE         (0x40000000UL) /**< VCMP base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define LEUART0_BASE      (0x40084000UL) /**< LEUART0 base address  */
+#define PCNT0_BASE        (0x40086000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000A000UL) /**< I2C0 base address  */
+#define RTC_BASE          (0x40080000UL) /**< RTC base address  */
+#define WDOG_BASE         (0x40088000UL) /**< WDOG base address  */
+#define MTB_BASE          (0xF0040000UL) /**< MTB base address  */
+#define CALIBRATE_BASE    (0x0FE08000UL) /**< CALIBRATE base address */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xF00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32HG310F32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F32_Peripheral_Declaration  EFM32HG310F32 Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define AES          ((AES_TypeDef *) AES_BASE)             /**< AES base pointer */
+#define DMA          ((DMA_TypeDef *) DMA_BASE)             /**< DMA base pointer */
+#define USB          ((USB_TypeDef *) USB_BASE)             /**< USB base pointer */
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        /**< TIMER2 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           /**< VCMP base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define RTC          ((RTC_TypeDef *) RTC_BASE)             /**< RTC base pointer */
+#define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           /**< WDOG base pointer */
+#define MTB          ((MTB_TypeDef *) MTB_BASE)             /**< MTB base pointer */
+#define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32HG310F32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F32_BitFields EFM32HG310F32 Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_prs_signals.h"
+#include "efm32hg_dmareq.h"
+#include "efm32hg_dmactrl.h"
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F32_UNLOCK EFM32HG310F32 Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+
+/** @} End of group EFM32HG310F32_UNLOCK */
+
+/** @} End of group EFM32HG310F32_BitFields */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F32_Alternate_Function EFM32HG310F32 Alternate Function
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_af_ports.h"
+#include "efm32hg_af_pins.h"
+
+/** @} End of group EFM32HG310F32_Alternate_Function */
+
+/***************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32HG310F32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFM32HG310F32_H */

cpu/efm32/families/efm32hg/include/vendor/efm32hg310f64.h

@@ -0,0 +1,410 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32HG310F64
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+#ifndef EFM32HG310F64_H
+#define EFM32HG310F64_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F64 EFM32HG310F64
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
+  NonMaskableInt_IRQn = -14,                /*!< -14 Cortex-M0+ Non Maskable Interrupt   */
+  HardFault_IRQn      = -13,                /*!< -13 Cortex-M0+ Hard Fault Interrupt     */
+  SVCall_IRQn         = -5,                 /*!< -5  Cortex-M0+ SV Call Interrupt        */
+  PendSV_IRQn         = -2,                 /*!< -2  Cortex-M0+ Pend SV Interrupt        */
+  SysTick_IRQn        = -1,                 /*!< -1  Cortex-M0+ System Tick Interrupt    */
+
+/******  EFM32HG Peripheral Interrupt Numbers ********************************************/
+  DMA_IRQn            = 0,  /*!< 0 EFM32 DMA Interrupt */
+  GPIO_EVEN_IRQn      = 1,  /*!< 1 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn         = 2,  /*!< 2 EFM32 TIMER0 Interrupt */
+  ACMP0_IRQn          = 3,  /*!< 3 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn           = 4,  /*!< 4 EFM32 ADC0 Interrupt */
+  I2C0_IRQn           = 5,  /*!< 5 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn       = 6,  /*!< 6 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn         = 7,  /*!< 7 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn      = 8,  /*!< 8 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn      = 9,  /*!< 9 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn        = 10, /*!< 10 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn          = 11, /*!< 11 EFM32 PCNT0 Interrupt */
+  RTC_IRQn            = 12, /*!< 12 EFM32 RTC Interrupt */
+  CMU_IRQn            = 13, /*!< 13 EFM32 CMU Interrupt */
+  VCMP_IRQn           = 14, /*!< 14 EFM32 VCMP Interrupt */
+  MSC_IRQn            = 15, /*!< 15 EFM32 MSC Interrupt */
+  AES_IRQn            = 16, /*!< 16 EFM32 AES Interrupt */
+  USART0_RX_IRQn      = 17, /*!< 17 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn      = 18, /*!< 18 EFM32 USART0_TX Interrupt */
+  USB_IRQn            = 19, /*!< 19 EFM32 USB Interrupt */
+  TIMER2_IRQn         = 20, /*!< 20 EFM32 TIMER2 Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F64_Core EFM32HG310F64 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT             0U /**< MPU not present */
+#define __VTOR_PRESENT            1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS          2U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32HG310F64_Core */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F64_Part EFM32HG310F64 Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFM32_HAPPY_FAMILY                     1  /**< Happy Gecko EFM32HG MCU Family */
+#define _EFM_DEVICE                                /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_SERIES_0                 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES                0  /**< Silicon Labs series number */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID       77 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_77       /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_PLATFORM_1               /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM              1  /**< @deprecated Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32HG310F64)
+#define EFM32HG310F64    1 /**< Happy Gecko Part  */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER          "EFM32HG310F64" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define RAM_MEM_BASE         (0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE         (0x40000UL)    /**< RAM available address space  */
+#define RAM_MEM_END          (0x2003FFFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS         (0x18UL)       /**< RAM used bits  */
+#define DEVICE_MEM_BASE      (0xF0040000UL) /**< DEVICE base address  */
+#define DEVICE_MEM_SIZE      (0x1000UL)     /**< DEVICE available address space  */
+#define DEVICE_MEM_END       (0xF0040FFFUL) /**< DEVICE end address  */
+#define DEVICE_MEM_BITS      (0x12UL)       /**< DEVICE used bits  */
+#define USBC_MEM_BASE        (0x40100000UL) /**< USBC base address  */
+#define USBC_MEM_SIZE        (0x40000UL)    /**< USBC available address space  */
+#define USBC_MEM_END         (0x4013FFFFUL) /**< USBC end address  */
+#define USBC_MEM_BITS        (0x18UL)       /**< USBC used bits  */
+#define RAM_CODE_MEM_BASE    (0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE    (0x20000UL)    /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END     (0x1001FFFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS    (0x17UL)       /**< RAM_CODE used bits  */
+#define PER_MEM_BASE         (0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE         (0xE0000UL)    /**< PER available address space  */
+#define PER_MEM_END          (0x400DFFFFUL) /**< PER end address  */
+#define PER_MEM_BITS         (0x20UL)       /**< PER used bits  */
+#define FLASH_MEM_BASE       (0x0UL)        /**< FLASH base address  */
+#define FLASH_MEM_SIZE       (0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END        (0xFFFFFFFUL)  /**< FLASH end address  */
+#define FLASH_MEM_BITS       (0x28UL)       /**< FLASH used bits  */
+#define AES_MEM_BASE         (0x400E0000UL) /**< AES base address  */
+#define AES_MEM_SIZE         (0x400UL)      /**< AES available address space  */
+#define AES_MEM_END          (0x400E03FFUL) /**< AES end address  */
+#define AES_MEM_BITS         (0x10UL)       /**< AES used bits  */
+
+/** Flash and SRAM limits for EFM32HG310F64 */
+#define FLASH_BASE           (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE           (0x00010000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE      1024U          /**< Flash Memory page size */
+#define SRAM_BASE            (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE            (0x00002000UL) /**< Available SRAM Memory */
+#define __CM0PLUS_REV        0x0001U        /**< Cortex-M0+ Core revision r0p1 */
+#define PRS_CHAN_COUNT       6              /**< Number of PRS channels */
+#define DMA_CHAN_COUNT       6              /**< Number of DMA channels */
+#define EXT_IRQ_COUNT        21             /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX           42U
+#define AFCHANLOC_MAX        7U
+/** Analog AF channels */
+#define AFACHAN_MAX          27U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT           /**< TIMER is available in this part */
+#define TIMER_COUNT           3 /**< 3 TIMERs available  */
+#define ACMP_PRESENT            /**< ACMP is available in this part */
+#define ACMP_COUNT            1 /**< 1 ACMPs available  */
+#define USART_PRESENT           /**< USART is available in this part */
+#define USART_COUNT           2 /**< 2 USARTs available  */
+#define IDAC_PRESENT            /**< IDAC is available in this part */
+#define IDAC_COUNT            1 /**< 1 IDACs available  */
+#define ADC_PRESENT             /**< ADC is available in this part */
+#define ADC_COUNT             1 /**< 1 ADCs available  */
+#define LEUART_PRESENT          /**< LEUART is available in this part */
+#define LEUART_COUNT          1 /**< 1 LEUARTs available  */
+#define PCNT_PRESENT            /**< PCNT is available in this part */
+#define PCNT_COUNT            1 /**< 1 PCNTs available  */
+#define I2C_PRESENT             /**< I2C is available in this part */
+#define I2C_COUNT             1 /**< 1 I2Cs available  */
+#define AES_PRESENT             /**< AES is available in this part */
+#define AES_COUNT             1 /**< 1 AES available */
+#define DMA_PRESENT             /**< DMA is available in this part */
+#define DMA_COUNT             1 /**< 1 DMA available */
+#define LE_PRESENT              /**< LE is available in this part */
+#define LE_COUNT              1 /**< 1 LE available */
+#define USBC_PRESENT            /**< USBC is available in this part */
+#define USBC_COUNT            1 /**< 1 USBC available */
+#define USBLE_PRESENT           /**< USBLE is available in this part */
+#define USBLE_COUNT           1 /**< 1 USBLE available */
+#define USB_PRESENT             /**< USB is available in this part */
+#define USB_COUNT             1 /**< 1 USB available */
+#define MSC_PRESENT             /**< MSC is available in this part */
+#define MSC_COUNT             1 /**< 1 MSC available */
+#define EMU_PRESENT             /**< EMU is available in this part */
+#define EMU_COUNT             1 /**< 1 EMU available */
+#define RMU_PRESENT             /**< RMU is available in this part */
+#define RMU_COUNT             1 /**< 1 RMU available */
+#define CMU_PRESENT             /**< CMU is available in this part */
+#define CMU_COUNT             1 /**< 1 CMU available */
+#define PRS_PRESENT             /**< PRS is available in this part */
+#define PRS_COUNT             1 /**< 1 PRS available */
+#define GPIO_PRESENT            /**< GPIO is available in this part */
+#define GPIO_COUNT            1 /**< 1 GPIO available */
+#define VCMP_PRESENT            /**< VCMP is available in this part */
+#define VCMP_COUNT            1 /**< 1 VCMP available */
+#define RTC_PRESENT             /**< RTC is available in this part */
+#define RTC_COUNT             1 /**< 1 RTC available */
+#define HFXTAL_PRESENT          /**< HFXTAL is available in this part */
+#define HFXTAL_COUNT          1 /**< 1 HFXTAL available */
+#define LFXTAL_PRESENT          /**< LFXTAL is available in this part */
+#define LFXTAL_COUNT          1 /**< 1 LFXTAL available */
+#define USHFRCO_PRESENT         /**< USHFRCO is available in this part */
+#define USHFRCO_COUNT         1 /**< 1 USHFRCO available */
+#define WDOG_PRESENT            /**< WDOG is available in this part */
+#define WDOG_COUNT            1 /**< 1 WDOG available */
+#define DBG_PRESENT             /**< DBG is available in this part */
+#define DBG_COUNT             1 /**< 1 DBG available */
+#define MTB_PRESENT             /**< MTB is available in this part */
+#define MTB_COUNT             1 /**< 1 MTB available */
+#define BOOTLOADER_PRESENT      /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT      1 /**< 1 BOOTLOADER available */
+#define ANALOG_PRESENT          /**< ANALOG is available in this part */
+#define ANALOG_COUNT          1 /**< 1 ANALOG available */
+
+/** @} End of group EFM32HG310F64_Part */
+
+#ifndef ARM_MATH_CM0PLUS
+#define ARM_MATH_CM0PLUS
+#endif
+#include "arm_math.h"     /* To get __CLZ definitions etc. */
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_efm32hg.h" /* System Header */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F64_Peripheral_TypeDefs EFM32HG310F64 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efm32hg_aes.h"
+#include "efm32hg_dma_ch.h"
+#include "efm32hg_dma.h"
+#include "efm32hg_usb_diep.h"
+#include "efm32hg_usb_doep.h"
+#include "efm32hg_usb.h"
+#include "efm32hg_msc.h"
+#include "efm32hg_emu.h"
+#include "efm32hg_rmu.h"
+#include "efm32hg_cmu.h"
+#include "efm32hg_timer_cc.h"
+#include "efm32hg_timer.h"
+#include "efm32hg_acmp.h"
+#include "efm32hg_usart.h"
+#include "efm32hg_prs_ch.h"
+#include "efm32hg_prs.h"
+#include "efm32hg_idac.h"
+#include "efm32hg_gpio_p.h"
+#include "efm32hg_gpio.h"
+#include "efm32hg_vcmp.h"
+#include "efm32hg_adc.h"
+#include "efm32hg_leuart.h"
+#include "efm32hg_pcnt.h"
+#include "efm32hg_i2c.h"
+#include "efm32hg_rtc.h"
+#include "efm32hg_wdog.h"
+#include "efm32hg_mtb.h"
+#include "efm32hg_dma_descriptor.h"
+#include "efm32hg_devinfo.h"
+#include "efm32hg_romtable.h"
+#include "efm32hg_calibrate.h"
+
+/** @} End of group EFM32HG310F64_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F64_Peripheral_Base EFM32HG310F64 Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define AES_BASE          (0x400E0000UL) /**< AES base address  */
+#define DMA_BASE          (0x400C2000UL) /**< DMA base address  */
+#define USB_BASE          (0x400C4000UL) /**< USB base address  */
+#define MSC_BASE          (0x400C0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400C6000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400CA000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400C8000UL) /**< CMU base address  */
+#define TIMER0_BASE       (0x40010000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40010400UL) /**< TIMER1 base address  */
+#define TIMER2_BASE       (0x40010800UL) /**< TIMER2 base address  */
+#define ACMP0_BASE        (0x40001000UL) /**< ACMP0 base address  */
+#define USART0_BASE       (0x4000C000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x4000C400UL) /**< USART1 base address  */
+#define PRS_BASE          (0x400CC000UL) /**< PRS base address  */
+#define IDAC0_BASE        (0x40004000UL) /**< IDAC0 base address  */
+#define GPIO_BASE         (0x40006000UL) /**< GPIO base address  */
+#define VCMP_BASE         (0x40000000UL) /**< VCMP base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define LEUART0_BASE      (0x40084000UL) /**< LEUART0 base address  */
+#define PCNT0_BASE        (0x40086000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000A000UL) /**< I2C0 base address  */
+#define RTC_BASE          (0x40080000UL) /**< RTC base address  */
+#define WDOG_BASE         (0x40088000UL) /**< WDOG base address  */
+#define MTB_BASE          (0xF0040000UL) /**< MTB base address  */
+#define CALIBRATE_BASE    (0x0FE08000UL) /**< CALIBRATE base address */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xF00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32HG310F64_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F64_Peripheral_Declaration  EFM32HG310F64 Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define AES          ((AES_TypeDef *) AES_BASE)             /**< AES base pointer */
+#define DMA          ((DMA_TypeDef *) DMA_BASE)             /**< DMA base pointer */
+#define USB          ((USB_TypeDef *) USB_BASE)             /**< USB base pointer */
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        /**< TIMER2 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           /**< VCMP base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define RTC          ((RTC_TypeDef *) RTC_BASE)             /**< RTC base pointer */
+#define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           /**< WDOG base pointer */
+#define MTB          ((MTB_TypeDef *) MTB_BASE)             /**< MTB base pointer */
+#define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32HG310F64_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F64_BitFields EFM32HG310F64 Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_prs_signals.h"
+#include "efm32hg_dmareq.h"
+#include "efm32hg_dmactrl.h"
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F64_UNLOCK EFM32HG310F64 Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+
+/** @} End of group EFM32HG310F64_UNLOCK */
+
+/** @} End of group EFM32HG310F64_BitFields */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG310F64_Alternate_Function EFM32HG310F64 Alternate Function
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_af_ports.h"
+#include "efm32hg_af_pins.h"
+
+/** @} End of group EFM32HG310F64_Alternate_Function */
+
+/***************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32HG310F64 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFM32HG310F64_H */

cpu/efm32/families/efm32hg/include/vendor/efm32hg322f32.h

@@ -0,0 +1,410 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32HG322F32
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+#ifndef EFM32HG322F32_H
+#define EFM32HG322F32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F32 EFM32HG322F32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
+  NonMaskableInt_IRQn = -14,                /*!< -14 Cortex-M0+ Non Maskable Interrupt   */
+  HardFault_IRQn      = -13,                /*!< -13 Cortex-M0+ Hard Fault Interrupt     */
+  SVCall_IRQn         = -5,                 /*!< -5  Cortex-M0+ SV Call Interrupt        */
+  PendSV_IRQn         = -2,                 /*!< -2  Cortex-M0+ Pend SV Interrupt        */
+  SysTick_IRQn        = -1,                 /*!< -1  Cortex-M0+ System Tick Interrupt    */
+
+/******  EFM32HG Peripheral Interrupt Numbers ********************************************/
+  DMA_IRQn            = 0,  /*!< 0 EFM32 DMA Interrupt */
+  GPIO_EVEN_IRQn      = 1,  /*!< 1 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn         = 2,  /*!< 2 EFM32 TIMER0 Interrupt */
+  ACMP0_IRQn          = 3,  /*!< 3 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn           = 4,  /*!< 4 EFM32 ADC0 Interrupt */
+  I2C0_IRQn           = 5,  /*!< 5 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn       = 6,  /*!< 6 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn         = 7,  /*!< 7 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn      = 8,  /*!< 8 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn      = 9,  /*!< 9 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn        = 10, /*!< 10 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn          = 11, /*!< 11 EFM32 PCNT0 Interrupt */
+  RTC_IRQn            = 12, /*!< 12 EFM32 RTC Interrupt */
+  CMU_IRQn            = 13, /*!< 13 EFM32 CMU Interrupt */
+  VCMP_IRQn           = 14, /*!< 14 EFM32 VCMP Interrupt */
+  MSC_IRQn            = 15, /*!< 15 EFM32 MSC Interrupt */
+  AES_IRQn            = 16, /*!< 16 EFM32 AES Interrupt */
+  USART0_RX_IRQn      = 17, /*!< 17 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn      = 18, /*!< 18 EFM32 USART0_TX Interrupt */
+  USB_IRQn            = 19, /*!< 19 EFM32 USB Interrupt */
+  TIMER2_IRQn         = 20, /*!< 20 EFM32 TIMER2 Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F32_Core EFM32HG322F32 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT             0U /**< MPU not present */
+#define __VTOR_PRESENT            1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS          2U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32HG322F32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F32_Part EFM32HG322F32 Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFM32_HAPPY_FAMILY                     1  /**< Happy Gecko EFM32HG MCU Family */
+#define _EFM_DEVICE                                /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_SERIES_0                 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES                0  /**< Silicon Labs series number */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID       77 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_77       /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_PLATFORM_1               /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM              1  /**< @deprecated Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32HG322F32)
+#define EFM32HG322F32    1 /**< Happy Gecko Part  */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER          "EFM32HG322F32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define RAM_MEM_BASE         (0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE         (0x40000UL)    /**< RAM available address space  */
+#define RAM_MEM_END          (0x2003FFFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS         (0x18UL)       /**< RAM used bits  */
+#define DEVICE_MEM_BASE      (0xF0040000UL) /**< DEVICE base address  */
+#define DEVICE_MEM_SIZE      (0x1000UL)     /**< DEVICE available address space  */
+#define DEVICE_MEM_END       (0xF0040FFFUL) /**< DEVICE end address  */
+#define DEVICE_MEM_BITS      (0x12UL)       /**< DEVICE used bits  */
+#define USBC_MEM_BASE        (0x40100000UL) /**< USBC base address  */
+#define USBC_MEM_SIZE        (0x40000UL)    /**< USBC available address space  */
+#define USBC_MEM_END         (0x4013FFFFUL) /**< USBC end address  */
+#define USBC_MEM_BITS        (0x18UL)       /**< USBC used bits  */
+#define RAM_CODE_MEM_BASE    (0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE    (0x20000UL)    /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END     (0x1001FFFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS    (0x17UL)       /**< RAM_CODE used bits  */
+#define PER_MEM_BASE         (0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE         (0xE0000UL)    /**< PER available address space  */
+#define PER_MEM_END          (0x400DFFFFUL) /**< PER end address  */
+#define PER_MEM_BITS         (0x20UL)       /**< PER used bits  */
+#define FLASH_MEM_BASE       (0x0UL)        /**< FLASH base address  */
+#define FLASH_MEM_SIZE       (0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END        (0xFFFFFFFUL)  /**< FLASH end address  */
+#define FLASH_MEM_BITS       (0x28UL)       /**< FLASH used bits  */
+#define AES_MEM_BASE         (0x400E0000UL) /**< AES base address  */
+#define AES_MEM_SIZE         (0x400UL)      /**< AES available address space  */
+#define AES_MEM_END          (0x400E03FFUL) /**< AES end address  */
+#define AES_MEM_BITS         (0x10UL)       /**< AES used bits  */
+
+/** Flash and SRAM limits for EFM32HG322F32 */
+#define FLASH_BASE           (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE           (0x00008000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE      1024U          /**< Flash Memory page size */
+#define SRAM_BASE            (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE            (0x00002000UL) /**< Available SRAM Memory */
+#define __CM0PLUS_REV        0x0001U        /**< Cortex-M0+ Core revision r0p1 */
+#define PRS_CHAN_COUNT       6              /**< Number of PRS channels */
+#define DMA_CHAN_COUNT       6              /**< Number of DMA channels */
+#define EXT_IRQ_COUNT        21             /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX           42U
+#define AFCHANLOC_MAX        7U
+/** Analog AF channels */
+#define AFACHAN_MAX          27U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT           /**< TIMER is available in this part */
+#define TIMER_COUNT           3 /**< 3 TIMERs available  */
+#define ACMP_PRESENT            /**< ACMP is available in this part */
+#define ACMP_COUNT            1 /**< 1 ACMPs available  */
+#define USART_PRESENT           /**< USART is available in this part */
+#define USART_COUNT           2 /**< 2 USARTs available  */
+#define IDAC_PRESENT            /**< IDAC is available in this part */
+#define IDAC_COUNT            1 /**< 1 IDACs available  */
+#define ADC_PRESENT             /**< ADC is available in this part */
+#define ADC_COUNT             1 /**< 1 ADCs available  */
+#define LEUART_PRESENT          /**< LEUART is available in this part */
+#define LEUART_COUNT          1 /**< 1 LEUARTs available  */
+#define PCNT_PRESENT            /**< PCNT is available in this part */
+#define PCNT_COUNT            1 /**< 1 PCNTs available  */
+#define I2C_PRESENT             /**< I2C is available in this part */
+#define I2C_COUNT             1 /**< 1 I2Cs available  */
+#define AES_PRESENT             /**< AES is available in this part */
+#define AES_COUNT             1 /**< 1 AES available */
+#define DMA_PRESENT             /**< DMA is available in this part */
+#define DMA_COUNT             1 /**< 1 DMA available */
+#define LE_PRESENT              /**< LE is available in this part */
+#define LE_COUNT              1 /**< 1 LE available */
+#define USBC_PRESENT            /**< USBC is available in this part */
+#define USBC_COUNT            1 /**< 1 USBC available */
+#define USBLE_PRESENT           /**< USBLE is available in this part */
+#define USBLE_COUNT           1 /**< 1 USBLE available */
+#define USB_PRESENT             /**< USB is available in this part */
+#define USB_COUNT             1 /**< 1 USB available */
+#define MSC_PRESENT             /**< MSC is available in this part */
+#define MSC_COUNT             1 /**< 1 MSC available */
+#define EMU_PRESENT             /**< EMU is available in this part */
+#define EMU_COUNT             1 /**< 1 EMU available */
+#define RMU_PRESENT             /**< RMU is available in this part */
+#define RMU_COUNT             1 /**< 1 RMU available */
+#define CMU_PRESENT             /**< CMU is available in this part */
+#define CMU_COUNT             1 /**< 1 CMU available */
+#define PRS_PRESENT             /**< PRS is available in this part */
+#define PRS_COUNT             1 /**< 1 PRS available */
+#define GPIO_PRESENT            /**< GPIO is available in this part */
+#define GPIO_COUNT            1 /**< 1 GPIO available */
+#define VCMP_PRESENT            /**< VCMP is available in this part */
+#define VCMP_COUNT            1 /**< 1 VCMP available */
+#define RTC_PRESENT             /**< RTC is available in this part */
+#define RTC_COUNT             1 /**< 1 RTC available */
+#define HFXTAL_PRESENT          /**< HFXTAL is available in this part */
+#define HFXTAL_COUNT          1 /**< 1 HFXTAL available */
+#define LFXTAL_PRESENT          /**< LFXTAL is available in this part */
+#define LFXTAL_COUNT          1 /**< 1 LFXTAL available */
+#define USHFRCO_PRESENT         /**< USHFRCO is available in this part */
+#define USHFRCO_COUNT         1 /**< 1 USHFRCO available */
+#define WDOG_PRESENT            /**< WDOG is available in this part */
+#define WDOG_COUNT            1 /**< 1 WDOG available */
+#define DBG_PRESENT             /**< DBG is available in this part */
+#define DBG_COUNT             1 /**< 1 DBG available */
+#define MTB_PRESENT             /**< MTB is available in this part */
+#define MTB_COUNT             1 /**< 1 MTB available */
+#define BOOTLOADER_PRESENT      /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT      1 /**< 1 BOOTLOADER available */
+#define ANALOG_PRESENT          /**< ANALOG is available in this part */
+#define ANALOG_COUNT          1 /**< 1 ANALOG available */
+
+/** @} End of group EFM32HG322F32_Part */
+
+#ifndef ARM_MATH_CM0PLUS
+#define ARM_MATH_CM0PLUS
+#endif
+#include "arm_math.h"     /* To get __CLZ definitions etc. */
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_efm32hg.h" /* System Header */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F32_Peripheral_TypeDefs EFM32HG322F32 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efm32hg_aes.h"
+#include "efm32hg_dma_ch.h"
+#include "efm32hg_dma.h"
+#include "efm32hg_usb_diep.h"
+#include "efm32hg_usb_doep.h"
+#include "efm32hg_usb.h"
+#include "efm32hg_msc.h"
+#include "efm32hg_emu.h"
+#include "efm32hg_rmu.h"
+#include "efm32hg_cmu.h"
+#include "efm32hg_timer_cc.h"
+#include "efm32hg_timer.h"
+#include "efm32hg_acmp.h"
+#include "efm32hg_usart.h"
+#include "efm32hg_prs_ch.h"
+#include "efm32hg_prs.h"
+#include "efm32hg_idac.h"
+#include "efm32hg_gpio_p.h"
+#include "efm32hg_gpio.h"
+#include "efm32hg_vcmp.h"
+#include "efm32hg_adc.h"
+#include "efm32hg_leuart.h"
+#include "efm32hg_pcnt.h"
+#include "efm32hg_i2c.h"
+#include "efm32hg_rtc.h"
+#include "efm32hg_wdog.h"
+#include "efm32hg_mtb.h"
+#include "efm32hg_dma_descriptor.h"
+#include "efm32hg_devinfo.h"
+#include "efm32hg_romtable.h"
+#include "efm32hg_calibrate.h"
+
+/** @} End of group EFM32HG322F32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F32_Peripheral_Base EFM32HG322F32 Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define AES_BASE          (0x400E0000UL) /**< AES base address  */
+#define DMA_BASE          (0x400C2000UL) /**< DMA base address  */
+#define USB_BASE          (0x400C4000UL) /**< USB base address  */
+#define MSC_BASE          (0x400C0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400C6000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400CA000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400C8000UL) /**< CMU base address  */
+#define TIMER0_BASE       (0x40010000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40010400UL) /**< TIMER1 base address  */
+#define TIMER2_BASE       (0x40010800UL) /**< TIMER2 base address  */
+#define ACMP0_BASE        (0x40001000UL) /**< ACMP0 base address  */
+#define USART0_BASE       (0x4000C000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x4000C400UL) /**< USART1 base address  */
+#define PRS_BASE          (0x400CC000UL) /**< PRS base address  */
+#define IDAC0_BASE        (0x40004000UL) /**< IDAC0 base address  */
+#define GPIO_BASE         (0x40006000UL) /**< GPIO base address  */
+#define VCMP_BASE         (0x40000000UL) /**< VCMP base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define LEUART0_BASE      (0x40084000UL) /**< LEUART0 base address  */
+#define PCNT0_BASE        (0x40086000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000A000UL) /**< I2C0 base address  */
+#define RTC_BASE          (0x40080000UL) /**< RTC base address  */
+#define WDOG_BASE         (0x40088000UL) /**< WDOG base address  */
+#define MTB_BASE          (0xF0040000UL) /**< MTB base address  */
+#define CALIBRATE_BASE    (0x0FE08000UL) /**< CALIBRATE base address */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xF00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32HG322F32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F32_Peripheral_Declaration  EFM32HG322F32 Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define AES          ((AES_TypeDef *) AES_BASE)             /**< AES base pointer */
+#define DMA          ((DMA_TypeDef *) DMA_BASE)             /**< DMA base pointer */
+#define USB          ((USB_TypeDef *) USB_BASE)             /**< USB base pointer */
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        /**< TIMER2 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           /**< VCMP base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define RTC          ((RTC_TypeDef *) RTC_BASE)             /**< RTC base pointer */
+#define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           /**< WDOG base pointer */
+#define MTB          ((MTB_TypeDef *) MTB_BASE)             /**< MTB base pointer */
+#define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32HG322F32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F32_BitFields EFM32HG322F32 Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_prs_signals.h"
+#include "efm32hg_dmareq.h"
+#include "efm32hg_dmactrl.h"
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F32_UNLOCK EFM32HG322F32 Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+
+/** @} End of group EFM32HG322F32_UNLOCK */
+
+/** @} End of group EFM32HG322F32_BitFields */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F32_Alternate_Function EFM32HG322F32 Alternate Function
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_af_ports.h"
+#include "efm32hg_af_pins.h"
+
+/** @} End of group EFM32HG322F32_Alternate_Function */
+
+/***************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32HG322F32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFM32HG322F32_H */

cpu/efm32/families/efm32hg/include/vendor/efm32hg322f64.h

@@ -0,0 +1,410 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32HG322F64
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+#ifndef EFM32HG322F64_H
+#define EFM32HG322F64_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F64 EFM32HG322F64
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
+  NonMaskableInt_IRQn = -14,                /*!< -14 Cortex-M0+ Non Maskable Interrupt   */
+  HardFault_IRQn      = -13,                /*!< -13 Cortex-M0+ Hard Fault Interrupt     */
+  SVCall_IRQn         = -5,                 /*!< -5  Cortex-M0+ SV Call Interrupt        */
+  PendSV_IRQn         = -2,                 /*!< -2  Cortex-M0+ Pend SV Interrupt        */
+  SysTick_IRQn        = -1,                 /*!< -1  Cortex-M0+ System Tick Interrupt    */
+
+/******  EFM32HG Peripheral Interrupt Numbers ********************************************/
+  DMA_IRQn            = 0,  /*!< 0 EFM32 DMA Interrupt */
+  GPIO_EVEN_IRQn      = 1,  /*!< 1 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn         = 2,  /*!< 2 EFM32 TIMER0 Interrupt */
+  ACMP0_IRQn          = 3,  /*!< 3 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn           = 4,  /*!< 4 EFM32 ADC0 Interrupt */
+  I2C0_IRQn           = 5,  /*!< 5 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn       = 6,  /*!< 6 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn         = 7,  /*!< 7 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn      = 8,  /*!< 8 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn      = 9,  /*!< 9 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn        = 10, /*!< 10 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn          = 11, /*!< 11 EFM32 PCNT0 Interrupt */
+  RTC_IRQn            = 12, /*!< 12 EFM32 RTC Interrupt */
+  CMU_IRQn            = 13, /*!< 13 EFM32 CMU Interrupt */
+  VCMP_IRQn           = 14, /*!< 14 EFM32 VCMP Interrupt */
+  MSC_IRQn            = 15, /*!< 15 EFM32 MSC Interrupt */
+  AES_IRQn            = 16, /*!< 16 EFM32 AES Interrupt */
+  USART0_RX_IRQn      = 17, /*!< 17 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn      = 18, /*!< 18 EFM32 USART0_TX Interrupt */
+  USB_IRQn            = 19, /*!< 19 EFM32 USB Interrupt */
+  TIMER2_IRQn         = 20, /*!< 20 EFM32 TIMER2 Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F64_Core EFM32HG322F64 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT             0U /**< MPU not present */
+#define __VTOR_PRESENT            1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS          2U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32HG322F64_Core */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F64_Part EFM32HG322F64 Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFM32_HAPPY_FAMILY                     1  /**< Happy Gecko EFM32HG MCU Family */
+#define _EFM_DEVICE                                /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_SERIES_0                 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES                0  /**< Silicon Labs series number */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID       77 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_77       /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_PLATFORM_1               /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM              1  /**< @deprecated Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32HG322F64)
+#define EFM32HG322F64    1 /**< Happy Gecko Part  */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER          "EFM32HG322F64" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define RAM_MEM_BASE         (0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE         (0x40000UL)    /**< RAM available address space  */
+#define RAM_MEM_END          (0x2003FFFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS         (0x18UL)       /**< RAM used bits  */
+#define DEVICE_MEM_BASE      (0xF0040000UL) /**< DEVICE base address  */
+#define DEVICE_MEM_SIZE      (0x1000UL)     /**< DEVICE available address space  */
+#define DEVICE_MEM_END       (0xF0040FFFUL) /**< DEVICE end address  */
+#define DEVICE_MEM_BITS      (0x12UL)       /**< DEVICE used bits  */
+#define USBC_MEM_BASE        (0x40100000UL) /**< USBC base address  */
+#define USBC_MEM_SIZE        (0x40000UL)    /**< USBC available address space  */
+#define USBC_MEM_END         (0x4013FFFFUL) /**< USBC end address  */
+#define USBC_MEM_BITS        (0x18UL)       /**< USBC used bits  */
+#define RAM_CODE_MEM_BASE    (0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE    (0x20000UL)    /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END     (0x1001FFFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS    (0x17UL)       /**< RAM_CODE used bits  */
+#define PER_MEM_BASE         (0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE         (0xE0000UL)    /**< PER available address space  */
+#define PER_MEM_END          (0x400DFFFFUL) /**< PER end address  */
+#define PER_MEM_BITS         (0x20UL)       /**< PER used bits  */
+#define FLASH_MEM_BASE       (0x0UL)        /**< FLASH base address  */
+#define FLASH_MEM_SIZE       (0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END        (0xFFFFFFFUL)  /**< FLASH end address  */
+#define FLASH_MEM_BITS       (0x28UL)       /**< FLASH used bits  */
+#define AES_MEM_BASE         (0x400E0000UL) /**< AES base address  */
+#define AES_MEM_SIZE         (0x400UL)      /**< AES available address space  */
+#define AES_MEM_END          (0x400E03FFUL) /**< AES end address  */
+#define AES_MEM_BITS         (0x10UL)       /**< AES used bits  */
+
+/** Flash and SRAM limits for EFM32HG322F64 */
+#define FLASH_BASE           (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE           (0x00010000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE      1024U          /**< Flash Memory page size */
+#define SRAM_BASE            (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE            (0x00002000UL) /**< Available SRAM Memory */
+#define __CM0PLUS_REV        0x0001U        /**< Cortex-M0+ Core revision r0p1 */
+#define PRS_CHAN_COUNT       6              /**< Number of PRS channels */
+#define DMA_CHAN_COUNT       6              /**< Number of DMA channels */
+#define EXT_IRQ_COUNT        21             /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX           42U
+#define AFCHANLOC_MAX        7U
+/** Analog AF channels */
+#define AFACHAN_MAX          27U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT           /**< TIMER is available in this part */
+#define TIMER_COUNT           3 /**< 3 TIMERs available  */
+#define ACMP_PRESENT            /**< ACMP is available in this part */
+#define ACMP_COUNT            1 /**< 1 ACMPs available  */
+#define USART_PRESENT           /**< USART is available in this part */
+#define USART_COUNT           2 /**< 2 USARTs available  */
+#define IDAC_PRESENT            /**< IDAC is available in this part */
+#define IDAC_COUNT            1 /**< 1 IDACs available  */
+#define ADC_PRESENT             /**< ADC is available in this part */
+#define ADC_COUNT             1 /**< 1 ADCs available  */
+#define LEUART_PRESENT          /**< LEUART is available in this part */
+#define LEUART_COUNT          1 /**< 1 LEUARTs available  */
+#define PCNT_PRESENT            /**< PCNT is available in this part */
+#define PCNT_COUNT            1 /**< 1 PCNTs available  */
+#define I2C_PRESENT             /**< I2C is available in this part */
+#define I2C_COUNT             1 /**< 1 I2Cs available  */
+#define AES_PRESENT             /**< AES is available in this part */
+#define AES_COUNT             1 /**< 1 AES available */
+#define DMA_PRESENT             /**< DMA is available in this part */
+#define DMA_COUNT             1 /**< 1 DMA available */
+#define LE_PRESENT              /**< LE is available in this part */
+#define LE_COUNT              1 /**< 1 LE available */
+#define USBC_PRESENT            /**< USBC is available in this part */
+#define USBC_COUNT            1 /**< 1 USBC available */
+#define USBLE_PRESENT           /**< USBLE is available in this part */
+#define USBLE_COUNT           1 /**< 1 USBLE available */
+#define USB_PRESENT             /**< USB is available in this part */
+#define USB_COUNT             1 /**< 1 USB available */
+#define MSC_PRESENT             /**< MSC is available in this part */
+#define MSC_COUNT             1 /**< 1 MSC available */
+#define EMU_PRESENT             /**< EMU is available in this part */
+#define EMU_COUNT             1 /**< 1 EMU available */
+#define RMU_PRESENT             /**< RMU is available in this part */
+#define RMU_COUNT             1 /**< 1 RMU available */
+#define CMU_PRESENT             /**< CMU is available in this part */
+#define CMU_COUNT             1 /**< 1 CMU available */
+#define PRS_PRESENT             /**< PRS is available in this part */
+#define PRS_COUNT             1 /**< 1 PRS available */
+#define GPIO_PRESENT            /**< GPIO is available in this part */
+#define GPIO_COUNT            1 /**< 1 GPIO available */
+#define VCMP_PRESENT            /**< VCMP is available in this part */
+#define VCMP_COUNT            1 /**< 1 VCMP available */
+#define RTC_PRESENT             /**< RTC is available in this part */
+#define RTC_COUNT             1 /**< 1 RTC available */
+#define HFXTAL_PRESENT          /**< HFXTAL is available in this part */
+#define HFXTAL_COUNT          1 /**< 1 HFXTAL available */
+#define LFXTAL_PRESENT          /**< LFXTAL is available in this part */
+#define LFXTAL_COUNT          1 /**< 1 LFXTAL available */
+#define USHFRCO_PRESENT         /**< USHFRCO is available in this part */
+#define USHFRCO_COUNT         1 /**< 1 USHFRCO available */
+#define WDOG_PRESENT            /**< WDOG is available in this part */
+#define WDOG_COUNT            1 /**< 1 WDOG available */
+#define DBG_PRESENT             /**< DBG is available in this part */
+#define DBG_COUNT             1 /**< 1 DBG available */
+#define MTB_PRESENT             /**< MTB is available in this part */
+#define MTB_COUNT             1 /**< 1 MTB available */
+#define BOOTLOADER_PRESENT      /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT      1 /**< 1 BOOTLOADER available */
+#define ANALOG_PRESENT          /**< ANALOG is available in this part */
+#define ANALOG_COUNT          1 /**< 1 ANALOG available */
+
+/** @} End of group EFM32HG322F64_Part */
+
+#ifndef ARM_MATH_CM0PLUS
+#define ARM_MATH_CM0PLUS
+#endif
+#include "arm_math.h"     /* To get __CLZ definitions etc. */
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_efm32hg.h" /* System Header */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F64_Peripheral_TypeDefs EFM32HG322F64 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efm32hg_aes.h"
+#include "efm32hg_dma_ch.h"
+#include "efm32hg_dma.h"
+#include "efm32hg_usb_diep.h"
+#include "efm32hg_usb_doep.h"
+#include "efm32hg_usb.h"
+#include "efm32hg_msc.h"
+#include "efm32hg_emu.h"
+#include "efm32hg_rmu.h"
+#include "efm32hg_cmu.h"
+#include "efm32hg_timer_cc.h"
+#include "efm32hg_timer.h"
+#include "efm32hg_acmp.h"
+#include "efm32hg_usart.h"
+#include "efm32hg_prs_ch.h"
+#include "efm32hg_prs.h"
+#include "efm32hg_idac.h"
+#include "efm32hg_gpio_p.h"
+#include "efm32hg_gpio.h"
+#include "efm32hg_vcmp.h"
+#include "efm32hg_adc.h"
+#include "efm32hg_leuart.h"
+#include "efm32hg_pcnt.h"
+#include "efm32hg_i2c.h"
+#include "efm32hg_rtc.h"
+#include "efm32hg_wdog.h"
+#include "efm32hg_mtb.h"
+#include "efm32hg_dma_descriptor.h"
+#include "efm32hg_devinfo.h"
+#include "efm32hg_romtable.h"
+#include "efm32hg_calibrate.h"
+
+/** @} End of group EFM32HG322F64_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F64_Peripheral_Base EFM32HG322F64 Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define AES_BASE          (0x400E0000UL) /**< AES base address  */
+#define DMA_BASE          (0x400C2000UL) /**< DMA base address  */
+#define USB_BASE          (0x400C4000UL) /**< USB base address  */
+#define MSC_BASE          (0x400C0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400C6000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400CA000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400C8000UL) /**< CMU base address  */
+#define TIMER0_BASE       (0x40010000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40010400UL) /**< TIMER1 base address  */
+#define TIMER2_BASE       (0x40010800UL) /**< TIMER2 base address  */
+#define ACMP0_BASE        (0x40001000UL) /**< ACMP0 base address  */
+#define USART0_BASE       (0x4000C000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x4000C400UL) /**< USART1 base address  */
+#define PRS_BASE          (0x400CC000UL) /**< PRS base address  */
+#define IDAC0_BASE        (0x40004000UL) /**< IDAC0 base address  */
+#define GPIO_BASE         (0x40006000UL) /**< GPIO base address  */
+#define VCMP_BASE         (0x40000000UL) /**< VCMP base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define LEUART0_BASE      (0x40084000UL) /**< LEUART0 base address  */
+#define PCNT0_BASE        (0x40086000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000A000UL) /**< I2C0 base address  */
+#define RTC_BASE          (0x40080000UL) /**< RTC base address  */
+#define WDOG_BASE         (0x40088000UL) /**< WDOG base address  */
+#define MTB_BASE          (0xF0040000UL) /**< MTB base address  */
+#define CALIBRATE_BASE    (0x0FE08000UL) /**< CALIBRATE base address */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xF00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32HG322F64_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F64_Peripheral_Declaration  EFM32HG322F64 Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define AES          ((AES_TypeDef *) AES_BASE)             /**< AES base pointer */
+#define DMA          ((DMA_TypeDef *) DMA_BASE)             /**< DMA base pointer */
+#define USB          ((USB_TypeDef *) USB_BASE)             /**< USB base pointer */
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        /**< TIMER2 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           /**< VCMP base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define RTC          ((RTC_TypeDef *) RTC_BASE)             /**< RTC base pointer */
+#define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           /**< WDOG base pointer */
+#define MTB          ((MTB_TypeDef *) MTB_BASE)             /**< MTB base pointer */
+#define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32HG322F64_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F64_BitFields EFM32HG322F64 Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_prs_signals.h"
+#include "efm32hg_dmareq.h"
+#include "efm32hg_dmactrl.h"
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F64_UNLOCK EFM32HG322F64 Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+
+/** @} End of group EFM32HG322F64_UNLOCK */
+
+/** @} End of group EFM32HG322F64_BitFields */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG322F64_Alternate_Function EFM32HG322F64 Alternate Function
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_af_ports.h"
+#include "efm32hg_af_pins.h"
+
+/** @} End of group EFM32HG322F64_Alternate_Function */
+
+/***************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32HG322F64 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFM32HG322F64_H */

cpu/efm32/families/efm32hg/include/vendor/efm32hg350f32.h

@@ -0,0 +1,410 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32HG350F32
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+#ifndef EFM32HG350F32_H
+#define EFM32HG350F32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F32 EFM32HG350F32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
+  NonMaskableInt_IRQn = -14,                /*!< -14 Cortex-M0+ Non Maskable Interrupt   */
+  HardFault_IRQn      = -13,                /*!< -13 Cortex-M0+ Hard Fault Interrupt     */
+  SVCall_IRQn         = -5,                 /*!< -5  Cortex-M0+ SV Call Interrupt        */
+  PendSV_IRQn         = -2,                 /*!< -2  Cortex-M0+ Pend SV Interrupt        */
+  SysTick_IRQn        = -1,                 /*!< -1  Cortex-M0+ System Tick Interrupt    */
+
+/******  EFM32HG Peripheral Interrupt Numbers ********************************************/
+  DMA_IRQn            = 0,  /*!< 0 EFM32 DMA Interrupt */
+  GPIO_EVEN_IRQn      = 1,  /*!< 1 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn         = 2,  /*!< 2 EFM32 TIMER0 Interrupt */
+  ACMP0_IRQn          = 3,  /*!< 3 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn           = 4,  /*!< 4 EFM32 ADC0 Interrupt */
+  I2C0_IRQn           = 5,  /*!< 5 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn       = 6,  /*!< 6 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn         = 7,  /*!< 7 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn      = 8,  /*!< 8 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn      = 9,  /*!< 9 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn        = 10, /*!< 10 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn          = 11, /*!< 11 EFM32 PCNT0 Interrupt */
+  RTC_IRQn            = 12, /*!< 12 EFM32 RTC Interrupt */
+  CMU_IRQn            = 13, /*!< 13 EFM32 CMU Interrupt */
+  VCMP_IRQn           = 14, /*!< 14 EFM32 VCMP Interrupt */
+  MSC_IRQn            = 15, /*!< 15 EFM32 MSC Interrupt */
+  AES_IRQn            = 16, /*!< 16 EFM32 AES Interrupt */
+  USART0_RX_IRQn      = 17, /*!< 17 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn      = 18, /*!< 18 EFM32 USART0_TX Interrupt */
+  USB_IRQn            = 19, /*!< 19 EFM32 USB Interrupt */
+  TIMER2_IRQn         = 20, /*!< 20 EFM32 TIMER2 Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F32_Core EFM32HG350F32 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT             0U /**< MPU not present */
+#define __VTOR_PRESENT            1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS          2U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32HG350F32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F32_Part EFM32HG350F32 Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFM32_HAPPY_FAMILY                     1  /**< Happy Gecko EFM32HG MCU Family */
+#define _EFM_DEVICE                                /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_SERIES_0                 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES                0  /**< Silicon Labs series number */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID       77 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_77       /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_PLATFORM_1               /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM              1  /**< @deprecated Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32HG350F32)
+#define EFM32HG350F32    1 /**< Happy Gecko Part  */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER          "EFM32HG350F32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define RAM_MEM_BASE         (0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE         (0x40000UL)    /**< RAM available address space  */
+#define RAM_MEM_END          (0x2003FFFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS         (0x18UL)       /**< RAM used bits  */
+#define DEVICE_MEM_BASE      (0xF0040000UL) /**< DEVICE base address  */
+#define DEVICE_MEM_SIZE      (0x1000UL)     /**< DEVICE available address space  */
+#define DEVICE_MEM_END       (0xF0040FFFUL) /**< DEVICE end address  */
+#define DEVICE_MEM_BITS      (0x12UL)       /**< DEVICE used bits  */
+#define USBC_MEM_BASE        (0x40100000UL) /**< USBC base address  */
+#define USBC_MEM_SIZE        (0x40000UL)    /**< USBC available address space  */
+#define USBC_MEM_END         (0x4013FFFFUL) /**< USBC end address  */
+#define USBC_MEM_BITS        (0x18UL)       /**< USBC used bits  */
+#define RAM_CODE_MEM_BASE    (0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE    (0x20000UL)    /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END     (0x1001FFFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS    (0x17UL)       /**< RAM_CODE used bits  */
+#define PER_MEM_BASE         (0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE         (0xE0000UL)    /**< PER available address space  */
+#define PER_MEM_END          (0x400DFFFFUL) /**< PER end address  */
+#define PER_MEM_BITS         (0x20UL)       /**< PER used bits  */
+#define FLASH_MEM_BASE       (0x0UL)        /**< FLASH base address  */
+#define FLASH_MEM_SIZE       (0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END        (0xFFFFFFFUL)  /**< FLASH end address  */
+#define FLASH_MEM_BITS       (0x28UL)       /**< FLASH used bits  */
+#define AES_MEM_BASE         (0x400E0000UL) /**< AES base address  */
+#define AES_MEM_SIZE         (0x400UL)      /**< AES available address space  */
+#define AES_MEM_END          (0x400E03FFUL) /**< AES end address  */
+#define AES_MEM_BITS         (0x10UL)       /**< AES used bits  */
+
+/** Flash and SRAM limits for EFM32HG350F32 */
+#define FLASH_BASE           (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE           (0x00008000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE      1024U          /**< Flash Memory page size */
+#define SRAM_BASE            (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE            (0x00002000UL) /**< Available SRAM Memory */
+#define __CM0PLUS_REV        0x0001U        /**< Cortex-M0+ Core revision r0p1 */
+#define PRS_CHAN_COUNT       6              /**< Number of PRS channels */
+#define DMA_CHAN_COUNT       6              /**< Number of DMA channels */
+#define EXT_IRQ_COUNT        21             /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX           42U
+#define AFCHANLOC_MAX        7U
+/** Analog AF channels */
+#define AFACHAN_MAX          27U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT           /**< TIMER is available in this part */
+#define TIMER_COUNT           3 /**< 3 TIMERs available  */
+#define ACMP_PRESENT            /**< ACMP is available in this part */
+#define ACMP_COUNT            1 /**< 1 ACMPs available  */
+#define USART_PRESENT           /**< USART is available in this part */
+#define USART_COUNT           2 /**< 2 USARTs available  */
+#define IDAC_PRESENT            /**< IDAC is available in this part */
+#define IDAC_COUNT            1 /**< 1 IDACs available  */
+#define ADC_PRESENT             /**< ADC is available in this part */
+#define ADC_COUNT             1 /**< 1 ADCs available  */
+#define LEUART_PRESENT          /**< LEUART is available in this part */
+#define LEUART_COUNT          1 /**< 1 LEUARTs available  */
+#define PCNT_PRESENT            /**< PCNT is available in this part */
+#define PCNT_COUNT            1 /**< 1 PCNTs available  */
+#define I2C_PRESENT             /**< I2C is available in this part */
+#define I2C_COUNT             1 /**< 1 I2Cs available  */
+#define AES_PRESENT             /**< AES is available in this part */
+#define AES_COUNT             1 /**< 1 AES available */
+#define DMA_PRESENT             /**< DMA is available in this part */
+#define DMA_COUNT             1 /**< 1 DMA available */
+#define LE_PRESENT              /**< LE is available in this part */
+#define LE_COUNT              1 /**< 1 LE available */
+#define USBC_PRESENT            /**< USBC is available in this part */
+#define USBC_COUNT            1 /**< 1 USBC available */
+#define USBLE_PRESENT           /**< USBLE is available in this part */
+#define USBLE_COUNT           1 /**< 1 USBLE available */
+#define USB_PRESENT             /**< USB is available in this part */
+#define USB_COUNT             1 /**< 1 USB available */
+#define MSC_PRESENT             /**< MSC is available in this part */
+#define MSC_COUNT             1 /**< 1 MSC available */
+#define EMU_PRESENT             /**< EMU is available in this part */
+#define EMU_COUNT             1 /**< 1 EMU available */
+#define RMU_PRESENT             /**< RMU is available in this part */
+#define RMU_COUNT             1 /**< 1 RMU available */
+#define CMU_PRESENT             /**< CMU is available in this part */
+#define CMU_COUNT             1 /**< 1 CMU available */
+#define PRS_PRESENT             /**< PRS is available in this part */
+#define PRS_COUNT             1 /**< 1 PRS available */
+#define GPIO_PRESENT            /**< GPIO is available in this part */
+#define GPIO_COUNT            1 /**< 1 GPIO available */
+#define VCMP_PRESENT            /**< VCMP is available in this part */
+#define VCMP_COUNT            1 /**< 1 VCMP available */
+#define RTC_PRESENT             /**< RTC is available in this part */
+#define RTC_COUNT             1 /**< 1 RTC available */
+#define HFXTAL_PRESENT          /**< HFXTAL is available in this part */
+#define HFXTAL_COUNT          1 /**< 1 HFXTAL available */
+#define LFXTAL_PRESENT          /**< LFXTAL is available in this part */
+#define LFXTAL_COUNT          1 /**< 1 LFXTAL available */
+#define USHFRCO_PRESENT         /**< USHFRCO is available in this part */
+#define USHFRCO_COUNT         1 /**< 1 USHFRCO available */
+#define WDOG_PRESENT            /**< WDOG is available in this part */
+#define WDOG_COUNT            1 /**< 1 WDOG available */
+#define DBG_PRESENT             /**< DBG is available in this part */
+#define DBG_COUNT             1 /**< 1 DBG available */
+#define MTB_PRESENT             /**< MTB is available in this part */
+#define MTB_COUNT             1 /**< 1 MTB available */
+#define BOOTLOADER_PRESENT      /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT      1 /**< 1 BOOTLOADER available */
+#define ANALOG_PRESENT          /**< ANALOG is available in this part */
+#define ANALOG_COUNT          1 /**< 1 ANALOG available */
+
+/** @} End of group EFM32HG350F32_Part */
+
+#ifndef ARM_MATH_CM0PLUS
+#define ARM_MATH_CM0PLUS
+#endif
+#include "arm_math.h"     /* To get __CLZ definitions etc. */
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_efm32hg.h" /* System Header */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F32_Peripheral_TypeDefs EFM32HG350F32 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efm32hg_aes.h"
+#include "efm32hg_dma_ch.h"
+#include "efm32hg_dma.h"
+#include "efm32hg_usb_diep.h"
+#include "efm32hg_usb_doep.h"
+#include "efm32hg_usb.h"
+#include "efm32hg_msc.h"
+#include "efm32hg_emu.h"
+#include "efm32hg_rmu.h"
+#include "efm32hg_cmu.h"
+#include "efm32hg_timer_cc.h"
+#include "efm32hg_timer.h"
+#include "efm32hg_acmp.h"
+#include "efm32hg_usart.h"
+#include "efm32hg_prs_ch.h"
+#include "efm32hg_prs.h"
+#include "efm32hg_idac.h"
+#include "efm32hg_gpio_p.h"
+#include "efm32hg_gpio.h"
+#include "efm32hg_vcmp.h"
+#include "efm32hg_adc.h"
+#include "efm32hg_leuart.h"
+#include "efm32hg_pcnt.h"
+#include "efm32hg_i2c.h"
+#include "efm32hg_rtc.h"
+#include "efm32hg_wdog.h"
+#include "efm32hg_mtb.h"
+#include "efm32hg_dma_descriptor.h"
+#include "efm32hg_devinfo.h"
+#include "efm32hg_romtable.h"
+#include "efm32hg_calibrate.h"
+
+/** @} End of group EFM32HG350F32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F32_Peripheral_Base EFM32HG350F32 Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define AES_BASE          (0x400E0000UL) /**< AES base address  */
+#define DMA_BASE          (0x400C2000UL) /**< DMA base address  */
+#define USB_BASE          (0x400C4000UL) /**< USB base address  */
+#define MSC_BASE          (0x400C0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400C6000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400CA000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400C8000UL) /**< CMU base address  */
+#define TIMER0_BASE       (0x40010000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40010400UL) /**< TIMER1 base address  */
+#define TIMER2_BASE       (0x40010800UL) /**< TIMER2 base address  */
+#define ACMP0_BASE        (0x40001000UL) /**< ACMP0 base address  */
+#define USART0_BASE       (0x4000C000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x4000C400UL) /**< USART1 base address  */
+#define PRS_BASE          (0x400CC000UL) /**< PRS base address  */
+#define IDAC0_BASE        (0x40004000UL) /**< IDAC0 base address  */
+#define GPIO_BASE         (0x40006000UL) /**< GPIO base address  */
+#define VCMP_BASE         (0x40000000UL) /**< VCMP base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define LEUART0_BASE      (0x40084000UL) /**< LEUART0 base address  */
+#define PCNT0_BASE        (0x40086000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000A000UL) /**< I2C0 base address  */
+#define RTC_BASE          (0x40080000UL) /**< RTC base address  */
+#define WDOG_BASE         (0x40088000UL) /**< WDOG base address  */
+#define MTB_BASE          (0xF0040000UL) /**< MTB base address  */
+#define CALIBRATE_BASE    (0x0FE08000UL) /**< CALIBRATE base address */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xF00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32HG350F32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F32_Peripheral_Declaration  EFM32HG350F32 Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define AES          ((AES_TypeDef *) AES_BASE)             /**< AES base pointer */
+#define DMA          ((DMA_TypeDef *) DMA_BASE)             /**< DMA base pointer */
+#define USB          ((USB_TypeDef *) USB_BASE)             /**< USB base pointer */
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        /**< TIMER2 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           /**< VCMP base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define RTC          ((RTC_TypeDef *) RTC_BASE)             /**< RTC base pointer */
+#define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           /**< WDOG base pointer */
+#define MTB          ((MTB_TypeDef *) MTB_BASE)             /**< MTB base pointer */
+#define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32HG350F32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F32_BitFields EFM32HG350F32 Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_prs_signals.h"
+#include "efm32hg_dmareq.h"
+#include "efm32hg_dmactrl.h"
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F32_UNLOCK EFM32HG350F32 Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+
+/** @} End of group EFM32HG350F32_UNLOCK */
+
+/** @} End of group EFM32HG350F32_BitFields */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F32_Alternate_Function EFM32HG350F32 Alternate Function
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_af_ports.h"
+#include "efm32hg_af_pins.h"
+
+/** @} End of group EFM32HG350F32_Alternate_Function */
+
+/***************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32HG350F32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFM32HG350F32_H */

cpu/efm32/families/efm32hg/include/vendor/efm32hg350f64.h

@@ -0,0 +1,410 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ *        for EFM32HG350F64
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+#ifndef EFM32HG350F64_H
+#define EFM32HG350F64_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F64 EFM32HG350F64
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
+  NonMaskableInt_IRQn = -14,                /*!< -14 Cortex-M0+ Non Maskable Interrupt   */
+  HardFault_IRQn      = -13,                /*!< -13 Cortex-M0+ Hard Fault Interrupt     */
+  SVCall_IRQn         = -5,                 /*!< -5  Cortex-M0+ SV Call Interrupt        */
+  PendSV_IRQn         = -2,                 /*!< -2  Cortex-M0+ Pend SV Interrupt        */
+  SysTick_IRQn        = -1,                 /*!< -1  Cortex-M0+ System Tick Interrupt    */
+
+/******  EFM32HG Peripheral Interrupt Numbers ********************************************/
+  DMA_IRQn            = 0,  /*!< 0 EFM32 DMA Interrupt */
+  GPIO_EVEN_IRQn      = 1,  /*!< 1 EFM32 GPIO_EVEN Interrupt */
+  TIMER0_IRQn         = 2,  /*!< 2 EFM32 TIMER0 Interrupt */
+  ACMP0_IRQn          = 3,  /*!< 3 EFM32 ACMP0 Interrupt */
+  ADC0_IRQn           = 4,  /*!< 4 EFM32 ADC0 Interrupt */
+  I2C0_IRQn           = 5,  /*!< 5 EFM32 I2C0 Interrupt */
+  GPIO_ODD_IRQn       = 6,  /*!< 6 EFM32 GPIO_ODD Interrupt */
+  TIMER1_IRQn         = 7,  /*!< 7 EFM32 TIMER1 Interrupt */
+  USART1_RX_IRQn      = 8,  /*!< 8 EFM32 USART1_RX Interrupt */
+  USART1_TX_IRQn      = 9,  /*!< 9 EFM32 USART1_TX Interrupt */
+  LEUART0_IRQn        = 10, /*!< 10 EFM32 LEUART0 Interrupt */
+  PCNT0_IRQn          = 11, /*!< 11 EFM32 PCNT0 Interrupt */
+  RTC_IRQn            = 12, /*!< 12 EFM32 RTC Interrupt */
+  CMU_IRQn            = 13, /*!< 13 EFM32 CMU Interrupt */
+  VCMP_IRQn           = 14, /*!< 14 EFM32 VCMP Interrupt */
+  MSC_IRQn            = 15, /*!< 15 EFM32 MSC Interrupt */
+  AES_IRQn            = 16, /*!< 16 EFM32 AES Interrupt */
+  USART0_RX_IRQn      = 17, /*!< 17 EFM32 USART0_RX Interrupt */
+  USART0_TX_IRQn      = 18, /*!< 18 EFM32 USART0_TX Interrupt */
+  USB_IRQn            = 19, /*!< 19 EFM32 USB Interrupt */
+  TIMER2_IRQn         = 20, /*!< 20 EFM32 TIMER2 Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F64_Core EFM32HG350F64 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT             0U /**< MPU not present */
+#define __VTOR_PRESENT            1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS          2U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig    0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFM32HG350F64_Core */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F64_Part EFM32HG350F64 Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFM32_HAPPY_FAMILY                     1  /**< Happy Gecko EFM32HG MCU Family */
+#define _EFM_DEVICE                                /**< Silicon Labs EFM-type microcontroller */
+#define _SILICON_LABS_32B_SERIES_0                 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES                0  /**< Silicon Labs series number */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID       77 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_77       /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_PLATFORM_1               /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM              1  /**< @deprecated Silicon Labs platform name */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFM32HG350F64)
+#define EFM32HG350F64    1 /**< Happy Gecko Part  */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER          "EFM32HG350F64" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define RAM_MEM_BASE         (0x20000000UL) /**< RAM base address  */
+#define RAM_MEM_SIZE         (0x40000UL)    /**< RAM available address space  */
+#define RAM_MEM_END          (0x2003FFFFUL) /**< RAM end address  */
+#define RAM_MEM_BITS         (0x18UL)       /**< RAM used bits  */
+#define DEVICE_MEM_BASE      (0xF0040000UL) /**< DEVICE base address  */
+#define DEVICE_MEM_SIZE      (0x1000UL)     /**< DEVICE available address space  */
+#define DEVICE_MEM_END       (0xF0040FFFUL) /**< DEVICE end address  */
+#define DEVICE_MEM_BITS      (0x12UL)       /**< DEVICE used bits  */
+#define USBC_MEM_BASE        (0x40100000UL) /**< USBC base address  */
+#define USBC_MEM_SIZE        (0x40000UL)    /**< USBC available address space  */
+#define USBC_MEM_END         (0x4013FFFFUL) /**< USBC end address  */
+#define USBC_MEM_BITS        (0x18UL)       /**< USBC used bits  */
+#define RAM_CODE_MEM_BASE    (0x10000000UL) /**< RAM_CODE base address  */
+#define RAM_CODE_MEM_SIZE    (0x20000UL)    /**< RAM_CODE available address space  */
+#define RAM_CODE_MEM_END     (0x1001FFFFUL) /**< RAM_CODE end address  */
+#define RAM_CODE_MEM_BITS    (0x17UL)       /**< RAM_CODE used bits  */
+#define PER_MEM_BASE         (0x40000000UL) /**< PER base address  */
+#define PER_MEM_SIZE         (0xE0000UL)    /**< PER available address space  */
+#define PER_MEM_END          (0x400DFFFFUL) /**< PER end address  */
+#define PER_MEM_BITS         (0x20UL)       /**< PER used bits  */
+#define FLASH_MEM_BASE       (0x0UL)        /**< FLASH base address  */
+#define FLASH_MEM_SIZE       (0x10000000UL) /**< FLASH available address space  */
+#define FLASH_MEM_END        (0xFFFFFFFUL)  /**< FLASH end address  */
+#define FLASH_MEM_BITS       (0x28UL)       /**< FLASH used bits  */
+#define AES_MEM_BASE         (0x400E0000UL) /**< AES base address  */
+#define AES_MEM_SIZE         (0x400UL)      /**< AES available address space  */
+#define AES_MEM_END          (0x400E03FFUL) /**< AES end address  */
+#define AES_MEM_BITS         (0x10UL)       /**< AES used bits  */
+
+/** Flash and SRAM limits for EFM32HG350F64 */
+#define FLASH_BASE           (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE           (0x00010000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE      1024U          /**< Flash Memory page size */
+#define SRAM_BASE            (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE            (0x00002000UL) /**< Available SRAM Memory */
+#define __CM0PLUS_REV        0x0001U        /**< Cortex-M0+ Core revision r0p1 */
+#define PRS_CHAN_COUNT       6              /**< Number of PRS channels */
+#define DMA_CHAN_COUNT       6              /**< Number of DMA channels */
+#define EXT_IRQ_COUNT        21             /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX           42U
+#define AFCHANLOC_MAX        7U
+/** Analog AF channels */
+#define AFACHAN_MAX          27U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT           /**< TIMER is available in this part */
+#define TIMER_COUNT           3 /**< 3 TIMERs available  */
+#define ACMP_PRESENT            /**< ACMP is available in this part */
+#define ACMP_COUNT            1 /**< 1 ACMPs available  */
+#define USART_PRESENT           /**< USART is available in this part */
+#define USART_COUNT           2 /**< 2 USARTs available  */
+#define IDAC_PRESENT            /**< IDAC is available in this part */
+#define IDAC_COUNT            1 /**< 1 IDACs available  */
+#define ADC_PRESENT             /**< ADC is available in this part */
+#define ADC_COUNT             1 /**< 1 ADCs available  */
+#define LEUART_PRESENT          /**< LEUART is available in this part */
+#define LEUART_COUNT          1 /**< 1 LEUARTs available  */
+#define PCNT_PRESENT            /**< PCNT is available in this part */
+#define PCNT_COUNT            1 /**< 1 PCNTs available  */
+#define I2C_PRESENT             /**< I2C is available in this part */
+#define I2C_COUNT             1 /**< 1 I2Cs available  */
+#define AES_PRESENT             /**< AES is available in this part */
+#define AES_COUNT             1 /**< 1 AES available */
+#define DMA_PRESENT             /**< DMA is available in this part */
+#define DMA_COUNT             1 /**< 1 DMA available */
+#define LE_PRESENT              /**< LE is available in this part */
+#define LE_COUNT              1 /**< 1 LE available */
+#define USBC_PRESENT            /**< USBC is available in this part */
+#define USBC_COUNT            1 /**< 1 USBC available */
+#define USBLE_PRESENT           /**< USBLE is available in this part */
+#define USBLE_COUNT           1 /**< 1 USBLE available */
+#define USB_PRESENT             /**< USB is available in this part */
+#define USB_COUNT             1 /**< 1 USB available */
+#define MSC_PRESENT             /**< MSC is available in this part */
+#define MSC_COUNT             1 /**< 1 MSC available */
+#define EMU_PRESENT             /**< EMU is available in this part */
+#define EMU_COUNT             1 /**< 1 EMU available */
+#define RMU_PRESENT             /**< RMU is available in this part */
+#define RMU_COUNT             1 /**< 1 RMU available */
+#define CMU_PRESENT             /**< CMU is available in this part */
+#define CMU_COUNT             1 /**< 1 CMU available */
+#define PRS_PRESENT             /**< PRS is available in this part */
+#define PRS_COUNT             1 /**< 1 PRS available */
+#define GPIO_PRESENT            /**< GPIO is available in this part */
+#define GPIO_COUNT            1 /**< 1 GPIO available */
+#define VCMP_PRESENT            /**< VCMP is available in this part */
+#define VCMP_COUNT            1 /**< 1 VCMP available */
+#define RTC_PRESENT             /**< RTC is available in this part */
+#define RTC_COUNT             1 /**< 1 RTC available */
+#define HFXTAL_PRESENT          /**< HFXTAL is available in this part */
+#define HFXTAL_COUNT          1 /**< 1 HFXTAL available */
+#define LFXTAL_PRESENT          /**< LFXTAL is available in this part */
+#define LFXTAL_COUNT          1 /**< 1 LFXTAL available */
+#define USHFRCO_PRESENT         /**< USHFRCO is available in this part */
+#define USHFRCO_COUNT         1 /**< 1 USHFRCO available */
+#define WDOG_PRESENT            /**< WDOG is available in this part */
+#define WDOG_COUNT            1 /**< 1 WDOG available */
+#define DBG_PRESENT             /**< DBG is available in this part */
+#define DBG_COUNT             1 /**< 1 DBG available */
+#define MTB_PRESENT             /**< MTB is available in this part */
+#define MTB_COUNT             1 /**< 1 MTB available */
+#define BOOTLOADER_PRESENT      /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT      1 /**< 1 BOOTLOADER available */
+#define ANALOG_PRESENT          /**< ANALOG is available in this part */
+#define ANALOG_COUNT          1 /**< 1 ANALOG available */
+
+/** @} End of group EFM32HG350F64_Part */
+
+#ifndef ARM_MATH_CM0PLUS
+#define ARM_MATH_CM0PLUS
+#endif
+#include "arm_math.h"     /* To get __CLZ definitions etc. */
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_efm32hg.h" /* System Header */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F64_Peripheral_TypeDefs EFM32HG350F64 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efm32hg_aes.h"
+#include "efm32hg_dma_ch.h"
+#include "efm32hg_dma.h"
+#include "efm32hg_usb_diep.h"
+#include "efm32hg_usb_doep.h"
+#include "efm32hg_usb.h"
+#include "efm32hg_msc.h"
+#include "efm32hg_emu.h"
+#include "efm32hg_rmu.h"
+#include "efm32hg_cmu.h"
+#include "efm32hg_timer_cc.h"
+#include "efm32hg_timer.h"
+#include "efm32hg_acmp.h"
+#include "efm32hg_usart.h"
+#include "efm32hg_prs_ch.h"
+#include "efm32hg_prs.h"
+#include "efm32hg_idac.h"
+#include "efm32hg_gpio_p.h"
+#include "efm32hg_gpio.h"
+#include "efm32hg_vcmp.h"
+#include "efm32hg_adc.h"
+#include "efm32hg_leuart.h"
+#include "efm32hg_pcnt.h"
+#include "efm32hg_i2c.h"
+#include "efm32hg_rtc.h"
+#include "efm32hg_wdog.h"
+#include "efm32hg_mtb.h"
+#include "efm32hg_dma_descriptor.h"
+#include "efm32hg_devinfo.h"
+#include "efm32hg_romtable.h"
+#include "efm32hg_calibrate.h"
+
+/** @} End of group EFM32HG350F64_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F64_Peripheral_Base EFM32HG350F64 Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define AES_BASE          (0x400E0000UL) /**< AES base address  */
+#define DMA_BASE          (0x400C2000UL) /**< DMA base address  */
+#define USB_BASE          (0x400C4000UL) /**< USB base address  */
+#define MSC_BASE          (0x400C0000UL) /**< MSC base address  */
+#define EMU_BASE          (0x400C6000UL) /**< EMU base address  */
+#define RMU_BASE          (0x400CA000UL) /**< RMU base address  */
+#define CMU_BASE          (0x400C8000UL) /**< CMU base address  */
+#define TIMER0_BASE       (0x40010000UL) /**< TIMER0 base address  */
+#define TIMER1_BASE       (0x40010400UL) /**< TIMER1 base address  */
+#define TIMER2_BASE       (0x40010800UL) /**< TIMER2 base address  */
+#define ACMP0_BASE        (0x40001000UL) /**< ACMP0 base address  */
+#define USART0_BASE       (0x4000C000UL) /**< USART0 base address  */
+#define USART1_BASE       (0x4000C400UL) /**< USART1 base address  */
+#define PRS_BASE          (0x400CC000UL) /**< PRS base address  */
+#define IDAC0_BASE        (0x40004000UL) /**< IDAC0 base address  */
+#define GPIO_BASE         (0x40006000UL) /**< GPIO base address  */
+#define VCMP_BASE         (0x40000000UL) /**< VCMP base address  */
+#define ADC0_BASE         (0x40002000UL) /**< ADC0 base address  */
+#define LEUART0_BASE      (0x40084000UL) /**< LEUART0 base address  */
+#define PCNT0_BASE        (0x40086000UL) /**< PCNT0 base address  */
+#define I2C0_BASE         (0x4000A000UL) /**< I2C0 base address  */
+#define RTC_BASE          (0x40080000UL) /**< RTC base address  */
+#define WDOG_BASE         (0x40088000UL) /**< WDOG base address  */
+#define MTB_BASE          (0xF0040000UL) /**< MTB base address  */
+#define CALIBRATE_BASE    (0x0FE08000UL) /**< CALIBRATE base address */
+#define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE     (0xF00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFM32HG350F64_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F64_Peripheral_Declaration  EFM32HG350F64 Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define AES          ((AES_TypeDef *) AES_BASE)             /**< AES base pointer */
+#define DMA          ((DMA_TypeDef *) DMA_BASE)             /**< DMA base pointer */
+#define USB          ((USB_TypeDef *) USB_BASE)             /**< USB base pointer */
+#define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
+#define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
+#define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
+#define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
+#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
+#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
+#define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        /**< TIMER2 base pointer */
+#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
+#define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
+#define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
+#define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
+#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
+#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
+#define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           /**< VCMP base pointer */
+#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
+#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
+#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
+#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
+#define RTC          ((RTC_TypeDef *) RTC_BASE)             /**< RTC base pointer */
+#define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           /**< WDOG base pointer */
+#define MTB          ((MTB_TypeDef *) MTB_BASE)             /**< MTB base pointer */
+#define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
+#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
+#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
+
+/** @} End of group EFM32HG350F64_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F64_BitFields EFM32HG350F64 Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_prs_signals.h"
+#include "efm32hg_dmareq.h"
+#include "efm32hg_dmactrl.h"
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F64_UNLOCK EFM32HG350F64 Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
+#define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
+#define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
+#define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
+
+/** @} End of group EFM32HG350F64_UNLOCK */
+
+/** @} End of group EFM32HG350F64_BitFields */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG350F64_Alternate_Function EFM32HG350F64 Alternate Function
+ * @{
+ ******************************************************************************/
+
+#include "efm32hg_af_ports.h"
+#include "efm32hg_af_pins.h"
+
+/** @} End of group EFM32HG350F64_Alternate_Function */
+
+/***************************************************************************//**
+ *  @brief Set the value of a bit field within a register.
+ *
+ *  @param REG
+ *       The register to update
+ *  @param MASK
+ *       The mask for the bit field to update
+ *  @param VALUE
+ *       The value to write to the bit field
+ *  @param OFFSET
+ *       The number of bits that the field is offset within the register.
+ *       0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFM32HG350F64 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFM32HG350F64_H */

cpu/efm32/families/efm32hg/include/vendor/efm32hg_acmp.h

@@ -0,0 +1,345 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_ACMP register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_ACMP
+ * @{
+ * @brief EFM32HG_ACMP Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;     /**< Control Register  */
+  __IOM uint32_t INPUTSEL; /**< Input Selection Register  */
+  __IM uint32_t  STATUS;   /**< Status Register  */
+  __IOM uint32_t IEN;      /**< Interrupt Enable Register  */
+  __IM uint32_t  IF;       /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;      /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;      /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t ROUTE;    /**< I/O Routing Register  */
+} ACMP_TypeDef;            /**< ACMP Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_ACMP_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for ACMP CTRL */
+#define _ACMP_CTRL_RESETVALUE              0x47000000UL                         /**< Default value for ACMP_CTRL */
+#define _ACMP_CTRL_MASK                    0xCF03077FUL                         /**< Mask for ACMP_CTRL */
+#define ACMP_CTRL_EN                       (0x1UL << 0)                         /**< Analog Comparator Enable */
+#define _ACMP_CTRL_EN_SHIFT                0                                    /**< Shift value for ACMP_EN */
+#define _ACMP_CTRL_EN_MASK                 0x1UL                                /**< Bit mask for ACMP_EN */
+#define _ACMP_CTRL_EN_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_EN_DEFAULT               (_ACMP_CTRL_EN_DEFAULT << 0)         /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_MUXEN                    (0x1UL << 1)                         /**< Input Mux Enable */
+#define _ACMP_CTRL_MUXEN_SHIFT             1                                    /**< Shift value for ACMP_MUXEN */
+#define _ACMP_CTRL_MUXEN_MASK              0x2UL                                /**< Bit mask for ACMP_MUXEN */
+#define _ACMP_CTRL_MUXEN_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_MUXEN_DEFAULT            (_ACMP_CTRL_MUXEN_DEFAULT << 1)      /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL                 (0x1UL << 2)                         /**< Inactive Value */
+#define _ACMP_CTRL_INACTVAL_SHIFT          2                                    /**< Shift value for ACMP_INACTVAL */
+#define _ACMP_CTRL_INACTVAL_MASK           0x4UL                                /**< Bit mask for ACMP_INACTVAL */
+#define _ACMP_CTRL_INACTVAL_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_INACTVAL_LOW            0x00000000UL                         /**< Mode LOW for ACMP_CTRL */
+#define _ACMP_CTRL_INACTVAL_HIGH           0x00000001UL                         /**< Mode HIGH for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL_DEFAULT         (_ACMP_CTRL_INACTVAL_DEFAULT << 2)   /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL_LOW             (_ACMP_CTRL_INACTVAL_LOW << 2)       /**< Shifted mode LOW for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL_HIGH            (_ACMP_CTRL_INACTVAL_HIGH << 2)      /**< Shifted mode HIGH for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV                  (0x1UL << 3)                         /**< Comparator GPIO Output Invert */
+#define _ACMP_CTRL_GPIOINV_SHIFT           3                                    /**< Shift value for ACMP_GPIOINV */
+#define _ACMP_CTRL_GPIOINV_MASK            0x8UL                                /**< Bit mask for ACMP_GPIOINV */
+#define _ACMP_CTRL_GPIOINV_DEFAULT         0x00000000UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_GPIOINV_NOTINV          0x00000000UL                         /**< Mode NOTINV for ACMP_CTRL */
+#define _ACMP_CTRL_GPIOINV_INV             0x00000001UL                         /**< Mode INV for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_DEFAULT          (_ACMP_CTRL_GPIOINV_DEFAULT << 3)    /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_NOTINV           (_ACMP_CTRL_GPIOINV_NOTINV << 3)     /**< Shifted mode NOTINV for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_INV              (_ACMP_CTRL_GPIOINV_INV << 3)        /**< Shifted mode INV for ACMP_CTRL */
+#define _ACMP_CTRL_HYSTSEL_SHIFT           4                                    /**< Shift value for ACMP_HYSTSEL */
+#define _ACMP_CTRL_HYSTSEL_MASK            0x70UL                               /**< Bit mask for ACMP_HYSTSEL */
+#define _ACMP_CTRL_HYSTSEL_DEFAULT         0x00000000UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_HYSTSEL_HYST0           0x00000000UL                         /**< Mode HYST0 for ACMP_CTRL */
+#define _ACMP_CTRL_HYSTSEL_HYST1           0x00000001UL                         /**< Mode HYST1 for ACMP_CTRL */
+#define _ACMP_CTRL_HYSTSEL_HYST2           0x00000002UL                         /**< Mode HYST2 for ACMP_CTRL */
+#define _ACMP_CTRL_HYSTSEL_HYST3           0x00000003UL                         /**< Mode HYST3 for ACMP_CTRL */
+#define _ACMP_CTRL_HYSTSEL_HYST4           0x00000004UL                         /**< Mode HYST4 for ACMP_CTRL */
+#define _ACMP_CTRL_HYSTSEL_HYST5           0x00000005UL                         /**< Mode HYST5 for ACMP_CTRL */
+#define _ACMP_CTRL_HYSTSEL_HYST6           0x00000006UL                         /**< Mode HYST6 for ACMP_CTRL */
+#define _ACMP_CTRL_HYSTSEL_HYST7           0x00000007UL                         /**< Mode HYST7 for ACMP_CTRL */
+#define ACMP_CTRL_HYSTSEL_DEFAULT          (_ACMP_CTRL_HYSTSEL_DEFAULT << 4)    /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_HYSTSEL_HYST0            (_ACMP_CTRL_HYSTSEL_HYST0 << 4)      /**< Shifted mode HYST0 for ACMP_CTRL */
+#define ACMP_CTRL_HYSTSEL_HYST1            (_ACMP_CTRL_HYSTSEL_HYST1 << 4)      /**< Shifted mode HYST1 for ACMP_CTRL */
+#define ACMP_CTRL_HYSTSEL_HYST2            (_ACMP_CTRL_HYSTSEL_HYST2 << 4)      /**< Shifted mode HYST2 for ACMP_CTRL */
+#define ACMP_CTRL_HYSTSEL_HYST3            (_ACMP_CTRL_HYSTSEL_HYST3 << 4)      /**< Shifted mode HYST3 for ACMP_CTRL */
+#define ACMP_CTRL_HYSTSEL_HYST4            (_ACMP_CTRL_HYSTSEL_HYST4 << 4)      /**< Shifted mode HYST4 for ACMP_CTRL */
+#define ACMP_CTRL_HYSTSEL_HYST5            (_ACMP_CTRL_HYSTSEL_HYST5 << 4)      /**< Shifted mode HYST5 for ACMP_CTRL */
+#define ACMP_CTRL_HYSTSEL_HYST6            (_ACMP_CTRL_HYSTSEL_HYST6 << 4)      /**< Shifted mode HYST6 for ACMP_CTRL */
+#define ACMP_CTRL_HYSTSEL_HYST7            (_ACMP_CTRL_HYSTSEL_HYST7 << 4)      /**< Shifted mode HYST7 for ACMP_CTRL */
+#define _ACMP_CTRL_WARMTIME_SHIFT          8                                    /**< Shift value for ACMP_WARMTIME */
+#define _ACMP_CTRL_WARMTIME_MASK           0x700UL                              /**< Bit mask for ACMP_WARMTIME */
+#define _ACMP_CTRL_WARMTIME_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_WARMTIME_4CYCLES        0x00000000UL                         /**< Mode 4CYCLES for ACMP_CTRL */
+#define _ACMP_CTRL_WARMTIME_8CYCLES        0x00000001UL                         /**< Mode 8CYCLES for ACMP_CTRL */
+#define _ACMP_CTRL_WARMTIME_16CYCLES       0x00000002UL                         /**< Mode 16CYCLES for ACMP_CTRL */
+#define _ACMP_CTRL_WARMTIME_32CYCLES       0x00000003UL                         /**< Mode 32CYCLES for ACMP_CTRL */
+#define _ACMP_CTRL_WARMTIME_64CYCLES       0x00000004UL                         /**< Mode 64CYCLES for ACMP_CTRL */
+#define _ACMP_CTRL_WARMTIME_128CYCLES      0x00000005UL                         /**< Mode 128CYCLES for ACMP_CTRL */
+#define _ACMP_CTRL_WARMTIME_256CYCLES      0x00000006UL                         /**< Mode 256CYCLES for ACMP_CTRL */
+#define _ACMP_CTRL_WARMTIME_512CYCLES      0x00000007UL                         /**< Mode 512CYCLES for ACMP_CTRL */
+#define ACMP_CTRL_WARMTIME_DEFAULT         (_ACMP_CTRL_WARMTIME_DEFAULT << 8)   /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_WARMTIME_4CYCLES         (_ACMP_CTRL_WARMTIME_4CYCLES << 8)   /**< Shifted mode 4CYCLES for ACMP_CTRL */
+#define ACMP_CTRL_WARMTIME_8CYCLES         (_ACMP_CTRL_WARMTIME_8CYCLES << 8)   /**< Shifted mode 8CYCLES for ACMP_CTRL */
+#define ACMP_CTRL_WARMTIME_16CYCLES        (_ACMP_CTRL_WARMTIME_16CYCLES << 8)  /**< Shifted mode 16CYCLES for ACMP_CTRL */
+#define ACMP_CTRL_WARMTIME_32CYCLES        (_ACMP_CTRL_WARMTIME_32CYCLES << 8)  /**< Shifted mode 32CYCLES for ACMP_CTRL */
+#define ACMP_CTRL_WARMTIME_64CYCLES        (_ACMP_CTRL_WARMTIME_64CYCLES << 8)  /**< Shifted mode 64CYCLES for ACMP_CTRL */
+#define ACMP_CTRL_WARMTIME_128CYCLES       (_ACMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for ACMP_CTRL */
+#define ACMP_CTRL_WARMTIME_256CYCLES       (_ACMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for ACMP_CTRL */
+#define ACMP_CTRL_WARMTIME_512CYCLES       (_ACMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for ACMP_CTRL */
+#define ACMP_CTRL_IRISE                    (0x1UL << 16)                        /**< Rising Edge Interrupt Sense */
+#define _ACMP_CTRL_IRISE_SHIFT             16                                   /**< Shift value for ACMP_IRISE */
+#define _ACMP_CTRL_IRISE_MASK              0x10000UL                            /**< Bit mask for ACMP_IRISE */
+#define _ACMP_CTRL_IRISE_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_IRISE_DISABLED          0x00000000UL                         /**< Mode DISABLED for ACMP_CTRL */
+#define _ACMP_CTRL_IRISE_ENABLED           0x00000001UL                         /**< Mode ENABLED for ACMP_CTRL */
+#define ACMP_CTRL_IRISE_DEFAULT            (_ACMP_CTRL_IRISE_DEFAULT << 16)     /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_IRISE_DISABLED           (_ACMP_CTRL_IRISE_DISABLED << 16)    /**< Shifted mode DISABLED for ACMP_CTRL */
+#define ACMP_CTRL_IRISE_ENABLED            (_ACMP_CTRL_IRISE_ENABLED << 16)     /**< Shifted mode ENABLED for ACMP_CTRL */
+#define ACMP_CTRL_IFALL                    (0x1UL << 17)                        /**< Falling Edge Interrupt Sense */
+#define _ACMP_CTRL_IFALL_SHIFT             17                                   /**< Shift value for ACMP_IFALL */
+#define _ACMP_CTRL_IFALL_MASK              0x20000UL                            /**< Bit mask for ACMP_IFALL */
+#define _ACMP_CTRL_IFALL_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_IFALL_DISABLED          0x00000000UL                         /**< Mode DISABLED for ACMP_CTRL */
+#define _ACMP_CTRL_IFALL_ENABLED           0x00000001UL                         /**< Mode ENABLED for ACMP_CTRL */
+#define ACMP_CTRL_IFALL_DEFAULT            (_ACMP_CTRL_IFALL_DEFAULT << 17)     /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_IFALL_DISABLED           (_ACMP_CTRL_IFALL_DISABLED << 17)    /**< Shifted mode DISABLED for ACMP_CTRL */
+#define ACMP_CTRL_IFALL_ENABLED            (_ACMP_CTRL_IFALL_ENABLED << 17)     /**< Shifted mode ENABLED for ACMP_CTRL */
+#define _ACMP_CTRL_BIASPROG_SHIFT          24                                   /**< Shift value for ACMP_BIASPROG */
+#define _ACMP_CTRL_BIASPROG_MASK           0xF000000UL                          /**< Bit mask for ACMP_BIASPROG */
+#define _ACMP_CTRL_BIASPROG_DEFAULT        0x00000007UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_BIASPROG_DEFAULT         (_ACMP_CTRL_BIASPROG_DEFAULT << 24)  /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_HALFBIAS                 (0x1UL << 30)                        /**< Half Bias Current */
+#define _ACMP_CTRL_HALFBIAS_SHIFT          30                                   /**< Shift value for ACMP_HALFBIAS */
+#define _ACMP_CTRL_HALFBIAS_MASK           0x40000000UL                         /**< Bit mask for ACMP_HALFBIAS */
+#define _ACMP_CTRL_HALFBIAS_DEFAULT        0x00000001UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_HALFBIAS_DEFAULT         (_ACMP_CTRL_HALFBIAS_DEFAULT << 30)  /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_FULLBIAS                 (0x1UL << 31)                        /**< Full Bias Current */
+#define _ACMP_CTRL_FULLBIAS_SHIFT          31                                   /**< Shift value for ACMP_FULLBIAS */
+#define _ACMP_CTRL_FULLBIAS_MASK           0x80000000UL                         /**< Bit mask for ACMP_FULLBIAS */
+#define _ACMP_CTRL_FULLBIAS_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_FULLBIAS_DEFAULT         (_ACMP_CTRL_FULLBIAS_DEFAULT << 31)  /**< Shifted mode DEFAULT for ACMP_CTRL */
+
+/* Bit fields for ACMP INPUTSEL */
+#define _ACMP_INPUTSEL_RESETVALUE          0x00010080UL                            /**< Default value for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_MASK                0x31013FF7UL                            /**< Mask for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_SHIFT        0                                       /**< Shift value for ACMP_POSSEL */
+#define _ACMP_INPUTSEL_POSSEL_MASK         0x7UL                                   /**< Bit mask for ACMP_POSSEL */
+#define _ACMP_INPUTSEL_POSSEL_DEFAULT      0x00000000UL                            /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_CH0          0x00000000UL                            /**< Mode CH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_CH1          0x00000001UL                            /**< Mode CH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_CH2          0x00000002UL                            /**< Mode CH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_CH3          0x00000003UL                            /**< Mode CH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_CH4          0x00000004UL                            /**< Mode CH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_CH5          0x00000005UL                            /**< Mode CH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_CH6          0x00000006UL                            /**< Mode CH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_CH7          0x00000007UL                            /**< Mode CH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_DEFAULT       (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0)    /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_CH0           (_ACMP_INPUTSEL_POSSEL_CH0 << 0)        /**< Shifted mode CH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_CH1           (_ACMP_INPUTSEL_POSSEL_CH1 << 0)        /**< Shifted mode CH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_CH2           (_ACMP_INPUTSEL_POSSEL_CH2 << 0)        /**< Shifted mode CH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_CH3           (_ACMP_INPUTSEL_POSSEL_CH3 << 0)        /**< Shifted mode CH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_CH4           (_ACMP_INPUTSEL_POSSEL_CH4 << 0)        /**< Shifted mode CH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_CH5           (_ACMP_INPUTSEL_POSSEL_CH5 << 0)        /**< Shifted mode CH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_CH6           (_ACMP_INPUTSEL_POSSEL_CH6 << 0)        /**< Shifted mode CH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_CH7           (_ACMP_INPUTSEL_POSSEL_CH7 << 0)        /**< Shifted mode CH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_SHIFT        4                                       /**< Shift value for ACMP_NEGSEL */
+#define _ACMP_INPUTSEL_NEGSEL_MASK         0xF0UL                                  /**< Bit mask for ACMP_NEGSEL */
+#define _ACMP_INPUTSEL_NEGSEL_CH0          0x00000000UL                            /**< Mode CH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_CH1          0x00000001UL                            /**< Mode CH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_CH2          0x00000002UL                            /**< Mode CH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_CH3          0x00000003UL                            /**< Mode CH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_CH4          0x00000004UL                            /**< Mode CH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_CH5          0x00000005UL                            /**< Mode CH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_CH6          0x00000006UL                            /**< Mode CH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_CH7          0x00000007UL                            /**< Mode CH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_DEFAULT      0x00000008UL                            /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_1V25         0x00000008UL                            /**< Mode 1V25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_2V5          0x00000009UL                            /**< Mode 2V5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VDD          0x0000000AUL                            /**< Mode VDD for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_CAPSENSE     0x0000000BUL                            /**< Mode CAPSENSE for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_CH0           (_ACMP_INPUTSEL_NEGSEL_CH0 << 4)        /**< Shifted mode CH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_CH1           (_ACMP_INPUTSEL_NEGSEL_CH1 << 4)        /**< Shifted mode CH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_CH2           (_ACMP_INPUTSEL_NEGSEL_CH2 << 4)        /**< Shifted mode CH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_CH3           (_ACMP_INPUTSEL_NEGSEL_CH3 << 4)        /**< Shifted mode CH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_CH4           (_ACMP_INPUTSEL_NEGSEL_CH4 << 4)        /**< Shifted mode CH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_CH5           (_ACMP_INPUTSEL_NEGSEL_CH5 << 4)        /**< Shifted mode CH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_CH6           (_ACMP_INPUTSEL_NEGSEL_CH6 << 4)        /**< Shifted mode CH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_CH7           (_ACMP_INPUTSEL_NEGSEL_CH7 << 4)        /**< Shifted mode CH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_DEFAULT       (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 4)    /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_1V25          (_ACMP_INPUTSEL_NEGSEL_1V25 << 4)       /**< Shifted mode 1V25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_2V5           (_ACMP_INPUTSEL_NEGSEL_2V5 << 4)        /**< Shifted mode 2V5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VDD           (_ACMP_INPUTSEL_NEGSEL_VDD << 4)        /**< Shifted mode VDD for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_CAPSENSE      (_ACMP_INPUTSEL_NEGSEL_CAPSENSE << 4)   /**< Shifted mode CAPSENSE for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VDDLEVEL_SHIFT      8                                       /**< Shift value for ACMP_VDDLEVEL */
+#define _ACMP_INPUTSEL_VDDLEVEL_MASK       0x3F00UL                                /**< Bit mask for ACMP_VDDLEVEL */
+#define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT    0x00000000UL                            /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VDDLEVEL_DEFAULT     (_ACMP_INPUTSEL_VDDLEVEL_DEFAULT << 8)  /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_LPREF                (0x1UL << 16)                           /**< Low Power Reference Mode */
+#define _ACMP_INPUTSEL_LPREF_SHIFT         16                                      /**< Shift value for ACMP_LPREF */
+#define _ACMP_INPUTSEL_LPREF_MASK          0x10000UL                               /**< Bit mask for ACMP_LPREF */
+#define _ACMP_INPUTSEL_LPREF_DEFAULT       0x00000001UL                            /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_LPREF_DEFAULT        (_ACMP_INPUTSEL_LPREF_DEFAULT << 16)    /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESEN              (0x1UL << 24)                           /**< Capacitive Sense Mode Internal Resistor Enable */
+#define _ACMP_INPUTSEL_CSRESEN_SHIFT       24                                      /**< Shift value for ACMP_CSRESEN */
+#define _ACMP_INPUTSEL_CSRESEN_MASK        0x1000000UL                             /**< Bit mask for ACMP_CSRESEN */
+#define _ACMP_INPUTSEL_CSRESEN_DEFAULT     0x00000000UL                            /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESEN_DEFAULT      (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 24)  /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_SHIFT      28                                      /**< Shift value for ACMP_CSRESSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_MASK       0x30000000UL                            /**< Bit mask for ACMP_CSRESSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT    0x00000000UL                            /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES0       0x00000000UL                            /**< Mode RES0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES1       0x00000001UL                            /**< Mode RES1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES2       0x00000002UL                            /**< Mode RES2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES3       0x00000003UL                            /**< Mode RES3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_DEFAULT     (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES0        (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28)    /**< Shifted mode RES0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES1        (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28)    /**< Shifted mode RES1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES2        (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28)    /**< Shifted mode RES2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES3        (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28)    /**< Shifted mode RES3 for ACMP_INPUTSEL */
+
+/* Bit fields for ACMP STATUS */
+#define _ACMP_STATUS_RESETVALUE            0x00000000UL                        /**< Default value for ACMP_STATUS */
+#define _ACMP_STATUS_MASK                  0x00000003UL                        /**< Mask for ACMP_STATUS */
+#define ACMP_STATUS_ACMPACT                (0x1UL << 0)                        /**< Analog Comparator Active */
+#define _ACMP_STATUS_ACMPACT_SHIFT         0                                   /**< Shift value for ACMP_ACMPACT */
+#define _ACMP_STATUS_ACMPACT_MASK          0x1UL                               /**< Bit mask for ACMP_ACMPACT */
+#define _ACMP_STATUS_ACMPACT_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPACT_DEFAULT        (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPOUT                (0x1UL << 1)                        /**< Analog Comparator Output */
+#define _ACMP_STATUS_ACMPOUT_SHIFT         1                                   /**< Shift value for ACMP_ACMPOUT */
+#define _ACMP_STATUS_ACMPOUT_MASK          0x2UL                               /**< Bit mask for ACMP_ACMPOUT */
+#define _ACMP_STATUS_ACMPOUT_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPOUT_DEFAULT        (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */
+
+/* Bit fields for ACMP IEN */
+#define _ACMP_IEN_RESETVALUE               0x00000000UL                    /**< Default value for ACMP_IEN */
+#define _ACMP_IEN_MASK                     0x00000003UL                    /**< Mask for ACMP_IEN */
+#define ACMP_IEN_EDGE                      (0x1UL << 0)                    /**< Edge Trigger Interrupt Enable */
+#define _ACMP_IEN_EDGE_SHIFT               0                               /**< Shift value for ACMP_EDGE */
+#define _ACMP_IEN_EDGE_MASK                0x1UL                           /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IEN_EDGE_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_EDGE_DEFAULT              (_ACMP_IEN_EDGE_DEFAULT << 0)   /**< Shifted mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_WARMUP                    (0x1UL << 1)                    /**< Warm-up Interrupt Enable */
+#define _ACMP_IEN_WARMUP_SHIFT             1                               /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IEN_WARMUP_MASK              0x2UL                           /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IEN_WARMUP_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_WARMUP_DEFAULT            (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */
+
+/* Bit fields for ACMP IF */
+#define _ACMP_IF_RESETVALUE                0x00000000UL                   /**< Default value for ACMP_IF */
+#define _ACMP_IF_MASK                      0x00000003UL                   /**< Mask for ACMP_IF */
+#define ACMP_IF_EDGE                       (0x1UL << 0)                   /**< Edge Triggered Interrupt Flag */
+#define _ACMP_IF_EDGE_SHIFT                0                              /**< Shift value for ACMP_EDGE */
+#define _ACMP_IF_EDGE_MASK                 0x1UL                          /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IF_EDGE_DEFAULT              0x00000000UL                   /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_EDGE_DEFAULT               (_ACMP_IF_EDGE_DEFAULT << 0)   /**< Shifted mode DEFAULT for ACMP_IF */
+#define ACMP_IF_WARMUP                     (0x1UL << 1)                   /**< Warm-up Interrupt Flag */
+#define _ACMP_IF_WARMUP_SHIFT              1                              /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IF_WARMUP_MASK               0x2UL                          /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IF_WARMUP_DEFAULT            0x00000000UL                   /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_WARMUP_DEFAULT             (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */
+
+/* Bit fields for ACMP IFS */
+#define _ACMP_IFS_RESETVALUE               0x00000000UL                    /**< Default value for ACMP_IFS */
+#define _ACMP_IFS_MASK                     0x00000003UL                    /**< Mask for ACMP_IFS */
+#define ACMP_IFS_EDGE                      (0x1UL << 0)                    /**< Edge Triggered Interrupt Flag Set */
+#define _ACMP_IFS_EDGE_SHIFT               0                               /**< Shift value for ACMP_EDGE */
+#define _ACMP_IFS_EDGE_MASK                0x1UL                           /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IFS_EDGE_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_EDGE_DEFAULT              (_ACMP_IFS_EDGE_DEFAULT << 0)   /**< Shifted mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_WARMUP                    (0x1UL << 1)                    /**< Warm-up Interrupt Flag Set */
+#define _ACMP_IFS_WARMUP_SHIFT             1                               /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IFS_WARMUP_MASK              0x2UL                           /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IFS_WARMUP_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_WARMUP_DEFAULT            (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */
+
+/* Bit fields for ACMP IFC */
+#define _ACMP_IFC_RESETVALUE               0x00000000UL                    /**< Default value for ACMP_IFC */
+#define _ACMP_IFC_MASK                     0x00000003UL                    /**< Mask for ACMP_IFC */
+#define ACMP_IFC_EDGE                      (0x1UL << 0)                    /**< Edge Triggered Interrupt Flag Clear */
+#define _ACMP_IFC_EDGE_SHIFT               0                               /**< Shift value for ACMP_EDGE */
+#define _ACMP_IFC_EDGE_MASK                0x1UL                           /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IFC_EDGE_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_EDGE_DEFAULT              (_ACMP_IFC_EDGE_DEFAULT << 0)   /**< Shifted mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_WARMUP                    (0x1UL << 1)                    /**< Warm-up Interrupt Flag Clear */
+#define _ACMP_IFC_WARMUP_SHIFT             1                               /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IFC_WARMUP_MASK              0x2UL                           /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IFC_WARMUP_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_WARMUP_DEFAULT            (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */
+
+/* Bit fields for ACMP ROUTE */
+#define _ACMP_ROUTE_RESETVALUE             0x00000000UL                        /**< Default value for ACMP_ROUTE */
+#define _ACMP_ROUTE_MASK                   0x00000701UL                        /**< Mask for ACMP_ROUTE */
+#define ACMP_ROUTE_ACMPPEN                 (0x1UL << 0)                        /**< ACMP Output Pin Enable */
+#define _ACMP_ROUTE_ACMPPEN_SHIFT          0                                   /**< Shift value for ACMP_ACMPPEN */
+#define _ACMP_ROUTE_ACMPPEN_MASK           0x1UL                               /**< Bit mask for ACMP_ACMPPEN */
+#define _ACMP_ROUTE_ACMPPEN_DEFAULT        0x00000000UL                        /**< Mode DEFAULT for ACMP_ROUTE */
+#define ACMP_ROUTE_ACMPPEN_DEFAULT         (_ACMP_ROUTE_ACMPPEN_DEFAULT << 0)  /**< Shifted mode DEFAULT for ACMP_ROUTE */
+#define _ACMP_ROUTE_LOCATION_SHIFT         8                                   /**< Shift value for ACMP_LOCATION */
+#define _ACMP_ROUTE_LOCATION_MASK          0x700UL                             /**< Bit mask for ACMP_LOCATION */
+#define _ACMP_ROUTE_LOCATION_LOC0          0x00000000UL                        /**< Mode LOC0 for ACMP_ROUTE */
+#define _ACMP_ROUTE_LOCATION_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for ACMP_ROUTE */
+#define _ACMP_ROUTE_LOCATION_LOC1          0x00000001UL                        /**< Mode LOC1 for ACMP_ROUTE */
+#define _ACMP_ROUTE_LOCATION_LOC2          0x00000002UL                        /**< Mode LOC2 for ACMP_ROUTE */
+#define _ACMP_ROUTE_LOCATION_LOC3          0x00000003UL                        /**< Mode LOC3 for ACMP_ROUTE */
+#define ACMP_ROUTE_LOCATION_LOC0           (_ACMP_ROUTE_LOCATION_LOC0 << 8)    /**< Shifted mode LOC0 for ACMP_ROUTE */
+#define ACMP_ROUTE_LOCATION_DEFAULT        (_ACMP_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_ROUTE */
+#define ACMP_ROUTE_LOCATION_LOC1           (_ACMP_ROUTE_LOCATION_LOC1 << 8)    /**< Shifted mode LOC1 for ACMP_ROUTE */
+#define ACMP_ROUTE_LOCATION_LOC2           (_ACMP_ROUTE_LOCATION_LOC2 << 8)    /**< Shifted mode LOC2 for ACMP_ROUTE */
+#define ACMP_ROUTE_LOCATION_LOC3           (_ACMP_ROUTE_LOCATION_LOC3 << 8)    /**< Shifted mode LOC3 for ACMP_ROUTE */
+
+/** @} End of group EFM32HG_ACMP */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_adc.h

@@ -0,0 +1,671 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_ADC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_ADC
+ * @{
+ * @brief EFM32HG_ADC Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;          /**< Control Register  */
+  __IOM uint32_t CMD;           /**< Command Register  */
+  __IM uint32_t  STATUS;        /**< Status Register  */
+  __IOM uint32_t SINGLECTRL;    /**< Single Sample Control Register  */
+  __IOM uint32_t SCANCTRL;      /**< Scan Control Register  */
+  __IOM uint32_t IEN;           /**< Interrupt Enable Register  */
+  __IM uint32_t  IF;            /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;           /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;           /**< Interrupt Flag Clear Register  */
+  __IM uint32_t  SINGLEDATA;    /**< Single Conversion Result Data  */
+  __IM uint32_t  SCANDATA;      /**< Scan Conversion Result Data  */
+  __IM uint32_t  SINGLEDATAP;   /**< Single Conversion Result Data Peek Register  */
+  __IM uint32_t  SCANDATAP;     /**< Scan Sequence Result Data Peek Register  */
+  __IOM uint32_t CAL;           /**< Calibration Register  */
+
+  uint32_t       RESERVED0[1U]; /**< Reserved for future use **/
+  __IOM uint32_t BIASPROG;      /**< Bias Programming Register  */
+} ADC_TypeDef;                  /**< ADC Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_ADC_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for ADC CTRL */
+#define _ADC_CTRL_RESETVALUE                    0x001F0000UL                                /**< Default value for ADC_CTRL */
+#define _ADC_CTRL_MASK                          0x1F7F7F3BUL                                /**< Mask for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_SHIFT              0                                           /**< Shift value for ADC_WARMUPMODE */
+#define _ADC_CTRL_WARMUPMODE_MASK               0x3UL                                       /**< Bit mask for ADC_WARMUPMODE */
+#define _ADC_CTRL_WARMUPMODE_DEFAULT            0x00000000UL                                /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_NORMAL             0x00000000UL                                /**< Mode NORMAL for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_FASTBG             0x00000001UL                                /**< Mode FASTBG for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM    0x00000002UL                                /**< Mode KEEPSCANREFWARM for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM        0x00000003UL                                /**< Mode KEEPADCWARM for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_DEFAULT             (_ADC_CTRL_WARMUPMODE_DEFAULT << 0)         /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_NORMAL              (_ADC_CTRL_WARMUPMODE_NORMAL << 0)          /**< Shifted mode NORMAL for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_FASTBG              (_ADC_CTRL_WARMUPMODE_FASTBG << 0)          /**< Shifted mode FASTBG for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM     (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0) /**< Shifted mode KEEPSCANREFWARM for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_KEEPADCWARM         (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0)     /**< Shifted mode KEEPADCWARM for ADC_CTRL */
+#define ADC_CTRL_TAILGATE                       (0x1UL << 3)                                /**< Conversion Tailgating */
+#define _ADC_CTRL_TAILGATE_SHIFT                3                                           /**< Shift value for ADC_TAILGATE */
+#define _ADC_CTRL_TAILGATE_MASK                 0x8UL                                       /**< Bit mask for ADC_TAILGATE */
+#define _ADC_CTRL_TAILGATE_DEFAULT              0x00000000UL                                /**< Mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_TAILGATE_DEFAULT               (_ADC_CTRL_TAILGATE_DEFAULT << 3)           /**< Shifted mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_LPFMODE_SHIFT                 4                                           /**< Shift value for ADC_LPFMODE */
+#define _ADC_CTRL_LPFMODE_MASK                  0x30UL                                      /**< Bit mask for ADC_LPFMODE */
+#define _ADC_CTRL_LPFMODE_DEFAULT               0x00000000UL                                /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_LPFMODE_BYPASS                0x00000000UL                                /**< Mode BYPASS for ADC_CTRL */
+#define _ADC_CTRL_LPFMODE_DECAP                 0x00000001UL                                /**< Mode DECAP for ADC_CTRL */
+#define _ADC_CTRL_LPFMODE_RCFILT                0x00000002UL                                /**< Mode RCFILT for ADC_CTRL */
+#define ADC_CTRL_LPFMODE_DEFAULT                (_ADC_CTRL_LPFMODE_DEFAULT << 4)            /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_LPFMODE_BYPASS                 (_ADC_CTRL_LPFMODE_BYPASS << 4)             /**< Shifted mode BYPASS for ADC_CTRL */
+#define ADC_CTRL_LPFMODE_DECAP                  (_ADC_CTRL_LPFMODE_DECAP << 4)              /**< Shifted mode DECAP for ADC_CTRL */
+#define ADC_CTRL_LPFMODE_RCFILT                 (_ADC_CTRL_LPFMODE_RCFILT << 4)             /**< Shifted mode RCFILT for ADC_CTRL */
+#define _ADC_CTRL_PRESC_SHIFT                   8                                           /**< Shift value for ADC_PRESC */
+#define _ADC_CTRL_PRESC_MASK                    0x7F00UL                                    /**< Bit mask for ADC_PRESC */
+#define _ADC_CTRL_PRESC_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_PRESC_NODIVISION              0x00000000UL                                /**< Mode NODIVISION for ADC_CTRL */
+#define ADC_CTRL_PRESC_DEFAULT                  (_ADC_CTRL_PRESC_DEFAULT << 8)              /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_PRESC_NODIVISION               (_ADC_CTRL_PRESC_NODIVISION << 8)           /**< Shifted mode NODIVISION for ADC_CTRL */
+#define _ADC_CTRL_TIMEBASE_SHIFT                16                                          /**< Shift value for ADC_TIMEBASE */
+#define _ADC_CTRL_TIMEBASE_MASK                 0x7F0000UL                                  /**< Bit mask for ADC_TIMEBASE */
+#define _ADC_CTRL_TIMEBASE_DEFAULT              0x0000001FUL                                /**< Mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_TIMEBASE_DEFAULT               (_ADC_CTRL_TIMEBASE_DEFAULT << 16)          /**< Shifted mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_SHIFT                 24                                          /**< Shift value for ADC_OVSRSEL */
+#define _ADC_CTRL_OVSRSEL_MASK                  0xF000000UL                                 /**< Bit mask for ADC_OVSRSEL */
+#define _ADC_CTRL_OVSRSEL_DEFAULT               0x00000000UL                                /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X2                    0x00000000UL                                /**< Mode X2 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X4                    0x00000001UL                                /**< Mode X4 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X8                    0x00000002UL                                /**< Mode X8 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X16                   0x00000003UL                                /**< Mode X16 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X32                   0x00000004UL                                /**< Mode X32 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X64                   0x00000005UL                                /**< Mode X64 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X128                  0x00000006UL                                /**< Mode X128 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X256                  0x00000007UL                                /**< Mode X256 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X512                  0x00000008UL                                /**< Mode X512 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X1024                 0x00000009UL                                /**< Mode X1024 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X2048                 0x0000000AUL                                /**< Mode X2048 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X4096                 0x0000000BUL                                /**< Mode X4096 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_DEFAULT                (_ADC_CTRL_OVSRSEL_DEFAULT << 24)           /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X2                     (_ADC_CTRL_OVSRSEL_X2 << 24)                /**< Shifted mode X2 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X4                     (_ADC_CTRL_OVSRSEL_X4 << 24)                /**< Shifted mode X4 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X8                     (_ADC_CTRL_OVSRSEL_X8 << 24)                /**< Shifted mode X8 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X16                    (_ADC_CTRL_OVSRSEL_X16 << 24)               /**< Shifted mode X16 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X32                    (_ADC_CTRL_OVSRSEL_X32 << 24)               /**< Shifted mode X32 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X64                    (_ADC_CTRL_OVSRSEL_X64 << 24)               /**< Shifted mode X64 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X128                   (_ADC_CTRL_OVSRSEL_X128 << 24)              /**< Shifted mode X128 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X256                   (_ADC_CTRL_OVSRSEL_X256 << 24)              /**< Shifted mode X256 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X512                   (_ADC_CTRL_OVSRSEL_X512 << 24)              /**< Shifted mode X512 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X1024                  (_ADC_CTRL_OVSRSEL_X1024 << 24)             /**< Shifted mode X1024 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X2048                  (_ADC_CTRL_OVSRSEL_X2048 << 24)             /**< Shifted mode X2048 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X4096                  (_ADC_CTRL_OVSRSEL_X4096 << 24)             /**< Shifted mode X4096 for ADC_CTRL */
+#define ADC_CTRL_CHCONIDLE                      (0x1UL << 28)                               /**< Input channel connected when ADC is IDLE */
+#define _ADC_CTRL_CHCONIDLE_SHIFT               28                                          /**< Shift value for ADC_CHCONIDLE */
+#define _ADC_CTRL_CHCONIDLE_MASK                0x10000000UL                                /**< Bit mask for ADC_CHCONIDLE */
+#define _ADC_CTRL_CHCONIDLE_DEFAULT             0x00000000UL                                /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_CHCONIDLE_DISCONNECT          0x00000000UL                                /**< Mode DISCONNECT for ADC_CTRL */
+#define _ADC_CTRL_CHCONIDLE_KEEPCON             0x00000001UL                                /**< Mode KEEPCON for ADC_CTRL */
+#define ADC_CTRL_CHCONIDLE_DEFAULT              (_ADC_CTRL_CHCONIDLE_DEFAULT << 28)         /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_CHCONIDLE_DISCONNECT           (_ADC_CTRL_CHCONIDLE_DISCONNECT << 28)      /**< Shifted mode DISCONNECT for ADC_CTRL */
+#define ADC_CTRL_CHCONIDLE_KEEPCON              (_ADC_CTRL_CHCONIDLE_KEEPCON << 28)         /**< Shifted mode KEEPCON for ADC_CTRL */
+
+/* Bit fields for ADC CMD */
+#define _ADC_CMD_RESETVALUE                     0x00000000UL                        /**< Default value for ADC_CMD */
+#define _ADC_CMD_MASK                           0x0000000FUL                        /**< Mask for ADC_CMD */
+#define ADC_CMD_SINGLESTART                     (0x1UL << 0)                        /**< Single Conversion Start */
+#define _ADC_CMD_SINGLESTART_SHIFT              0                                   /**< Shift value for ADC_SINGLESTART */
+#define _ADC_CMD_SINGLESTART_MASK               0x1UL                               /**< Bit mask for ADC_SINGLESTART */
+#define _ADC_CMD_SINGLESTART_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SINGLESTART_DEFAULT             (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SINGLESTOP                      (0x1UL << 1)                        /**< Single Conversion Stop */
+#define _ADC_CMD_SINGLESTOP_SHIFT               1                                   /**< Shift value for ADC_SINGLESTOP */
+#define _ADC_CMD_SINGLESTOP_MASK                0x2UL                               /**< Bit mask for ADC_SINGLESTOP */
+#define _ADC_CMD_SINGLESTOP_DEFAULT             0x00000000UL                        /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SINGLESTOP_DEFAULT              (_ADC_CMD_SINGLESTOP_DEFAULT << 1)  /**< Shifted mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTART                       (0x1UL << 2)                        /**< Scan Sequence Start */
+#define _ADC_CMD_SCANSTART_SHIFT                2                                   /**< Shift value for ADC_SCANSTART */
+#define _ADC_CMD_SCANSTART_MASK                 0x4UL                               /**< Bit mask for ADC_SCANSTART */
+#define _ADC_CMD_SCANSTART_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTART_DEFAULT               (_ADC_CMD_SCANSTART_DEFAULT << 2)   /**< Shifted mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTOP                        (0x1UL << 3)                        /**< Scan Sequence Stop */
+#define _ADC_CMD_SCANSTOP_SHIFT                 3                                   /**< Shift value for ADC_SCANSTOP */
+#define _ADC_CMD_SCANSTOP_MASK                  0x8UL                               /**< Bit mask for ADC_SCANSTOP */
+#define _ADC_CMD_SCANSTOP_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTOP_DEFAULT                (_ADC_CMD_SCANSTOP_DEFAULT << 3)    /**< Shifted mode DEFAULT for ADC_CMD */
+
+/* Bit fields for ADC STATUS */
+#define _ADC_STATUS_RESETVALUE                  0x00000000UL                             /**< Default value for ADC_STATUS */
+#define _ADC_STATUS_MASK                        0x07031303UL                             /**< Mask for ADC_STATUS */
+#define ADC_STATUS_SINGLEACT                    (0x1UL << 0)                             /**< Single Conversion Active */
+#define _ADC_STATUS_SINGLEACT_SHIFT             0                                        /**< Shift value for ADC_SINGLEACT */
+#define _ADC_STATUS_SINGLEACT_MASK              0x1UL                                    /**< Bit mask for ADC_SINGLEACT */
+#define _ADC_STATUS_SINGLEACT_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEACT_DEFAULT            (_ADC_STATUS_SINGLEACT_DEFAULT << 0)     /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANACT                      (0x1UL << 1)                             /**< Scan Conversion Active */
+#define _ADC_STATUS_SCANACT_SHIFT               1                                        /**< Shift value for ADC_SCANACT */
+#define _ADC_STATUS_SCANACT_MASK                0x2UL                                    /**< Bit mask for ADC_SCANACT */
+#define _ADC_STATUS_SCANACT_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANACT_DEFAULT              (_ADC_STATUS_SCANACT_DEFAULT << 1)       /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEREFWARM                (0x1UL << 8)                             /**< Single Reference Warmed Up */
+#define _ADC_STATUS_SINGLEREFWARM_SHIFT         8                                        /**< Shift value for ADC_SINGLEREFWARM */
+#define _ADC_STATUS_SINGLEREFWARM_MASK          0x100UL                                  /**< Bit mask for ADC_SINGLEREFWARM */
+#define _ADC_STATUS_SINGLEREFWARM_DEFAULT       0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEREFWARM_DEFAULT        (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANREFWARM                  (0x1UL << 9)                             /**< Scan Reference Warmed Up */
+#define _ADC_STATUS_SCANREFWARM_SHIFT           9                                        /**< Shift value for ADC_SCANREFWARM */
+#define _ADC_STATUS_SCANREFWARM_MASK            0x200UL                                  /**< Bit mask for ADC_SCANREFWARM */
+#define _ADC_STATUS_SCANREFWARM_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANREFWARM_DEFAULT          (_ADC_STATUS_SCANREFWARM_DEFAULT << 9)   /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_WARM                         (0x1UL << 12)                            /**< ADC Warmed Up */
+#define _ADC_STATUS_WARM_SHIFT                  12                                       /**< Shift value for ADC_WARM */
+#define _ADC_STATUS_WARM_MASK                   0x1000UL                                 /**< Bit mask for ADC_WARM */
+#define _ADC_STATUS_WARM_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_WARM_DEFAULT                 (_ADC_STATUS_WARM_DEFAULT << 12)         /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEDV                     (0x1UL << 16)                            /**< Single Sample Data Valid */
+#define _ADC_STATUS_SINGLEDV_SHIFT              16                                       /**< Shift value for ADC_SINGLEDV */
+#define _ADC_STATUS_SINGLEDV_MASK               0x10000UL                                /**< Bit mask for ADC_SINGLEDV */
+#define _ADC_STATUS_SINGLEDV_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEDV_DEFAULT             (_ADC_STATUS_SINGLEDV_DEFAULT << 16)     /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANDV                       (0x1UL << 17)                            /**< Scan Data Valid */
+#define _ADC_STATUS_SCANDV_SHIFT                17                                       /**< Shift value for ADC_SCANDV */
+#define _ADC_STATUS_SCANDV_MASK                 0x20000UL                                /**< Bit mask for ADC_SCANDV */
+#define _ADC_STATUS_SCANDV_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANDV_DEFAULT               (_ADC_STATUS_SCANDV_DEFAULT << 17)       /**< Shifted mode DEFAULT for ADC_STATUS */
+#define _ADC_STATUS_SCANDATASRC_SHIFT           24                                       /**< Shift value for ADC_SCANDATASRC */
+#define _ADC_STATUS_SCANDATASRC_MASK            0x7000000UL                              /**< Bit mask for ADC_SCANDATASRC */
+#define _ADC_STATUS_SCANDATASRC_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for ADC_STATUS */
+#define _ADC_STATUS_SCANDATASRC_CH0             0x00000000UL                             /**< Mode CH0 for ADC_STATUS */
+#define _ADC_STATUS_SCANDATASRC_CH1             0x00000001UL                             /**< Mode CH1 for ADC_STATUS */
+#define _ADC_STATUS_SCANDATASRC_CH2             0x00000002UL                             /**< Mode CH2 for ADC_STATUS */
+#define _ADC_STATUS_SCANDATASRC_CH3             0x00000003UL                             /**< Mode CH3 for ADC_STATUS */
+#define _ADC_STATUS_SCANDATASRC_CH4             0x00000004UL                             /**< Mode CH4 for ADC_STATUS */
+#define _ADC_STATUS_SCANDATASRC_CH5             0x00000005UL                             /**< Mode CH5 for ADC_STATUS */
+#define _ADC_STATUS_SCANDATASRC_CH6             0x00000006UL                             /**< Mode CH6 for ADC_STATUS */
+#define _ADC_STATUS_SCANDATASRC_CH7             0x00000007UL                             /**< Mode CH7 for ADC_STATUS */
+#define ADC_STATUS_SCANDATASRC_DEFAULT          (_ADC_STATUS_SCANDATASRC_DEFAULT << 24)  /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANDATASRC_CH0              (_ADC_STATUS_SCANDATASRC_CH0 << 24)      /**< Shifted mode CH0 for ADC_STATUS */
+#define ADC_STATUS_SCANDATASRC_CH1              (_ADC_STATUS_SCANDATASRC_CH1 << 24)      /**< Shifted mode CH1 for ADC_STATUS */
+#define ADC_STATUS_SCANDATASRC_CH2              (_ADC_STATUS_SCANDATASRC_CH2 << 24)      /**< Shifted mode CH2 for ADC_STATUS */
+#define ADC_STATUS_SCANDATASRC_CH3              (_ADC_STATUS_SCANDATASRC_CH3 << 24)      /**< Shifted mode CH3 for ADC_STATUS */
+#define ADC_STATUS_SCANDATASRC_CH4              (_ADC_STATUS_SCANDATASRC_CH4 << 24)      /**< Shifted mode CH4 for ADC_STATUS */
+#define ADC_STATUS_SCANDATASRC_CH5              (_ADC_STATUS_SCANDATASRC_CH5 << 24)      /**< Shifted mode CH5 for ADC_STATUS */
+#define ADC_STATUS_SCANDATASRC_CH6              (_ADC_STATUS_SCANDATASRC_CH6 << 24)      /**< Shifted mode CH6 for ADC_STATUS */
+#define ADC_STATUS_SCANDATASRC_CH7              (_ADC_STATUS_SCANDATASRC_CH7 << 24)      /**< Shifted mode CH7 for ADC_STATUS */
+
+/* Bit fields for ADC SINGLECTRL */
+#define _ADC_SINGLECTRL_RESETVALUE              0x00000000UL                             /**< Default value for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_MASK                    0x71F70F37UL                             /**< Mask for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REP                      (0x1UL << 0)                             /**< Single Sample Repetitive Mode */
+#define _ADC_SINGLECTRL_REP_SHIFT               0                                        /**< Shift value for ADC_REP */
+#define _ADC_SINGLECTRL_REP_MASK                0x1UL                                    /**< Bit mask for ADC_REP */
+#define _ADC_SINGLECTRL_REP_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REP_DEFAULT              (_ADC_SINGLECTRL_REP_DEFAULT << 0)       /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_DIFF                     (0x1UL << 1)                             /**< Single Sample Differential Mode */
+#define _ADC_SINGLECTRL_DIFF_SHIFT              1                                        /**< Shift value for ADC_DIFF */
+#define _ADC_SINGLECTRL_DIFF_MASK               0x2UL                                    /**< Bit mask for ADC_DIFF */
+#define _ADC_SINGLECTRL_DIFF_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_DIFF_DEFAULT             (_ADC_SINGLECTRL_DIFF_DEFAULT << 1)      /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ                      (0x1UL << 2)                             /**< Single Sample Result Adjustment */
+#define _ADC_SINGLECTRL_ADJ_SHIFT               2                                        /**< Shift value for ADC_ADJ */
+#define _ADC_SINGLECTRL_ADJ_MASK                0x4UL                                    /**< Bit mask for ADC_ADJ */
+#define _ADC_SINGLECTRL_ADJ_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_ADJ_RIGHT               0x00000000UL                             /**< Mode RIGHT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_ADJ_LEFT                0x00000001UL                             /**< Mode LEFT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ_DEFAULT              (_ADC_SINGLECTRL_ADJ_DEFAULT << 2)       /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ_RIGHT                (_ADC_SINGLECTRL_ADJ_RIGHT << 2)         /**< Shifted mode RIGHT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ_LEFT                 (_ADC_SINGLECTRL_ADJ_LEFT << 2)          /**< Shifted mode LEFT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_SHIFT               4                                        /**< Shift value for ADC_RES */
+#define _ADC_SINGLECTRL_RES_MASK                0x30UL                                   /**< Bit mask for ADC_RES */
+#define _ADC_SINGLECTRL_RES_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_12BIT               0x00000000UL                             /**< Mode 12BIT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_8BIT                0x00000001UL                             /**< Mode 8BIT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_6BIT                0x00000002UL                             /**< Mode 6BIT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_OVS                 0x00000003UL                             /**< Mode OVS for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_DEFAULT              (_ADC_SINGLECTRL_RES_DEFAULT << 4)       /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_12BIT                (_ADC_SINGLECTRL_RES_12BIT << 4)         /**< Shifted mode 12BIT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_8BIT                 (_ADC_SINGLECTRL_RES_8BIT << 4)          /**< Shifted mode 8BIT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_6BIT                 (_ADC_SINGLECTRL_RES_6BIT << 4)          /**< Shifted mode 6BIT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_OVS                  (_ADC_SINGLECTRL_RES_OVS << 4)           /**< Shifted mode OVS for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_SHIFT          8                                        /**< Shift value for ADC_INPUTSEL */
+#define _ADC_SINGLECTRL_INPUTSEL_MASK           0xF00UL                                  /**< Bit mask for ADC_INPUTSEL */
+#define _ADC_SINGLECTRL_INPUTSEL_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH0CH1         0x00000000UL                             /**< Mode CH0CH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH0            0x00000000UL                             /**< Mode CH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH2CH3         0x00000001UL                             /**< Mode CH2CH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH1            0x00000001UL                             /**< Mode CH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH4CH5         0x00000002UL                             /**< Mode CH4CH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH2            0x00000002UL                             /**< Mode CH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH6CH7         0x00000003UL                             /**< Mode CH6CH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH3            0x00000003UL                             /**< Mode CH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_DIFF0          0x00000004UL                             /**< Mode DIFF0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH4            0x00000004UL                             /**< Mode CH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH5            0x00000005UL                             /**< Mode CH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH6            0x00000006UL                             /**< Mode CH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_CH7            0x00000007UL                             /**< Mode CH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_TEMP           0x00000008UL                             /**< Mode TEMP for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3        0x00000009UL                             /**< Mode VDDDIV3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_VDD            0x0000000AUL                             /**< Mode VDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_VSS            0x0000000BUL                             /**< Mode VSS for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2       0x0000000CUL                             /**< Mode VREFDIV2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0       0x0000000DUL                             /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1       0x0000000EUL                             /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_DEFAULT         (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8)  /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH0CH1          (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8)   /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH0             (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8)      /**< Shifted mode CH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH2CH3          (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8)   /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH1             (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8)      /**< Shifted mode CH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH4CH5          (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8)   /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH2             (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8)      /**< Shifted mode CH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH6CH7          (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8)   /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH3             (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8)      /**< Shifted mode CH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_DIFF0           (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8)    /**< Shifted mode DIFF0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH4             (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8)      /**< Shifted mode CH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH5             (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8)      /**< Shifted mode CH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH6             (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8)      /**< Shifted mode CH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_CH7             (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8)      /**< Shifted mode CH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_TEMP            (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8)     /**< Shifted mode TEMP for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_VDDDIV3         (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8)  /**< Shifted mode VDDDIV3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_VDD             (_ADC_SINGLECTRL_INPUTSEL_VDD << 8)      /**< Shifted mode VDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_VSS             (_ADC_SINGLECTRL_INPUTSEL_VSS << 8)      /**< Shifted mode VSS for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_VREFDIV2        (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8) /**< Shifted mode VREFDIV2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0        (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1        (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_SHIFT               16                                       /**< Shift value for ADC_REF */
+#define _ADC_SINGLECTRL_REF_MASK                0x70000UL                                /**< Bit mask for ADC_REF */
+#define _ADC_SINGLECTRL_REF_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_1V25                0x00000000UL                             /**< Mode 1V25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_2V5                 0x00000001UL                             /**< Mode 2V5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_VDD                 0x00000002UL                             /**< Mode VDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_5VDIFF              0x00000003UL                             /**< Mode 5VDIFF for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_EXTSINGLE           0x00000004UL                             /**< Mode EXTSINGLE for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_2XEXTDIFF           0x00000005UL                             /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_2XVDD               0x00000006UL                             /**< Mode 2XVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_DEFAULT              (_ADC_SINGLECTRL_REF_DEFAULT << 16)      /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_1V25                 (_ADC_SINGLECTRL_REF_1V25 << 16)         /**< Shifted mode 1V25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_2V5                  (_ADC_SINGLECTRL_REF_2V5 << 16)          /**< Shifted mode 2V5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_VDD                  (_ADC_SINGLECTRL_REF_VDD << 16)          /**< Shifted mode VDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_5VDIFF               (_ADC_SINGLECTRL_REF_5VDIFF << 16)       /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_EXTSINGLE            (_ADC_SINGLECTRL_REF_EXTSINGLE << 16)    /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_2XEXTDIFF            (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16)    /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_2XVDD                (_ADC_SINGLECTRL_REF_2XVDD << 16)        /**< Shifted mode 2XVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_SHIFT                20                                       /**< Shift value for ADC_AT */
+#define _ADC_SINGLECTRL_AT_MASK                 0xF00000UL                               /**< Bit mask for ADC_AT */
+#define _ADC_SINGLECTRL_AT_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_1CYCLE               0x00000000UL                             /**< Mode 1CYCLE for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_2CYCLES              0x00000001UL                             /**< Mode 2CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_4CYCLES              0x00000002UL                             /**< Mode 4CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_8CYCLES              0x00000003UL                             /**< Mode 8CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_16CYCLES             0x00000004UL                             /**< Mode 16CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_32CYCLES             0x00000005UL                             /**< Mode 32CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_64CYCLES             0x00000006UL                             /**< Mode 64CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_128CYCLES            0x00000007UL                             /**< Mode 128CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_256CYCLES            0x00000008UL                             /**< Mode 256CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_DEFAULT               (_ADC_SINGLECTRL_AT_DEFAULT << 20)       /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_1CYCLE                (_ADC_SINGLECTRL_AT_1CYCLE << 20)        /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_2CYCLES               (_ADC_SINGLECTRL_AT_2CYCLES << 20)       /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_4CYCLES               (_ADC_SINGLECTRL_AT_4CYCLES << 20)       /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_8CYCLES               (_ADC_SINGLECTRL_AT_8CYCLES << 20)       /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_16CYCLES              (_ADC_SINGLECTRL_AT_16CYCLES << 20)      /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_32CYCLES              (_ADC_SINGLECTRL_AT_32CYCLES << 20)      /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_64CYCLES              (_ADC_SINGLECTRL_AT_64CYCLES << 20)      /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_128CYCLES             (_ADC_SINGLECTRL_AT_128CYCLES << 20)     /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_256CYCLES             (_ADC_SINGLECTRL_AT_256CYCLES << 20)     /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSEN                    (0x1UL << 24)                            /**< Single Sample PRS Trigger Enable */
+#define _ADC_SINGLECTRL_PRSEN_SHIFT             24                                       /**< Shift value for ADC_PRSEN */
+#define _ADC_SINGLECTRL_PRSEN_MASK              0x1000000UL                              /**< Bit mask for ADC_PRSEN */
+#define _ADC_SINGLECTRL_PRSEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSEN_DEFAULT            (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24)    /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_PRSSEL_SHIFT            28                                       /**< Shift value for ADC_PRSSEL */
+#define _ADC_SINGLECTRL_PRSSEL_MASK             0x70000000UL                             /**< Bit mask for ADC_PRSSEL */
+#define _ADC_SINGLECTRL_PRSSEL_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_PRSSEL_PRSCH0           0x00000000UL                             /**< Mode PRSCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_PRSSEL_PRSCH1           0x00000001UL                             /**< Mode PRSCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_PRSSEL_PRSCH2           0x00000002UL                             /**< Mode PRSCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_PRSSEL_PRSCH3           0x00000003UL                             /**< Mode PRSCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_PRSSEL_PRSCH4           0x00000004UL                             /**< Mode PRSCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_PRSSEL_PRSCH5           0x00000005UL                             /**< Mode PRSCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSSEL_DEFAULT           (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28)   /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSSEL_PRSCH0            (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28)    /**< Shifted mode PRSCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSSEL_PRSCH1            (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28)    /**< Shifted mode PRSCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSSEL_PRSCH2            (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28)    /**< Shifted mode PRSCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSSEL_PRSCH3            (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28)    /**< Shifted mode PRSCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSSEL_PRSCH4            (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28)    /**< Shifted mode PRSCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSSEL_PRSCH5            (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28)    /**< Shifted mode PRSCH5 for ADC_SINGLECTRL */
+
+/* Bit fields for ADC SCANCTRL */
+#define _ADC_SCANCTRL_RESETVALUE                0x00000000UL                           /**< Default value for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_MASK                      0x71F7FF37UL                           /**< Mask for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REP                        (0x1UL << 0)                           /**< Scan Sequence Repetitive Mode */
+#define _ADC_SCANCTRL_REP_SHIFT                 0                                      /**< Shift value for ADC_REP */
+#define _ADC_SCANCTRL_REP_MASK                  0x1UL                                  /**< Bit mask for ADC_REP */
+#define _ADC_SCANCTRL_REP_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REP_DEFAULT                (_ADC_SCANCTRL_REP_DEFAULT << 0)       /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_DIFF                       (0x1UL << 1)                           /**< Scan Sequence Differential Mode */
+#define _ADC_SCANCTRL_DIFF_SHIFT                1                                      /**< Shift value for ADC_DIFF */
+#define _ADC_SCANCTRL_DIFF_MASK                 0x2UL                                  /**< Bit mask for ADC_DIFF */
+#define _ADC_SCANCTRL_DIFF_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_DIFF_DEFAULT               (_ADC_SCANCTRL_DIFF_DEFAULT << 1)      /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ                        (0x1UL << 2)                           /**< Scan Sequence Result Adjustment */
+#define _ADC_SCANCTRL_ADJ_SHIFT                 2                                      /**< Shift value for ADC_ADJ */
+#define _ADC_SCANCTRL_ADJ_MASK                  0x4UL                                  /**< Bit mask for ADC_ADJ */
+#define _ADC_SCANCTRL_ADJ_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_ADJ_RIGHT                 0x00000000UL                           /**< Mode RIGHT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_ADJ_LEFT                  0x00000001UL                           /**< Mode LEFT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ_DEFAULT                (_ADC_SCANCTRL_ADJ_DEFAULT << 2)       /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ_RIGHT                  (_ADC_SCANCTRL_ADJ_RIGHT << 2)         /**< Shifted mode RIGHT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ_LEFT                   (_ADC_SCANCTRL_ADJ_LEFT << 2)          /**< Shifted mode LEFT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_SHIFT                 4                                      /**< Shift value for ADC_RES */
+#define _ADC_SCANCTRL_RES_MASK                  0x30UL                                 /**< Bit mask for ADC_RES */
+#define _ADC_SCANCTRL_RES_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_12BIT                 0x00000000UL                           /**< Mode 12BIT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_8BIT                  0x00000001UL                           /**< Mode 8BIT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_6BIT                  0x00000002UL                           /**< Mode 6BIT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_OVS                   0x00000003UL                           /**< Mode OVS for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_DEFAULT                (_ADC_SCANCTRL_RES_DEFAULT << 4)       /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_12BIT                  (_ADC_SCANCTRL_RES_12BIT << 4)         /**< Shifted mode 12BIT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_8BIT                   (_ADC_SCANCTRL_RES_8BIT << 4)          /**< Shifted mode 8BIT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_6BIT                   (_ADC_SCANCTRL_RES_6BIT << 4)          /**< Shifted mode 6BIT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_OVS                    (_ADC_SCANCTRL_RES_OVS << 4)           /**< Shifted mode OVS for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_SHIFT           8                                      /**< Shift value for ADC_INPUTMASK */
+#define _ADC_SCANCTRL_INPUTMASK_MASK            0xFF00UL                               /**< Bit mask for ADC_INPUTMASK */
+#define _ADC_SCANCTRL_INPUTMASK_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH0CH1          0x00000001UL                           /**< Mode CH0CH1 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH0             0x00000001UL                           /**< Mode CH0 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH2CH3          0x00000002UL                           /**< Mode CH2CH3 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH1             0x00000002UL                           /**< Mode CH1 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH4CH5          0x00000004UL                           /**< Mode CH4CH5 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH2             0x00000004UL                           /**< Mode CH2 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH6CH7          0x00000008UL                           /**< Mode CH6CH7 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH3             0x00000008UL                           /**< Mode CH3 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH4             0x00000010UL                           /**< Mode CH4 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH5             0x00000020UL                           /**< Mode CH5 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH6             0x00000040UL                           /**< Mode CH6 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_INPUTMASK_CH7             0x00000080UL                           /**< Mode CH7 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_DEFAULT          (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH0CH1           (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8)  /**< Shifted mode CH0CH1 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH0              (_ADC_SCANCTRL_INPUTMASK_CH0 << 8)     /**< Shifted mode CH0 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH2CH3           (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8)  /**< Shifted mode CH2CH3 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH1              (_ADC_SCANCTRL_INPUTMASK_CH1 << 8)     /**< Shifted mode CH1 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH4CH5           (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8)  /**< Shifted mode CH4CH5 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH2              (_ADC_SCANCTRL_INPUTMASK_CH2 << 8)     /**< Shifted mode CH2 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH6CH7           (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8)  /**< Shifted mode CH6CH7 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH3              (_ADC_SCANCTRL_INPUTMASK_CH3 << 8)     /**< Shifted mode CH3 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH4              (_ADC_SCANCTRL_INPUTMASK_CH4 << 8)     /**< Shifted mode CH4 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH5              (_ADC_SCANCTRL_INPUTMASK_CH5 << 8)     /**< Shifted mode CH5 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH6              (_ADC_SCANCTRL_INPUTMASK_CH6 << 8)     /**< Shifted mode CH6 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_INPUTMASK_CH7              (_ADC_SCANCTRL_INPUTMASK_CH7 << 8)     /**< Shifted mode CH7 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_SHIFT                 16                                     /**< Shift value for ADC_REF */
+#define _ADC_SCANCTRL_REF_MASK                  0x70000UL                              /**< Bit mask for ADC_REF */
+#define _ADC_SCANCTRL_REF_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_1V25                  0x00000000UL                           /**< Mode 1V25 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_2V5                   0x00000001UL                           /**< Mode 2V5 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_VDD                   0x00000002UL                           /**< Mode VDD for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_5VDIFF                0x00000003UL                           /**< Mode 5VDIFF for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_EXTSINGLE             0x00000004UL                           /**< Mode EXTSINGLE for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_2XEXTDIFF             0x00000005UL                           /**< Mode 2XEXTDIFF for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_2XVDD                 0x00000006UL                           /**< Mode 2XVDD for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_DEFAULT                (_ADC_SCANCTRL_REF_DEFAULT << 16)      /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_1V25                   (_ADC_SCANCTRL_REF_1V25 << 16)         /**< Shifted mode 1V25 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_2V5                    (_ADC_SCANCTRL_REF_2V5 << 16)          /**< Shifted mode 2V5 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_VDD                    (_ADC_SCANCTRL_REF_VDD << 16)          /**< Shifted mode VDD for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_5VDIFF                 (_ADC_SCANCTRL_REF_5VDIFF << 16)       /**< Shifted mode 5VDIFF for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_EXTSINGLE              (_ADC_SCANCTRL_REF_EXTSINGLE << 16)    /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_2XEXTDIFF              (_ADC_SCANCTRL_REF_2XEXTDIFF << 16)    /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_2XVDD                  (_ADC_SCANCTRL_REF_2XVDD << 16)        /**< Shifted mode 2XVDD for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_SHIFT                  20                                     /**< Shift value for ADC_AT */
+#define _ADC_SCANCTRL_AT_MASK                   0xF00000UL                             /**< Bit mask for ADC_AT */
+#define _ADC_SCANCTRL_AT_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_1CYCLE                 0x00000000UL                           /**< Mode 1CYCLE for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_2CYCLES                0x00000001UL                           /**< Mode 2CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_4CYCLES                0x00000002UL                           /**< Mode 4CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_8CYCLES                0x00000003UL                           /**< Mode 8CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_16CYCLES               0x00000004UL                           /**< Mode 16CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_32CYCLES               0x00000005UL                           /**< Mode 32CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_64CYCLES               0x00000006UL                           /**< Mode 64CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_128CYCLES              0x00000007UL                           /**< Mode 128CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_256CYCLES              0x00000008UL                           /**< Mode 256CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_DEFAULT                 (_ADC_SCANCTRL_AT_DEFAULT << 20)       /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_1CYCLE                  (_ADC_SCANCTRL_AT_1CYCLE << 20)        /**< Shifted mode 1CYCLE for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_2CYCLES                 (_ADC_SCANCTRL_AT_2CYCLES << 20)       /**< Shifted mode 2CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_4CYCLES                 (_ADC_SCANCTRL_AT_4CYCLES << 20)       /**< Shifted mode 4CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_8CYCLES                 (_ADC_SCANCTRL_AT_8CYCLES << 20)       /**< Shifted mode 8CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_16CYCLES                (_ADC_SCANCTRL_AT_16CYCLES << 20)      /**< Shifted mode 16CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_32CYCLES                (_ADC_SCANCTRL_AT_32CYCLES << 20)      /**< Shifted mode 32CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_64CYCLES                (_ADC_SCANCTRL_AT_64CYCLES << 20)      /**< Shifted mode 64CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_128CYCLES               (_ADC_SCANCTRL_AT_128CYCLES << 20)     /**< Shifted mode 128CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_256CYCLES               (_ADC_SCANCTRL_AT_256CYCLES << 20)     /**< Shifted mode 256CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSEN                      (0x1UL << 24)                          /**< Scan Sequence PRS Trigger Enable */
+#define _ADC_SCANCTRL_PRSEN_SHIFT               24                                     /**< Shift value for ADC_PRSEN */
+#define _ADC_SCANCTRL_PRSEN_MASK                0x1000000UL                            /**< Bit mask for ADC_PRSEN */
+#define _ADC_SCANCTRL_PRSEN_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSEN_DEFAULT              (_ADC_SCANCTRL_PRSEN_DEFAULT << 24)    /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_PRSSEL_SHIFT              28                                     /**< Shift value for ADC_PRSSEL */
+#define _ADC_SCANCTRL_PRSSEL_MASK               0x70000000UL                           /**< Bit mask for ADC_PRSSEL */
+#define _ADC_SCANCTRL_PRSSEL_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_PRSSEL_PRSCH0             0x00000000UL                           /**< Mode PRSCH0 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_PRSSEL_PRSCH1             0x00000001UL                           /**< Mode PRSCH1 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_PRSSEL_PRSCH2             0x00000002UL                           /**< Mode PRSCH2 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_PRSSEL_PRSCH3             0x00000003UL                           /**< Mode PRSCH3 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_PRSSEL_PRSCH4             0x00000004UL                           /**< Mode PRSCH4 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_PRSSEL_PRSCH5             0x00000005UL                           /**< Mode PRSCH5 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSSEL_DEFAULT             (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28)   /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSSEL_PRSCH0              (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28)    /**< Shifted mode PRSCH0 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSSEL_PRSCH1              (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28)    /**< Shifted mode PRSCH1 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSSEL_PRSCH2              (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28)    /**< Shifted mode PRSCH2 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSSEL_PRSCH3              (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28)    /**< Shifted mode PRSCH3 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSSEL_PRSCH4              (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28)    /**< Shifted mode PRSCH4 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSSEL_PRSCH5              (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28)    /**< Shifted mode PRSCH5 for ADC_SCANCTRL */
+
+/* Bit fields for ADC IEN */
+#define _ADC_IEN_RESETVALUE                     0x00000000UL                     /**< Default value for ADC_IEN */
+#define _ADC_IEN_MASK                           0x00000303UL                     /**< Mask for ADC_IEN */
+#define ADC_IEN_SINGLE                          (0x1UL << 0)                     /**< Single Conversion Complete Interrupt Enable */
+#define _ADC_IEN_SINGLE_SHIFT                   0                                /**< Shift value for ADC_SINGLE */
+#define _ADC_IEN_SINGLE_MASK                    0x1UL                            /**< Bit mask for ADC_SINGLE */
+#define _ADC_IEN_SINGLE_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLE_DEFAULT                  (_ADC_IEN_SINGLE_DEFAULT << 0)   /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCAN                            (0x1UL << 1)                     /**< Scan Conversion Complete Interrupt Enable */
+#define _ADC_IEN_SCAN_SHIFT                     1                                /**< Shift value for ADC_SCAN */
+#define _ADC_IEN_SCAN_MASK                      0x2UL                            /**< Bit mask for ADC_SCAN */
+#define _ADC_IEN_SCAN_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCAN_DEFAULT                    (_ADC_IEN_SCAN_DEFAULT << 1)     /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLEOF                        (0x1UL << 8)                     /**< Single Result Overflow Interrupt Enable */
+#define _ADC_IEN_SINGLEOF_SHIFT                 8                                /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IEN_SINGLEOF_MASK                  0x100UL                          /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IEN_SINGLEOF_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLEOF_DEFAULT                (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANOF                          (0x1UL << 9)                     /**< Scan Result Overflow Interrupt Enable */
+#define _ADC_IEN_SCANOF_SHIFT                   9                                /**< Shift value for ADC_SCANOF */
+#define _ADC_IEN_SCANOF_MASK                    0x200UL                          /**< Bit mask for ADC_SCANOF */
+#define _ADC_IEN_SCANOF_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANOF_DEFAULT                  (_ADC_IEN_SCANOF_DEFAULT << 9)   /**< Shifted mode DEFAULT for ADC_IEN */
+
+/* Bit fields for ADC IF */
+#define _ADC_IF_RESETVALUE                      0x00000000UL                    /**< Default value for ADC_IF */
+#define _ADC_IF_MASK                            0x00000303UL                    /**< Mask for ADC_IF */
+#define ADC_IF_SINGLE                           (0x1UL << 0)                    /**< Single Conversion Complete Interrupt Flag */
+#define _ADC_IF_SINGLE_SHIFT                    0                               /**< Shift value for ADC_SINGLE */
+#define _ADC_IF_SINGLE_MASK                     0x1UL                           /**< Bit mask for ADC_SINGLE */
+#define _ADC_IF_SINGLE_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLE_DEFAULT                   (_ADC_IF_SINGLE_DEFAULT << 0)   /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SCAN                             (0x1UL << 1)                    /**< Scan Conversion Complete Interrupt Flag */
+#define _ADC_IF_SCAN_SHIFT                      1                               /**< Shift value for ADC_SCAN */
+#define _ADC_IF_SCAN_MASK                       0x2UL                           /**< Bit mask for ADC_SCAN */
+#define _ADC_IF_SCAN_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SCAN_DEFAULT                     (_ADC_IF_SCAN_DEFAULT << 1)     /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLEOF                         (0x1UL << 8)                    /**< Single Result Overflow Interrupt Flag */
+#define _ADC_IF_SINGLEOF_SHIFT                  8                               /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IF_SINGLEOF_MASK                   0x100UL                         /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IF_SINGLEOF_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLEOF_DEFAULT                 (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANOF                           (0x1UL << 9)                    /**< Scan Result Overflow Interrupt Flag */
+#define _ADC_IF_SCANOF_SHIFT                    9                               /**< Shift value for ADC_SCANOF */
+#define _ADC_IF_SCANOF_MASK                     0x200UL                         /**< Bit mask for ADC_SCANOF */
+#define _ADC_IF_SCANOF_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANOF_DEFAULT                   (_ADC_IF_SCANOF_DEFAULT << 9)   /**< Shifted mode DEFAULT for ADC_IF */
+
+/* Bit fields for ADC IFS */
+#define _ADC_IFS_RESETVALUE                     0x00000000UL                     /**< Default value for ADC_IFS */
+#define _ADC_IFS_MASK                           0x00000303UL                     /**< Mask for ADC_IFS */
+#define ADC_IFS_SINGLE                          (0x1UL << 0)                     /**< Single Conversion Complete Interrupt Flag Set */
+#define _ADC_IFS_SINGLE_SHIFT                   0                                /**< Shift value for ADC_SINGLE */
+#define _ADC_IFS_SINGLE_MASK                    0x1UL                            /**< Bit mask for ADC_SINGLE */
+#define _ADC_IFS_SINGLE_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLE_DEFAULT                  (_ADC_IFS_SINGLE_DEFAULT << 0)   /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCAN                            (0x1UL << 1)                     /**< Scan Conversion Complete Interrupt Flag Set */
+#define _ADC_IFS_SCAN_SHIFT                     1                                /**< Shift value for ADC_SCAN */
+#define _ADC_IFS_SCAN_MASK                      0x2UL                            /**< Bit mask for ADC_SCAN */
+#define _ADC_IFS_SCAN_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCAN_DEFAULT                    (_ADC_IFS_SCAN_DEFAULT << 1)     /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLEOF                        (0x1UL << 8)                     /**< Single Result Overflow Interrupt Flag Set */
+#define _ADC_IFS_SINGLEOF_SHIFT                 8                                /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IFS_SINGLEOF_MASK                  0x100UL                          /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IFS_SINGLEOF_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLEOF_DEFAULT                (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANOF                          (0x1UL << 9)                     /**< Scan Result Overflow Interrupt Flag Set */
+#define _ADC_IFS_SCANOF_SHIFT                   9                                /**< Shift value for ADC_SCANOF */
+#define _ADC_IFS_SCANOF_MASK                    0x200UL                          /**< Bit mask for ADC_SCANOF */
+#define _ADC_IFS_SCANOF_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANOF_DEFAULT                  (_ADC_IFS_SCANOF_DEFAULT << 9)   /**< Shifted mode DEFAULT for ADC_IFS */
+
+/* Bit fields for ADC IFC */
+#define _ADC_IFC_RESETVALUE                     0x00000000UL                     /**< Default value for ADC_IFC */
+#define _ADC_IFC_MASK                           0x00000303UL                     /**< Mask for ADC_IFC */
+#define ADC_IFC_SINGLE                          (0x1UL << 0)                     /**< Single Conversion Complete Interrupt Flag Clear */
+#define _ADC_IFC_SINGLE_SHIFT                   0                                /**< Shift value for ADC_SINGLE */
+#define _ADC_IFC_SINGLE_MASK                    0x1UL                            /**< Bit mask for ADC_SINGLE */
+#define _ADC_IFC_SINGLE_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLE_DEFAULT                  (_ADC_IFC_SINGLE_DEFAULT << 0)   /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCAN                            (0x1UL << 1)                     /**< Scan Conversion Complete Interrupt Flag Clear */
+#define _ADC_IFC_SCAN_SHIFT                     1                                /**< Shift value for ADC_SCAN */
+#define _ADC_IFC_SCAN_MASK                      0x2UL                            /**< Bit mask for ADC_SCAN */
+#define _ADC_IFC_SCAN_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCAN_DEFAULT                    (_ADC_IFC_SCAN_DEFAULT << 1)     /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLEOF                        (0x1UL << 8)                     /**< Single Result Overflow Interrupt Flag Clear */
+#define _ADC_IFC_SINGLEOF_SHIFT                 8                                /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IFC_SINGLEOF_MASK                  0x100UL                          /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IFC_SINGLEOF_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLEOF_DEFAULT                (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANOF                          (0x1UL << 9)                     /**< Scan Result Overflow Interrupt Flag Clear */
+#define _ADC_IFC_SCANOF_SHIFT                   9                                /**< Shift value for ADC_SCANOF */
+#define _ADC_IFC_SCANOF_MASK                    0x200UL                          /**< Bit mask for ADC_SCANOF */
+#define _ADC_IFC_SCANOF_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANOF_DEFAULT                  (_ADC_IFC_SCANOF_DEFAULT << 9)   /**< Shifted mode DEFAULT for ADC_IFC */
+
+/* Bit fields for ADC SINGLEDATA */
+#define _ADC_SINGLEDATA_RESETVALUE              0x00000000UL                        /**< Default value for ADC_SINGLEDATA */
+#define _ADC_SINGLEDATA_MASK                    0xFFFFFFFFUL                        /**< Mask for ADC_SINGLEDATA */
+#define _ADC_SINGLEDATA_DATA_SHIFT              0                                   /**< Shift value for ADC_DATA */
+#define _ADC_SINGLEDATA_DATA_MASK               0xFFFFFFFFUL                        /**< Bit mask for ADC_DATA */
+#define _ADC_SINGLEDATA_DATA_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for ADC_SINGLEDATA */
+#define ADC_SINGLEDATA_DATA_DEFAULT             (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */
+
+/* Bit fields for ADC SCANDATA */
+#define _ADC_SCANDATA_RESETVALUE                0x00000000UL                      /**< Default value for ADC_SCANDATA */
+#define _ADC_SCANDATA_MASK                      0xFFFFFFFFUL                      /**< Mask for ADC_SCANDATA */
+#define _ADC_SCANDATA_DATA_SHIFT                0                                 /**< Shift value for ADC_DATA */
+#define _ADC_SCANDATA_DATA_MASK                 0xFFFFFFFFUL                      /**< Bit mask for ADC_DATA */
+#define _ADC_SCANDATA_DATA_DEFAULT              0x00000000UL                      /**< Mode DEFAULT for ADC_SCANDATA */
+#define ADC_SCANDATA_DATA_DEFAULT               (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */
+
+/* Bit fields for ADC SINGLEDATAP */
+#define _ADC_SINGLEDATAP_RESETVALUE             0x00000000UL                          /**< Default value for ADC_SINGLEDATAP */
+#define _ADC_SINGLEDATAP_MASK                   0xFFFFFFFFUL                          /**< Mask for ADC_SINGLEDATAP */
+#define _ADC_SINGLEDATAP_DATAP_SHIFT            0                                     /**< Shift value for ADC_DATAP */
+#define _ADC_SINGLEDATAP_DATAP_MASK             0xFFFFFFFFUL                          /**< Bit mask for ADC_DATAP */
+#define _ADC_SINGLEDATAP_DATAP_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for ADC_SINGLEDATAP */
+#define ADC_SINGLEDATAP_DATAP_DEFAULT           (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */
+
+/* Bit fields for ADC SCANDATAP */
+#define _ADC_SCANDATAP_RESETVALUE               0x00000000UL                        /**< Default value for ADC_SCANDATAP */
+#define _ADC_SCANDATAP_MASK                     0xFFFFFFFFUL                        /**< Mask for ADC_SCANDATAP */
+#define _ADC_SCANDATAP_DATAP_SHIFT              0                                   /**< Shift value for ADC_DATAP */
+#define _ADC_SCANDATAP_DATAP_MASK               0xFFFFFFFFUL                        /**< Bit mask for ADC_DATAP */
+#define _ADC_SCANDATAP_DATAP_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for ADC_SCANDATAP */
+#define ADC_SCANDATAP_DATAP_DEFAULT             (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */
+
+/* Bit fields for ADC CAL */
+#define _ADC_CAL_RESETVALUE                     0x3F003F00UL                         /**< Default value for ADC_CAL */
+#define _ADC_CAL_MASK                           0x7F7F7F7FUL                         /**< Mask for ADC_CAL */
+#define _ADC_CAL_SINGLEOFFSET_SHIFT             0                                    /**< Shift value for ADC_SINGLEOFFSET */
+#define _ADC_CAL_SINGLEOFFSET_MASK              0x7FUL                               /**< Bit mask for ADC_SINGLEOFFSET */
+#define _ADC_CAL_SINGLEOFFSET_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SINGLEOFFSET_DEFAULT            (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SINGLEGAIN_SHIFT               8                                    /**< Shift value for ADC_SINGLEGAIN */
+#define _ADC_CAL_SINGLEGAIN_MASK                0x7F00UL                             /**< Bit mask for ADC_SINGLEGAIN */
+#define _ADC_CAL_SINGLEGAIN_DEFAULT             0x0000003FUL                         /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SINGLEGAIN_DEFAULT              (_ADC_CAL_SINGLEGAIN_DEFAULT << 8)   /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SCANOFFSET_SHIFT               16                                   /**< Shift value for ADC_SCANOFFSET */
+#define _ADC_CAL_SCANOFFSET_MASK                0x7F0000UL                           /**< Bit mask for ADC_SCANOFFSET */
+#define _ADC_CAL_SCANOFFSET_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SCANOFFSET_DEFAULT              (_ADC_CAL_SCANOFFSET_DEFAULT << 16)  /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SCANGAIN_SHIFT                 24                                   /**< Shift value for ADC_SCANGAIN */
+#define _ADC_CAL_SCANGAIN_MASK                  0x7F000000UL                         /**< Bit mask for ADC_SCANGAIN */
+#define _ADC_CAL_SCANGAIN_DEFAULT               0x0000003FUL                         /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SCANGAIN_DEFAULT                (_ADC_CAL_SCANGAIN_DEFAULT << 24)    /**< Shifted mode DEFAULT for ADC_CAL */
+
+/* Bit fields for ADC BIASPROG */
+#define _ADC_BIASPROG_RESETVALUE                0x00000747UL                          /**< Default value for ADC_BIASPROG */
+#define _ADC_BIASPROG_MASK                      0x00000F4FUL                          /**< Mask for ADC_BIASPROG */
+#define _ADC_BIASPROG_BIASPROG_SHIFT            0                                     /**< Shift value for ADC_BIASPROG */
+#define _ADC_BIASPROG_BIASPROG_MASK             0xFUL                                 /**< Bit mask for ADC_BIASPROG */
+#define _ADC_BIASPROG_BIASPROG_DEFAULT          0x00000007UL                          /**< Mode DEFAULT for ADC_BIASPROG */
+#define ADC_BIASPROG_BIASPROG_DEFAULT           (_ADC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */
+#define ADC_BIASPROG_HALFBIAS                   (0x1UL << 6)                          /**< Half Bias Current */
+#define _ADC_BIASPROG_HALFBIAS_SHIFT            6                                     /**< Shift value for ADC_HALFBIAS */
+#define _ADC_BIASPROG_HALFBIAS_MASK             0x40UL                                /**< Bit mask for ADC_HALFBIAS */
+#define _ADC_BIASPROG_HALFBIAS_DEFAULT          0x00000001UL                          /**< Mode DEFAULT for ADC_BIASPROG */
+#define ADC_BIASPROG_HALFBIAS_DEFAULT           (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_BIASPROG */
+#define _ADC_BIASPROG_COMPBIAS_SHIFT            8                                     /**< Shift value for ADC_COMPBIAS */
+#define _ADC_BIASPROG_COMPBIAS_MASK             0xF00UL                               /**< Bit mask for ADC_COMPBIAS */
+#define _ADC_BIASPROG_COMPBIAS_DEFAULT          0x00000007UL                          /**< Mode DEFAULT for ADC_BIASPROG */
+#define ADC_BIASPROG_COMPBIAS_DEFAULT           (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
+
+/** @} End of group EFM32HG_ADC */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_aes.h

@@ -0,0 +1,209 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_AES register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_AES
+ * @{
+ * @brief EFM32HG_AES Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;          /**< Control Register  */
+  __IOM uint32_t CMD;           /**< Command Register  */
+  __IM uint32_t  STATUS;        /**< Status Register  */
+  __IOM uint32_t IEN;           /**< Interrupt Enable Register  */
+  __IM uint32_t  IF;            /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;           /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;           /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t DATA;          /**< DATA Register  */
+  __IOM uint32_t XORDATA;       /**< XORDATA Register  */
+  uint32_t       RESERVED0[3U]; /**< Reserved for future use **/
+  __IOM uint32_t KEYLA;         /**< KEY Low Register  */
+  __IOM uint32_t KEYLB;         /**< KEY Low Register  */
+  __IOM uint32_t KEYLC;         /**< KEY Low Register  */
+  __IOM uint32_t KEYLD;         /**< KEY Low Register  */
+} AES_TypeDef;                  /**< AES Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_AES_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for AES CTRL */
+#define _AES_CTRL_RESETVALUE            0x00000000UL                       /**< Default value for AES_CTRL */
+#define _AES_CTRL_MASK                  0x00000071UL                       /**< Mask for AES_CTRL */
+#define AES_CTRL_DECRYPT                (0x1UL << 0)                       /**< Decryption/Encryption Mode */
+#define _AES_CTRL_DECRYPT_SHIFT         0                                  /**< Shift value for AES_DECRYPT */
+#define _AES_CTRL_DECRYPT_MASK          0x1UL                              /**< Bit mask for AES_DECRYPT */
+#define _AES_CTRL_DECRYPT_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for AES_CTRL */
+#define AES_CTRL_DECRYPT_DEFAULT        (_AES_CTRL_DECRYPT_DEFAULT << 0)   /**< Shifted mode DEFAULT for AES_CTRL */
+#define AES_CTRL_DATASTART              (0x1UL << 4)                       /**< AES_DATA Write Start */
+#define _AES_CTRL_DATASTART_SHIFT       4                                  /**< Shift value for AES_DATASTART */
+#define _AES_CTRL_DATASTART_MASK        0x10UL                             /**< Bit mask for AES_DATASTART */
+#define _AES_CTRL_DATASTART_DEFAULT     0x00000000UL                       /**< Mode DEFAULT for AES_CTRL */
+#define AES_CTRL_DATASTART_DEFAULT      (_AES_CTRL_DATASTART_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */
+#define AES_CTRL_XORSTART               (0x1UL << 5)                       /**< AES_XORDATA Write Start */
+#define _AES_CTRL_XORSTART_SHIFT        5                                  /**< Shift value for AES_XORSTART */
+#define _AES_CTRL_XORSTART_MASK         0x20UL                             /**< Bit mask for AES_XORSTART */
+#define _AES_CTRL_XORSTART_DEFAULT      0x00000000UL                       /**< Mode DEFAULT for AES_CTRL */
+#define AES_CTRL_XORSTART_DEFAULT       (_AES_CTRL_XORSTART_DEFAULT << 5)  /**< Shifted mode DEFAULT for AES_CTRL */
+#define AES_CTRL_BYTEORDER              (0x1UL << 6)                       /**< Configure byte order in data and key registers */
+#define _AES_CTRL_BYTEORDER_SHIFT       6                                  /**< Shift value for AES_BYTEORDER */
+#define _AES_CTRL_BYTEORDER_MASK        0x40UL                             /**< Bit mask for AES_BYTEORDER */
+#define _AES_CTRL_BYTEORDER_DEFAULT     0x00000000UL                       /**< Mode DEFAULT for AES_CTRL */
+#define AES_CTRL_BYTEORDER_DEFAULT      (_AES_CTRL_BYTEORDER_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_CTRL */
+
+/* Bit fields for AES CMD */
+#define _AES_CMD_RESETVALUE             0x00000000UL                  /**< Default value for AES_CMD */
+#define _AES_CMD_MASK                   0x00000003UL                  /**< Mask for AES_CMD */
+#define AES_CMD_START                   (0x1UL << 0)                  /**< Encryption/Decryption Start */
+#define _AES_CMD_START_SHIFT            0                             /**< Shift value for AES_START */
+#define _AES_CMD_START_MASK             0x1UL                         /**< Bit mask for AES_START */
+#define _AES_CMD_START_DEFAULT          0x00000000UL                  /**< Mode DEFAULT for AES_CMD */
+#define AES_CMD_START_DEFAULT           (_AES_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */
+#define AES_CMD_STOP                    (0x1UL << 1)                  /**< Encryption/Decryption Stop */
+#define _AES_CMD_STOP_SHIFT             1                             /**< Shift value for AES_STOP */
+#define _AES_CMD_STOP_MASK              0x2UL                         /**< Bit mask for AES_STOP */
+#define _AES_CMD_STOP_DEFAULT           0x00000000UL                  /**< Mode DEFAULT for AES_CMD */
+#define AES_CMD_STOP_DEFAULT            (_AES_CMD_STOP_DEFAULT << 1)  /**< Shifted mode DEFAULT for AES_CMD */
+
+/* Bit fields for AES STATUS */
+#define _AES_STATUS_RESETVALUE          0x00000000UL                       /**< Default value for AES_STATUS */
+#define _AES_STATUS_MASK                0x00000001UL                       /**< Mask for AES_STATUS */
+#define AES_STATUS_RUNNING              (0x1UL << 0)                       /**< AES Running */
+#define _AES_STATUS_RUNNING_SHIFT       0                                  /**< Shift value for AES_RUNNING */
+#define _AES_STATUS_RUNNING_MASK        0x1UL                              /**< Bit mask for AES_RUNNING */
+#define _AES_STATUS_RUNNING_DEFAULT     0x00000000UL                       /**< Mode DEFAULT for AES_STATUS */
+#define AES_STATUS_RUNNING_DEFAULT      (_AES_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */
+
+/* Bit fields for AES IEN */
+#define _AES_IEN_RESETVALUE             0x00000000UL                 /**< Default value for AES_IEN */
+#define _AES_IEN_MASK                   0x00000001UL                 /**< Mask for AES_IEN */
+#define AES_IEN_DONE                    (0x1UL << 0)                 /**< Encryption/Decryption Done Interrupt Enable */
+#define _AES_IEN_DONE_SHIFT             0                            /**< Shift value for AES_DONE */
+#define _AES_IEN_DONE_MASK              0x1UL                        /**< Bit mask for AES_DONE */
+#define _AES_IEN_DONE_DEFAULT           0x00000000UL                 /**< Mode DEFAULT for AES_IEN */
+#define AES_IEN_DONE_DEFAULT            (_AES_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */
+
+/* Bit fields for AES IF */
+#define _AES_IF_RESETVALUE              0x00000000UL                /**< Default value for AES_IF */
+#define _AES_IF_MASK                    0x00000001UL                /**< Mask for AES_IF */
+#define AES_IF_DONE                     (0x1UL << 0)                /**< Encryption/Decryption Done Interrupt Flag */
+#define _AES_IF_DONE_SHIFT              0                           /**< Shift value for AES_DONE */
+#define _AES_IF_DONE_MASK               0x1UL                       /**< Bit mask for AES_DONE */
+#define _AES_IF_DONE_DEFAULT            0x00000000UL                /**< Mode DEFAULT for AES_IF */
+#define AES_IF_DONE_DEFAULT             (_AES_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */
+
+/* Bit fields for AES IFS */
+#define _AES_IFS_RESETVALUE             0x00000000UL                 /**< Default value for AES_IFS */
+#define _AES_IFS_MASK                   0x00000001UL                 /**< Mask for AES_IFS */
+#define AES_IFS_DONE                    (0x1UL << 0)                 /**< Encryption/Decryption Done Interrupt Flag Set */
+#define _AES_IFS_DONE_SHIFT             0                            /**< Shift value for AES_DONE */
+#define _AES_IFS_DONE_MASK              0x1UL                        /**< Bit mask for AES_DONE */
+#define _AES_IFS_DONE_DEFAULT           0x00000000UL                 /**< Mode DEFAULT for AES_IFS */
+#define AES_IFS_DONE_DEFAULT            (_AES_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFS */
+
+/* Bit fields for AES IFC */
+#define _AES_IFC_RESETVALUE             0x00000000UL                 /**< Default value for AES_IFC */
+#define _AES_IFC_MASK                   0x00000001UL                 /**< Mask for AES_IFC */
+#define AES_IFC_DONE                    (0x1UL << 0)                 /**< Encryption/Decryption Done Interrupt Flag Clear */
+#define _AES_IFC_DONE_SHIFT             0                            /**< Shift value for AES_DONE */
+#define _AES_IFC_DONE_MASK              0x1UL                        /**< Bit mask for AES_DONE */
+#define _AES_IFC_DONE_DEFAULT           0x00000000UL                 /**< Mode DEFAULT for AES_IFC */
+#define AES_IFC_DONE_DEFAULT            (_AES_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */
+
+/* Bit fields for AES DATA */
+#define _AES_DATA_RESETVALUE            0x00000000UL                  /**< Default value for AES_DATA */
+#define _AES_DATA_MASK                  0xFFFFFFFFUL                  /**< Mask for AES_DATA */
+#define _AES_DATA_DATA_SHIFT            0                             /**< Shift value for AES_DATA */
+#define _AES_DATA_DATA_MASK             0xFFFFFFFFUL                  /**< Bit mask for AES_DATA */
+#define _AES_DATA_DATA_DEFAULT          0x00000000UL                  /**< Mode DEFAULT for AES_DATA */
+#define AES_DATA_DATA_DEFAULT           (_AES_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_DATA */
+
+/* Bit fields for AES XORDATA */
+#define _AES_XORDATA_RESETVALUE         0x00000000UL                        /**< Default value for AES_XORDATA */
+#define _AES_XORDATA_MASK               0xFFFFFFFFUL                        /**< Mask for AES_XORDATA */
+#define _AES_XORDATA_XORDATA_SHIFT      0                                   /**< Shift value for AES_XORDATA */
+#define _AES_XORDATA_XORDATA_MASK       0xFFFFFFFFUL                        /**< Bit mask for AES_XORDATA */
+#define _AES_XORDATA_XORDATA_DEFAULT    0x00000000UL                        /**< Mode DEFAULT for AES_XORDATA */
+#define AES_XORDATA_XORDATA_DEFAULT     (_AES_XORDATA_XORDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_XORDATA */
+
+/* Bit fields for AES KEYLA */
+#define _AES_KEYLA_RESETVALUE           0x00000000UL                    /**< Default value for AES_KEYLA */
+#define _AES_KEYLA_MASK                 0xFFFFFFFFUL                    /**< Mask for AES_KEYLA */
+#define _AES_KEYLA_KEYLA_SHIFT          0                               /**< Shift value for AES_KEYLA */
+#define _AES_KEYLA_KEYLA_MASK           0xFFFFFFFFUL                    /**< Bit mask for AES_KEYLA */
+#define _AES_KEYLA_KEYLA_DEFAULT        0x00000000UL                    /**< Mode DEFAULT for AES_KEYLA */
+#define AES_KEYLA_KEYLA_DEFAULT         (_AES_KEYLA_KEYLA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLA */
+
+/* Bit fields for AES KEYLB */
+#define _AES_KEYLB_RESETVALUE           0x00000000UL                    /**< Default value for AES_KEYLB */
+#define _AES_KEYLB_MASK                 0xFFFFFFFFUL                    /**< Mask for AES_KEYLB */
+#define _AES_KEYLB_KEYLB_SHIFT          0                               /**< Shift value for AES_KEYLB */
+#define _AES_KEYLB_KEYLB_MASK           0xFFFFFFFFUL                    /**< Bit mask for AES_KEYLB */
+#define _AES_KEYLB_KEYLB_DEFAULT        0x00000000UL                    /**< Mode DEFAULT for AES_KEYLB */
+#define AES_KEYLB_KEYLB_DEFAULT         (_AES_KEYLB_KEYLB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLB */
+
+/* Bit fields for AES KEYLC */
+#define _AES_KEYLC_RESETVALUE           0x00000000UL                    /**< Default value for AES_KEYLC */
+#define _AES_KEYLC_MASK                 0xFFFFFFFFUL                    /**< Mask for AES_KEYLC */
+#define _AES_KEYLC_KEYLC_SHIFT          0                               /**< Shift value for AES_KEYLC */
+#define _AES_KEYLC_KEYLC_MASK           0xFFFFFFFFUL                    /**< Bit mask for AES_KEYLC */
+#define _AES_KEYLC_KEYLC_DEFAULT        0x00000000UL                    /**< Mode DEFAULT for AES_KEYLC */
+#define AES_KEYLC_KEYLC_DEFAULT         (_AES_KEYLC_KEYLC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLC */
+
+/* Bit fields for AES KEYLD */
+#define _AES_KEYLD_RESETVALUE           0x00000000UL                    /**< Default value for AES_KEYLD */
+#define _AES_KEYLD_MASK                 0xFFFFFFFFUL                    /**< Mask for AES_KEYLD */
+#define _AES_KEYLD_KEYLD_SHIFT          0                               /**< Shift value for AES_KEYLD */
+#define _AES_KEYLD_KEYLD_MASK           0xFFFFFFFFUL                    /**< Bit mask for AES_KEYLD */
+#define _AES_KEYLD_KEYLD_DEFAULT        0x00000000UL                    /**< Mode DEFAULT for AES_KEYLD */
+#define AES_KEYLD_KEYLD_DEFAULT         (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
+
+/** @} End of group EFM32HG_AES */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_af_pins.h

@@ -0,0 +1,99 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_AF_PINS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_AF_Pins
+ * @{
+ ******************************************************************************/
+
+#define AF_USB_DMPU_PIN(i)        ((i) == 0 ? 0 :  -1)                                                                                                 /**< Pin number for AF_USB_DMPU location number i */
+#define AF_CMU_CLK0_PIN(i)        ((i) == 0 ? 2 : (i) == 1 ? -1 : (i) == 2 ? 7 : (i) == 3 ? 2 :  -1)                                                   /**< Pin number for AF_CMU_CLK0 location number i */
+#define AF_CMU_CLK1_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? -1 : (i) == 2 ? 12 : (i) == 3 ? 11 :  -1)                                                 /**< Pin number for AF_CMU_CLK1 location number i */
+#define AF_TIMER0_CC0_PIN(i)      ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 :  -1)     /**< Pin number for AF_TIMER0_CC0 location number i */
+#define AF_TIMER0_CC1_PIN(i)      ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 0 :  -1)     /**< Pin number for AF_TIMER0_CC1 location number i */
+#define AF_TIMER0_CC2_PIN(i)      ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 2 :  -1)     /**< Pin number for AF_TIMER0_CC2 location number i */
+#define AF_TIMER0_CDTI0_PIN(i)    ((i) == 0 ? -1 : (i) == 1 ? 13 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 13 :  -1)  /**< Pin number for AF_TIMER0_CDTI0 location number i */
+#define AF_TIMER0_CDTI1_PIN(i)    ((i) == 0 ? -1 : (i) == 1 ? 14 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 3 : (i) == 5 ? 4 : (i) == 6 ? 14 :  -1)  /**< Pin number for AF_TIMER0_CDTI1 location number i */
+#define AF_TIMER0_CDTI2_PIN(i)    ((i) == 0 ? -1 : (i) == 1 ? 15 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 15 :  -1)  /**< Pin number for AF_TIMER0_CDTI2 location number i */
+#define AF_TIMER1_CC0_PIN(i)      ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? -1 : (i) == 3 ? 7 : (i) == 4 ? 6 :  -1)                                  /**< Pin number for AF_TIMER1_CC0 location number i */
+#define AF_TIMER1_CC1_PIN(i)      ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? -1 : (i) == 3 ? 8 : (i) == 4 ? 7 :  -1)                                  /**< Pin number for AF_TIMER1_CC1 location number i */
+#define AF_TIMER1_CC2_PIN(i)      ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? -1 : (i) == 3 ? 11 : (i) == 4 ? 13 :  -1)                                /**< Pin number for AF_TIMER1_CC2 location number i */
+#define AF_TIMER1_CDTI0_PIN(i)    (-1)                                                                                                                 /**< Pin number for AF_TIMER1_CDTI0 location number i */
+#define AF_TIMER1_CDTI1_PIN(i)    (-1)                                                                                                                 /**< Pin number for AF_TIMER1_CDTI1 location number i */
+#define AF_TIMER1_CDTI2_PIN(i)    (-1)                                                                                                                 /**< Pin number for AF_TIMER1_CDTI2 location number i */
+#define AF_TIMER2_CC0_PIN(i)      ((i) == 0 ? 8 : (i) == 1 ? -1 : (i) == 2 ? 8 : (i) == 3 ? 2 :  -1)                                                   /**< Pin number for AF_TIMER2_CC0 location number i */
+#define AF_TIMER2_CC1_PIN(i)      ((i) == 0 ? 9 : (i) == 1 ? -1 : (i) == 2 ? 9 : (i) == 3 ? 12 :  -1)                                                  /**< Pin number for AF_TIMER2_CC1 location number i */
+#define AF_TIMER2_CC2_PIN(i)      ((i) == 0 ? 10 : (i) == 1 ? -1 : (i) == 2 ? 10 : (i) == 3 ? 13 :  -1)                                                /**< Pin number for AF_TIMER2_CC2 location number i */
+#define AF_TIMER2_CDTI0_PIN(i)    (-1)                                                                                                                 /**< Pin number for AF_TIMER2_CDTI0 location number i */
+#define AF_TIMER2_CDTI1_PIN(i)    (-1)                                                                                                                 /**< Pin number for AF_TIMER2_CDTI1 location number i */
+#define AF_TIMER2_CDTI2_PIN(i)    (-1)                                                                                                                 /**< Pin number for AF_TIMER2_CDTI2 location number i */
+#define AF_ACMP0_OUT_PIN(i)       ((i) == 0 ? 13 : (i) == 1 ? -1 : (i) == 2 ? 6 : (i) == 3 ? 11 :  -1)                                                 /**< Pin number for AF_ACMP0_OUT location number i */
+#define AF_USART0_TX_PIN(i)       ((i) == 0 ? 10 : (i) == 1 ? -1 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 0 :  -1)   /**< Pin number for AF_USART0_TX location number i */
+#define AF_USART0_RX_PIN(i)       ((i) == 0 ? 11 : (i) == 1 ? -1 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 :  -1)   /**< Pin number for AF_USART0_RX location number i */
+#define AF_USART0_CLK_PIN(i)      ((i) == 0 ? 12 : (i) == 1 ? -1 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 13 : (i) == 6 ? 12 :  -1) /**< Pin number for AF_USART0_CLK location number i */
+#define AF_USART0_CS_PIN(i)       ((i) == 0 ? 13 : (i) == 1 ? -1 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 14 : (i) == 6 ? 13 :  -1) /**< Pin number for AF_USART0_CS location number i */
+#define AF_USART1_TX_PIN(i)       ((i) == 0 ? 0 : (i) == 1 ? -1 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 1 :  -1)                     /**< Pin number for AF_USART1_TX location number i */
+#define AF_USART1_RX_PIN(i)       ((i) == 0 ? 1 : (i) == 1 ? -1 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 2 :  -1)                     /**< Pin number for AF_USART1_RX location number i */
+#define AF_USART1_CLK_PIN(i)      ((i) == 0 ? 7 : (i) == 1 ? -1 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 11 : (i) == 5 ? 3 :  -1)                   /**< Pin number for AF_USART1_CLK location number i */
+#define AF_USART1_CS_PIN(i)       ((i) == 0 ? 8 : (i) == 1 ? -1 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 0 :  -1)                   /**< Pin number for AF_USART1_CS location number i */
+#define AF_PRS_CH0_PIN(i)         ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 :  -1)                                                   /**< Pin number for AF_PRS_CH0 location number i */
+#define AF_PRS_CH1_PIN(i)         ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 :  -1)                                                  /**< Pin number for AF_PRS_CH1 location number i */
+#define AF_PRS_CH2_PIN(i)         ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 :  -1)                                                  /**< Pin number for AF_PRS_CH2 location number i */
+#define AF_PRS_CH3_PIN(i)         ((i) == 0 ? 1 : (i) == 1 ? -1 : (i) == 2 ? 11 : (i) == 3 ? 0 :  -1)                                                  /**< Pin number for AF_PRS_CH3 location number i */
+#define AF_LEUART0_TX_PIN(i)      ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? -1 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 :  -1)                   /**< Pin number for AF_LEUART0_TX location number i */
+#define AF_LEUART0_RX_PIN(i)      ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? -1 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 :  -1)                   /**< Pin number for AF_LEUART0_RX location number i */
+#define AF_PCNT0_S0IN_PIN(i)      ((i) == 0 ? 13 : (i) == 1 ? -1 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 :  -1)                                   /**< Pin number for AF_PCNT0_S0IN location number i */
+#define AF_PCNT0_S1IN_PIN(i)      ((i) == 0 ? 14 : (i) == 1 ? -1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 11 :  -1)                                  /**< Pin number for AF_PCNT0_S1IN location number i */
+#define AF_I2C0_SDA_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 :  -1)    /**< Pin number for AF_I2C0_SDA location number i */
+#define AF_I2C0_SCL_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 :  -1)    /**< Pin number for AF_I2C0_SCL location number i */
+#define AF_DBG_SWDIO_PIN(i)       ((i) == 0 ? 1 :  -1)                                                                                                 /**< Pin number for AF_DBG_SWDIO location number i */
+#define AF_DBG_SWCLK_PIN(i)       ((i) == 0 ? 0 :  -1)                                                                                                 /**< Pin number for AF_DBG_SWCLK location number i */
+
+/** @} End of group EFM32HG_AF_Pins */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_af_ports.h

@@ -0,0 +1,99 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_AF_PORTS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_AF_Ports
+ * @{
+ ******************************************************************************/
+
+#define AF_USB_DMPU_PORT(i)        ((i) == 0 ? 0 :  -1)                                                                                              /**< Port number for AF_USB_DMPU location number i */
+#define AF_CMU_CLK0_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? -1 : (i) == 2 ? 3 : (i) == 3 ? 5 :  -1)                                                /**< Port number for AF_CMU_CLK0 location number i */
+#define AF_CMU_CLK1_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? -1 : (i) == 2 ? 4 : (i) == 3 ? 1 :  -1)                                                /**< Port number for AF_CMU_CLK1 location number i */
+#define AF_TIMER0_CC0_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 0 :  -1)  /**< Port number for AF_TIMER0_CC0 location number i */
+#define AF_TIMER0_CC1_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 :  -1)  /**< Port number for AF_TIMER0_CC1 location number i */
+#define AF_TIMER0_CC2_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 :  -1)  /**< Port number for AF_TIMER0_CC2 location number i */
+#define AF_TIMER0_CDTI0_PORT(i)    ((i) == 0 ? -1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 2 :  -1) /**< Port number for AF_TIMER0_CDTI0 location number i */
+#define AF_TIMER0_CDTI1_PORT(i)    ((i) == 0 ? -1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 2 :  -1) /**< Port number for AF_TIMER0_CDTI1 location number i */
+#define AF_TIMER0_CDTI2_PORT(i)    ((i) == 0 ? -1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 2 :  -1) /**< Port number for AF_TIMER0_CDTI2 location number i */
+#define AF_TIMER1_CC0_PORT(i)      ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                 /**< Port number for AF_TIMER1_CC0 location number i */
+#define AF_TIMER1_CC1_PORT(i)      ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                 /**< Port number for AF_TIMER1_CC1 location number i */
+#define AF_TIMER1_CC2_PORT(i)      ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 1 : (i) == 4 ? 2 :  -1)                                 /**< Port number for AF_TIMER1_CC2 location number i */
+#define AF_TIMER1_CDTI0_PORT(i)    (-1)                                                                                                              /**< Port number for AF_TIMER1_CDTI0 location number i */
+#define AF_TIMER1_CDTI1_PORT(i)    (-1)                                                                                                              /**< Port number for AF_TIMER1_CDTI1 location number i */
+#define AF_TIMER1_CDTI2_PORT(i)    (-1)                                                                                                              /**< Port number for AF_TIMER1_CDTI2 location number i */
+#define AF_TIMER2_CC0_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? -1 : (i) == 2 ? 2 : (i) == 3 ? 5 :  -1)                                                /**< Port number for AF_TIMER2_CC0 location number i */
+#define AF_TIMER2_CC1_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? -1 : (i) == 2 ? 2 : (i) == 3 ? 4 :  -1)                                                /**< Port number for AF_TIMER2_CC1 location number i */
+#define AF_TIMER2_CC2_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? -1 : (i) == 2 ? 2 : (i) == 3 ? 4 :  -1)                                                /**< Port number for AF_TIMER2_CC2 location number i */
+#define AF_TIMER2_CDTI0_PORT(i)    (-1)                                                                                                              /**< Port number for AF_TIMER2_CDTI0 location number i */
+#define AF_TIMER2_CDTI1_PORT(i)    (-1)                                                                                                              /**< Port number for AF_TIMER2_CDTI1 location number i */
+#define AF_TIMER2_CDTI2_PORT(i)    (-1)                                                                                                              /**< Port number for AF_TIMER2_CDTI2 location number i */
+#define AF_ACMP0_OUT_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 3 : (i) == 3 ? 1 :  -1)                                                /**< Port number for AF_ACMP0_OUT location number i */
+#define AF_USART0_TX_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 2 :  -1)   /**< Port number for AF_USART0_TX location number i */
+#define AF_USART0_RX_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 2 :  -1)   /**< Port number for AF_USART0_RX location number i */
+#define AF_USART0_CLK_PORT(i)      ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 4 :  -1)   /**< Port number for AF_USART0_CLK location number i */
+#define AF_USART0_CS_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 4 :  -1)   /**< Port number for AF_USART0_CS location number i */
+#define AF_USART1_TX_PORT(i)       ((i) == 0 ? 2 : (i) == 1 ? -1 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 2 :  -1)                  /**< Port number for AF_USART1_TX location number i */
+#define AF_USART1_RX_PORT(i)       ((i) == 0 ? 2 : (i) == 1 ? -1 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 2 :  -1)                  /**< Port number for AF_USART1_RX location number i */
+#define AF_USART1_CLK_PORT(i)      ((i) == 0 ? 1 : (i) == 1 ? -1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 2 :  -1)                  /**< Port number for AF_USART1_CLK location number i */
+#define AF_USART1_CS_PORT(i)       ((i) == 0 ? 1 : (i) == 1 ? -1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)                  /**< Port number for AF_USART1_CS location number i */
+#define AF_PRS_CH0_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 :  -1)                                                 /**< Port number for AF_PRS_CH0 location number i */
+#define AF_PRS_CH1_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 :  -1)                                                 /**< Port number for AF_PRS_CH1 location number i */
+#define AF_PRS_CH2_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 :  -1)                                                 /**< Port number for AF_PRS_CH2 location number i */
+#define AF_PRS_CH3_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? -1 : (i) == 2 ? 4 : (i) == 3 ? 0 :  -1)                                                /**< Port number for AF_PRS_CH3 location number i */
+#define AF_LEUART0_TX_PORT(i)      ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 :  -1)                  /**< Port number for AF_LEUART0_TX location number i */
+#define AF_LEUART0_RX_PORT(i)      ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 :  -1)                  /**< Port number for AF_LEUART0_RX location number i */
+#define AF_PCNT0_S0IN_PORT(i)      ((i) == 0 ? 2 : (i) == 1 ? -1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 :  -1)                                 /**< Port number for AF_PCNT0_S0IN location number i */
+#define AF_PCNT0_S1IN_PORT(i)      ((i) == 0 ? 2 : (i) == 1 ? -1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 1 :  -1)                                 /**< Port number for AF_PCNT0_S1IN location number i */
+#define AF_I2C0_SDA_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 :  -1)  /**< Port number for AF_I2C0_SDA location number i */
+#define AF_I2C0_SCL_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 :  -1)  /**< Port number for AF_I2C0_SCL location number i */
+#define AF_DBG_SWDIO_PORT(i)       ((i) == 0 ? 5 :  -1)                                                                                              /**< Port number for AF_DBG_SWDIO location number i */
+#define AF_DBG_SWCLK_PORT(i)       ((i) == 0 ? 5 :  -1)                                                                                              /**< Port number for AF_DBG_SWCLK location number i */
+
+/** @} End of group EFM32HG_AF_Ports */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_calibrate.h

@@ -0,0 +1,61 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_CALIBRATE register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_CALIBRATE
+ * @{
+ ******************************************************************************/
+#define CALIBRATE_MAX_REGISTERS    50 /**< Max number of address/value pairs for calibration */
+
+typedef struct {
+  __IM uint32_t ADDRESS; /**< Address of calibration register */
+  __IM uint32_t VALUE;   /**< Default value for calibration register */
+} CALIBRATE_TypeDef;     /** @} */
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_devinfo.h

@@ -0,0 +1,177 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_DEVINFO register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_DEVINFO
+ * @{
+ ******************************************************************************/
+typedef struct {
+  __IM uint32_t CAL;           /**< Calibration temperature and checksum */
+  __IM uint32_t ADC0CAL0;      /**< ADC0 Calibration register 0 */
+  __IM uint32_t ADC0CAL1;      /**< ADC0 Calibration register 1 */
+  __IM uint32_t ADC0CAL2;      /**< ADC0 Calibration register 2 */
+  uint32_t      RESERVED0[2U]; /**< Reserved */
+  __IM uint32_t IDAC0CAL0;     /**< IDAC0 calibration register */
+  __IM uint32_t USHFRCOCAL0;   /**< USHFRCO calibration register */
+  uint32_t      RESERVED1[1U]; /**< Reserved */
+  __IM uint32_t AUXHFRCOCAL0;  /**< AUXHFRCO calibration register 0 */
+  __IM uint32_t AUXHFRCOCAL1;  /**< AUXHFRCO calibration register 1 */
+  __IM uint32_t HFRCOCAL0;     /**< HFRCO calibration register 0 */
+  __IM uint32_t HFRCOCAL1;     /**< HFRCO calibration register 1 */
+  __IM uint32_t MEMINFO;       /**< Memory information */
+  uint32_t      RESERVED2[2U]; /**< Reserved */
+  __IM uint32_t UNIQUEL;       /**< Low 32 bits of device unique number */
+  __IM uint32_t UNIQUEH;       /**< High 32 bits of device unique number */
+  __IM uint32_t MSIZE;         /**< Flash and SRAM Memory size in KiloBytes */
+  __IM uint32_t PART;          /**< Part description */
+} DEVINFO_TypeDef;             /** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_DEVINFO_BitFields
+ * @{
+ ******************************************************************************/
+/* Bit fields for EFM32HG_DEVINFO */
+#define _DEVINFO_CAL_CRC_MASK                           0x0000FFFFUL /**< Integrity CRC checksum mask */
+#define _DEVINFO_CAL_CRC_SHIFT                          0            /**< Integrity CRC checksum shift */
+#define _DEVINFO_CAL_TEMP_MASK                          0x00FF0000UL /**< Calibration temperature, DegC, mask */
+#define _DEVINFO_CAL_TEMP_SHIFT                         16           /**< Calibration temperature shift */
+#define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK                0x00007F00UL /**< Gain for 1V25 reference, mask */
+#define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT               8            /**< Gain for 1V25 reference, shift */
+#define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK              0x0000007FUL /**< Offset for 1V25 reference, mask */
+#define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT             0            /**< Offset for 1V25 reference, shift */
+#define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK                 0x7F000000UL /**< Gain for 2V5 reference, mask */
+#define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT                24           /**< Gain for 2V5 reference, shift */
+#define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK               0x007F0000UL /**< Offset for 2V5 reference, mask */
+#define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT              16           /**< Offset for 2V5 reference, shift */
+#define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK                 0x00007F00UL /**< Gain for VDD reference, mask */
+#define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT                8            /**< Gain for VDD reference, shift */
+#define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK               0x0000007FUL /**< Offset for VDD reference, mask */
+#define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT              0            /**< Offset for VDD reference, shift */
+#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK              0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
+#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT             24           /**< Gain for 5VDIFF reference, mask */
+#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK            0x007F0000UL /**< Offset for 5VDIFF reference, mask */
+#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT           16           /**< Offset for 5VDIFF reference, shift */
+#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK          0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
+#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT         0            /**< Offset for 2XVDDVSS reference, shift */
+#define _DEVINFO_ADC0CAL2_TEMP1V25_MASK                 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
+#define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT                20           /**< Temperature reading at 1V25 reference, DegC */
+#define _DEVINFO_IDAC0CAL0_RANGE0_MASK                  0x000000FFUL /**< Current range 0 tuning value for IDAC0 mask */
+#define _DEVINFO_IDAC0CAL0_RANGE0_SHIFT                 0            /**< Current range 0 tuning value for IDAC0 shift */
+#define _DEVINFO_IDAC0CAL0_RANGE1_MASK                  0x0000FF00UL /**< Current range 1 tuning value for IDAC0 mask */
+#define _DEVINFO_IDAC0CAL0_RANGE1_SHIFT                 8            /**< Current range 1 tuning value for IDAC0 shift */
+#define _DEVINFO_IDAC0CAL0_RANGE2_MASK                  0x00FF0000UL /**< Current range 2 tuning value for IDAC0 mask */
+#define _DEVINFO_IDAC0CAL0_RANGE2_SHIFT                 16           /**< Current range 2 tuning value for IDAC0 shift */
+#define _DEVINFO_IDAC0CAL0_RANGE3_MASK                  0xFF000000UL /**< Current range 3 tuning value for IDAC0 mask */
+#define _DEVINFO_IDAC0CAL0_RANGE3_SHIFT                 24           /**< Current range 3 tuning value for IDAC0 shift */
+#define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK         0x0000007FUL /**< 24 MHz TUNING value for USFRCO mask */
+#define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT        0            /**< 24 MHz TUNING value for USFRCO shift */
+#define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK     0x00003F00UL /**< 24 MHz FINETUNING value for USFRCO mask */
+#define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT    8            /**< 24 MHz FINETUNING value for USFRCO shift */
+#define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK         0x007F0000UL /**< 24 MHz TUNING value for USFRCO mask */
+#define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT        16           /**< 24 MHz TUNING value for USFRCO shift */
+#define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK     0x3F000000UL /**< 24 MHz FINETUNING value for USFRCO mask */
+#define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT    24           /**< 24 MHz FINETUNING value for USFRCO shift */
+#define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK                0x000000FFUL /**< 1MHz tuning value for AUXHFRCO, mask */
+#define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT               0            /**< 1MHz tuning value for AUXHFRCO, shift */
+#define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK                0x0000FF00UL /**< 7MHz tuning value for AUXHFRCO, mask */
+#define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT               8            /**< 7MHz tuning value for AUXHFRCO, shift */
+#define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK               0x00FF0000UL /**< 11MHz tuning value for AUXHFRCO, mask */
+#define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT              16           /**< 11MHz tuning value for AUXHFRCO, shift */
+#define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK               0xFF000000UL /**< 14MHz tuning value for AUXHFRCO, mask */
+#define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT              24           /**< 14MHz tuning value for AUXHFRCO, shift */
+#define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK               0x000000FFUL /**< 21MHz tuning value for AUXHFRCO, mask */
+#define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT              0            /**< 21MHz tuning value for AUXHFRCO, shift */
+#define _DEVINFO_HFRCOCAL0_BAND1_MASK                   0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
+#define _DEVINFO_HFRCOCAL0_BAND1_SHIFT                  0            /**< 1MHz tuning value for HFRCO, shift */
+#define _DEVINFO_HFRCOCAL0_BAND7_MASK                   0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
+#define _DEVINFO_HFRCOCAL0_BAND7_SHIFT                  8            /**< 7MHz tuning value for HFRCO, shift */
+#define _DEVINFO_HFRCOCAL0_BAND11_MASK                  0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
+#define _DEVINFO_HFRCOCAL0_BAND11_SHIFT                 16           /**< 11MHz tuning value for HFRCO, shift */
+#define _DEVINFO_HFRCOCAL0_BAND14_MASK                  0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
+#define _DEVINFO_HFRCOCAL0_BAND14_SHIFT                 24           /**< 14MHz tuning value for HFRCO, shift */
+#define _DEVINFO_HFRCOCAL1_BAND21_MASK                  0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
+#define _DEVINFO_HFRCOCAL1_BAND21_SHIFT                 0            /**< 21MHz tuning value for HFRCO, shift */
+#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK           0xFF000000UL /**< Flash page size (refer to ref.man for encoding) mask */
+#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT          24           /**< Flash page size shift */
+#define _DEVINFO_UNIQUEL_MASK                           0xFFFFFFFFUL /**< Lower part of  64-bit device unique number */
+#define _DEVINFO_UNIQUEL_SHIFT                          0            /**< Unique Low 32-bit shift */
+#define _DEVINFO_UNIQUEH_MASK                           0xFFFFFFFFUL /**< High part of  64-bit device unique number */
+#define _DEVINFO_UNIQUEH_SHIFT                          0            /**< Unique High 32-bit shift */
+#define _DEVINFO_MSIZE_SRAM_MASK                        0xFFFF0000UL /**< Flash size in kilobytes */
+#define _DEVINFO_MSIZE_SRAM_SHIFT                       16           /**< Bit position for flash size */
+#define _DEVINFO_MSIZE_FLASH_MASK                       0x0000FFFFUL /**< SRAM size in kilobytes */
+#define _DEVINFO_MSIZE_FLASH_SHIFT                      0            /**< Bit position for SRAM size */
+#define _DEVINFO_PART_PROD_REV_MASK                     0xFF000000UL /**< Production revision */
+#define _DEVINFO_PART_PROD_REV_SHIFT                    24           /**< Bit position for production revision */
+#define _DEVINFO_PART_DEVICE_FAMILY_MASK                0x00FF0000UL /**< Device Family, 0x47 for Gecko */
+#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT               16           /**< Bit position for device family */
+/* Legacy family #defines */
+#define _DEVINFO_PART_DEVICE_FAMILY_G                   71           /**< Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_GG                  72           /**< Giant Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_TG                  73           /**< Tiny Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_LG                  74           /**< Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_WG                  75           /**< Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_ZG                  76           /**< Zero Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG                  77           /**< Happy Gecko Device Family */
+/* New style family #defines */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G              71           /**< Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG             72           /**< Giant Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG             73           /**< Tiny Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG             74           /**< Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG             75           /**< Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG             76           /**< Zero Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG             77           /**< Happy Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG             120          /**< EZR Wonder Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG             121          /**< EZR Leopard Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG             122          /**< EZR Happy Gecko Device Family */
+#define _DEVINFO_PART_DEVICE_NUMBER_MASK                0x0000FFFFUL /**< Device number */
+#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT               0            /**< Bit position for device number */
+
+/** @} End of group EFM32HG_DEVINFO */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_dma.h

@@ -0,0 +1,904 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_DMA register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_DMA
+ * @{
+ * @brief EFM32HG_DMA Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IM uint32_t  STATUS;          /**< DMA Status Registers  */
+  __OM uint32_t  CONFIG;          /**< DMA Configuration Register  */
+  __IOM uint32_t CTRLBASE;        /**< Channel Control Data Base Pointer Register  */
+  __IM uint32_t  ALTCTRLBASE;     /**< Channel Alternate Control Data Base Pointer Register  */
+  __IM uint32_t  CHWAITSTATUS;    /**< Channel Wait on Request Status Register  */
+  __OM uint32_t  CHSWREQ;         /**< Channel Software Request Register  */
+  __IOM uint32_t CHUSEBURSTS;     /**< Channel Useburst Set Register  */
+  __OM uint32_t  CHUSEBURSTC;     /**< Channel Useburst Clear Register  */
+  __IOM uint32_t CHREQMASKS;      /**< Channel Request Mask Set Register  */
+  __OM uint32_t  CHREQMASKC;      /**< Channel Request Mask Clear Register  */
+  __IOM uint32_t CHENS;           /**< Channel Enable Set Register  */
+  __OM uint32_t  CHENC;           /**< Channel Enable Clear Register  */
+  __IOM uint32_t CHALTS;          /**< Channel Alternate Set Register  */
+  __OM uint32_t  CHALTC;          /**< Channel Alternate Clear Register  */
+  __IOM uint32_t CHPRIS;          /**< Channel Priority Set Register  */
+  __OM uint32_t  CHPRIC;          /**< Channel Priority Clear Register  */
+  uint32_t       RESERVED0[3U];   /**< Reserved for future use **/
+  __IOM uint32_t ERRORC;          /**< Bus Error Clear Register  */
+
+  uint32_t       RESERVED1[880U]; /**< Reserved for future use **/
+  __IM uint32_t  CHREQSTATUS;     /**< Channel Request Status  */
+  uint32_t       RESERVED2[1U];   /**< Reserved for future use **/
+  __IM uint32_t  CHSREQSTATUS;    /**< Channel Single Request Status  */
+
+  uint32_t       RESERVED3[121U]; /**< Reserved for future use **/
+  __IM uint32_t  IF;              /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;             /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;             /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;             /**< Interrupt Enable register  */
+
+  uint32_t       RESERVED4[60U];  /**< Reserved registers */
+  DMA_CH_TypeDef CH[6U];          /**< Channel registers */
+} DMA_TypeDef;                    /**< DMA Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_DMA_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for DMA STATUS */
+#define _DMA_STATUS_RESETVALUE                          0x10050000UL                          /**< Default value for DMA_STATUS */
+#define _DMA_STATUS_MASK                                0x001F00F1UL                          /**< Mask for DMA_STATUS */
+#define DMA_STATUS_EN                                   (0x1UL << 0)                          /**< DMA Enable Status */
+#define _DMA_STATUS_EN_SHIFT                            0                                     /**< Shift value for DMA_EN */
+#define _DMA_STATUS_EN_MASK                             0x1UL                                 /**< Bit mask for DMA_EN */
+#define _DMA_STATUS_EN_DEFAULT                          0x00000000UL                          /**< Mode DEFAULT for DMA_STATUS */
+#define DMA_STATUS_EN_DEFAULT                           (_DMA_STATUS_EN_DEFAULT << 0)         /**< Shifted mode DEFAULT for DMA_STATUS */
+#define _DMA_STATUS_STATE_SHIFT                         4                                     /**< Shift value for DMA_STATE */
+#define _DMA_STATUS_STATE_MASK                          0xF0UL                                /**< Bit mask for DMA_STATE */
+#define _DMA_STATUS_STATE_DEFAULT                       0x00000000UL                          /**< Mode DEFAULT for DMA_STATUS */
+#define _DMA_STATUS_STATE_IDLE                          0x00000000UL                          /**< Mode IDLE for DMA_STATUS */
+#define _DMA_STATUS_STATE_RDCHCTRLDATA                  0x00000001UL                          /**< Mode RDCHCTRLDATA for DMA_STATUS */
+#define _DMA_STATUS_STATE_RDSRCENDPTR                   0x00000002UL                          /**< Mode RDSRCENDPTR for DMA_STATUS */
+#define _DMA_STATUS_STATE_RDDSTENDPTR                   0x00000003UL                          /**< Mode RDDSTENDPTR for DMA_STATUS */
+#define _DMA_STATUS_STATE_RDSRCDATA                     0x00000004UL                          /**< Mode RDSRCDATA for DMA_STATUS */
+#define _DMA_STATUS_STATE_WRDSTDATA                     0x00000005UL                          /**< Mode WRDSTDATA for DMA_STATUS */
+#define _DMA_STATUS_STATE_WAITREQCLR                    0x00000006UL                          /**< Mode WAITREQCLR for DMA_STATUS */
+#define _DMA_STATUS_STATE_WRCHCTRLDATA                  0x00000007UL                          /**< Mode WRCHCTRLDATA for DMA_STATUS */
+#define _DMA_STATUS_STATE_STALLED                       0x00000008UL                          /**< Mode STALLED for DMA_STATUS */
+#define _DMA_STATUS_STATE_DONE                          0x00000009UL                          /**< Mode DONE for DMA_STATUS */
+#define _DMA_STATUS_STATE_PERSCATTRANS                  0x0000000AUL                          /**< Mode PERSCATTRANS for DMA_STATUS */
+#define DMA_STATUS_STATE_DEFAULT                        (_DMA_STATUS_STATE_DEFAULT << 4)      /**< Shifted mode DEFAULT for DMA_STATUS */
+#define DMA_STATUS_STATE_IDLE                           (_DMA_STATUS_STATE_IDLE << 4)         /**< Shifted mode IDLE for DMA_STATUS */
+#define DMA_STATUS_STATE_RDCHCTRLDATA                   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */
+#define DMA_STATUS_STATE_RDSRCENDPTR                    (_DMA_STATUS_STATE_RDSRCENDPTR << 4)  /**< Shifted mode RDSRCENDPTR for DMA_STATUS */
+#define DMA_STATUS_STATE_RDDSTENDPTR                    (_DMA_STATUS_STATE_RDDSTENDPTR << 4)  /**< Shifted mode RDDSTENDPTR for DMA_STATUS */
+#define DMA_STATUS_STATE_RDSRCDATA                      (_DMA_STATUS_STATE_RDSRCDATA << 4)    /**< Shifted mode RDSRCDATA for DMA_STATUS */
+#define DMA_STATUS_STATE_WRDSTDATA                      (_DMA_STATUS_STATE_WRDSTDATA << 4)    /**< Shifted mode WRDSTDATA for DMA_STATUS */
+#define DMA_STATUS_STATE_WAITREQCLR                     (_DMA_STATUS_STATE_WAITREQCLR << 4)   /**< Shifted mode WAITREQCLR for DMA_STATUS */
+#define DMA_STATUS_STATE_WRCHCTRLDATA                   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */
+#define DMA_STATUS_STATE_STALLED                        (_DMA_STATUS_STATE_STALLED << 4)      /**< Shifted mode STALLED for DMA_STATUS */
+#define DMA_STATUS_STATE_DONE                           (_DMA_STATUS_STATE_DONE << 4)         /**< Shifted mode DONE for DMA_STATUS */
+#define DMA_STATUS_STATE_PERSCATTRANS                   (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */
+#define _DMA_STATUS_CHNUM_SHIFT                         16                                    /**< Shift value for DMA_CHNUM */
+#define _DMA_STATUS_CHNUM_MASK                          0x1F0000UL                            /**< Bit mask for DMA_CHNUM */
+#define _DMA_STATUS_CHNUM_DEFAULT                       0x00000005UL                          /**< Mode DEFAULT for DMA_STATUS */
+#define DMA_STATUS_CHNUM_DEFAULT                        (_DMA_STATUS_CHNUM_DEFAULT << 16)     /**< Shifted mode DEFAULT for DMA_STATUS */
+
+/* Bit fields for DMA CONFIG */
+#define _DMA_CONFIG_RESETVALUE                          0x00000000UL                      /**< Default value for DMA_CONFIG */
+#define _DMA_CONFIG_MASK                                0x00000021UL                      /**< Mask for DMA_CONFIG */
+#define DMA_CONFIG_EN                                   (0x1UL << 0)                      /**< Enable DMA */
+#define _DMA_CONFIG_EN_SHIFT                            0                                 /**< Shift value for DMA_EN */
+#define _DMA_CONFIG_EN_MASK                             0x1UL                             /**< Bit mask for DMA_EN */
+#define _DMA_CONFIG_EN_DEFAULT                          0x00000000UL                      /**< Mode DEFAULT for DMA_CONFIG */
+#define DMA_CONFIG_EN_DEFAULT                           (_DMA_CONFIG_EN_DEFAULT << 0)     /**< Shifted mode DEFAULT for DMA_CONFIG */
+#define DMA_CONFIG_CHPROT                               (0x1UL << 5)                      /**< Channel Protection Control */
+#define _DMA_CONFIG_CHPROT_SHIFT                        5                                 /**< Shift value for DMA_CHPROT */
+#define _DMA_CONFIG_CHPROT_MASK                         0x20UL                            /**< Bit mask for DMA_CHPROT */
+#define _DMA_CONFIG_CHPROT_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for DMA_CONFIG */
+#define DMA_CONFIG_CHPROT_DEFAULT                       (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */
+
+/* Bit fields for DMA CTRLBASE */
+#define _DMA_CTRLBASE_RESETVALUE                        0x00000000UL                          /**< Default value for DMA_CTRLBASE */
+#define _DMA_CTRLBASE_MASK                              0xFFFFFFFFUL                          /**< Mask for DMA_CTRLBASE */
+#define _DMA_CTRLBASE_CTRLBASE_SHIFT                    0                                     /**< Shift value for DMA_CTRLBASE */
+#define _DMA_CTRLBASE_CTRLBASE_MASK                     0xFFFFFFFFUL                          /**< Bit mask for DMA_CTRLBASE */
+#define _DMA_CTRLBASE_CTRLBASE_DEFAULT                  0x00000000UL                          /**< Mode DEFAULT for DMA_CTRLBASE */
+#define DMA_CTRLBASE_CTRLBASE_DEFAULT                   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */
+
+/* Bit fields for DMA ALTCTRLBASE */
+#define _DMA_ALTCTRLBASE_RESETVALUE                     0x00000080UL                                /**< Default value for DMA_ALTCTRLBASE */
+#define _DMA_ALTCTRLBASE_MASK                           0xFFFFFFFFUL                                /**< Mask for DMA_ALTCTRLBASE */
+#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT              0                                           /**< Shift value for DMA_ALTCTRLBASE */
+#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK               0xFFFFFFFFUL                                /**< Bit mask for DMA_ALTCTRLBASE */
+#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT            0x00000080UL                                /**< Mode DEFAULT for DMA_ALTCTRLBASE */
+#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT             (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */
+
+/* Bit fields for DMA CHWAITSTATUS */
+#define _DMA_CHWAITSTATUS_RESETVALUE                    0x0000003FUL                                   /**< Default value for DMA_CHWAITSTATUS */
+#define _DMA_CHWAITSTATUS_MASK                          0x0000003FUL                                   /**< Mask for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH0WAITSTATUS                  (0x1UL << 0)                                   /**< Channel 0 Wait on Request Status */
+#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT           0                                              /**< Shift value for DMA_CH0WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK            0x1UL                                          /**< Bit mask for DMA_CH0WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT         0x00000001UL                                   /**< Mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH1WAITSTATUS                  (0x1UL << 1)                                   /**< Channel 1 Wait on Request Status */
+#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT           1                                              /**< Shift value for DMA_CH1WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK            0x2UL                                          /**< Bit mask for DMA_CH1WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT         0x00000001UL                                   /**< Mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH2WAITSTATUS                  (0x1UL << 2)                                   /**< Channel 2 Wait on Request Status */
+#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT           2                                              /**< Shift value for DMA_CH2WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK            0x4UL                                          /**< Bit mask for DMA_CH2WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT         0x00000001UL                                   /**< Mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH3WAITSTATUS                  (0x1UL << 3)                                   /**< Channel 3 Wait on Request Status */
+#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT           3                                              /**< Shift value for DMA_CH3WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK            0x8UL                                          /**< Bit mask for DMA_CH3WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT         0x00000001UL                                   /**< Mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH4WAITSTATUS                  (0x1UL << 4)                                   /**< Channel 4 Wait on Request Status */
+#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT           4                                              /**< Shift value for DMA_CH4WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK            0x10UL                                         /**< Bit mask for DMA_CH4WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT         0x00000001UL                                   /**< Mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH5WAITSTATUS                  (0x1UL << 5)                                   /**< Channel 5 Wait on Request Status */
+#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT           5                                              /**< Shift value for DMA_CH5WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK            0x20UL                                         /**< Bit mask for DMA_CH5WAITSTATUS */
+#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT         0x00000001UL                                   /**< Mode DEFAULT for DMA_CHWAITSTATUS */
+#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
+
+/* Bit fields for DMA CHSWREQ */
+#define _DMA_CHSWREQ_RESETVALUE                         0x00000000UL                         /**< Default value for DMA_CHSWREQ */
+#define _DMA_CHSWREQ_MASK                               0x0000003FUL                         /**< Mask for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH0SWREQ                            (0x1UL << 0)                         /**< Channel 0 Software Request */
+#define _DMA_CHSWREQ_CH0SWREQ_SHIFT                     0                                    /**< Shift value for DMA_CH0SWREQ */
+#define _DMA_CHSWREQ_CH0SWREQ_MASK                      0x1UL                                /**< Bit mask for DMA_CH0SWREQ */
+#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH0SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH1SWREQ                            (0x1UL << 1)                         /**< Channel 1 Software Request */
+#define _DMA_CHSWREQ_CH1SWREQ_SHIFT                     1                                    /**< Shift value for DMA_CH1SWREQ */
+#define _DMA_CHSWREQ_CH1SWREQ_MASK                      0x2UL                                /**< Bit mask for DMA_CH1SWREQ */
+#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH1SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH2SWREQ                            (0x1UL << 2)                         /**< Channel 2 Software Request */
+#define _DMA_CHSWREQ_CH2SWREQ_SHIFT                     2                                    /**< Shift value for DMA_CH2SWREQ */
+#define _DMA_CHSWREQ_CH2SWREQ_MASK                      0x4UL                                /**< Bit mask for DMA_CH2SWREQ */
+#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH2SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH3SWREQ                            (0x1UL << 3)                         /**< Channel 3 Software Request */
+#define _DMA_CHSWREQ_CH3SWREQ_SHIFT                     3                                    /**< Shift value for DMA_CH3SWREQ */
+#define _DMA_CHSWREQ_CH3SWREQ_MASK                      0x8UL                                /**< Bit mask for DMA_CH3SWREQ */
+#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH3SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH4SWREQ                            (0x1UL << 4)                         /**< Channel 4 Software Request */
+#define _DMA_CHSWREQ_CH4SWREQ_SHIFT                     4                                    /**< Shift value for DMA_CH4SWREQ */
+#define _DMA_CHSWREQ_CH4SWREQ_MASK                      0x10UL                               /**< Bit mask for DMA_CH4SWREQ */
+#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH4SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH5SWREQ                            (0x1UL << 5)                         /**< Channel 5 Software Request */
+#define _DMA_CHSWREQ_CH5SWREQ_SHIFT                     5                                    /**< Shift value for DMA_CH5SWREQ */
+#define _DMA_CHSWREQ_CH5SWREQ_MASK                      0x20UL                               /**< Bit mask for DMA_CH5SWREQ */
+#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for DMA_CHSWREQ */
+#define DMA_CHSWREQ_CH5SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
+
+/* Bit fields for DMA CHUSEBURSTS */
+#define _DMA_CHUSEBURSTS_RESETVALUE                     0x00000000UL                                        /**< Default value for DMA_CHUSEBURSTS */
+#define _DMA_CHUSEBURSTS_MASK                           0x0000003FUL                                        /**< Mask for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH0USEBURSTS                    (0x1UL << 0)                                        /**< Channel 0 Useburst Set */
+#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT             0                                                   /**< Shift value for DMA_CH0USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK              0x1UL                                               /**< Bit mask for DMA_CH0USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT           0x00000000UL                                        /**< Mode DEFAULT for DMA_CHUSEBURSTS */
+#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST    0x00000000UL                                        /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */
+#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY         0x00000001UL                                        /**< Mode BURSTONLY for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)        /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST     (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY          (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)      /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH1USEBURSTS                    (0x1UL << 1)                                        /**< Channel 1 Useburst Set */
+#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT             1                                                   /**< Shift value for DMA_CH1USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK              0x2UL                                               /**< Bit mask for DMA_CH1USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT           0x00000000UL                                        /**< Mode DEFAULT for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)        /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH2USEBURSTS                    (0x1UL << 2)                                        /**< Channel 2 Useburst Set */
+#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT             2                                                   /**< Shift value for DMA_CH2USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK              0x4UL                                               /**< Bit mask for DMA_CH2USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT           0x00000000UL                                        /**< Mode DEFAULT for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)        /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH3USEBURSTS                    (0x1UL << 3)                                        /**< Channel 3 Useburst Set */
+#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT             3                                                   /**< Shift value for DMA_CH3USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK              0x8UL                                               /**< Bit mask for DMA_CH3USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT           0x00000000UL                                        /**< Mode DEFAULT for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)        /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH4USEBURSTS                    (0x1UL << 4)                                        /**< Channel 4 Useburst Set */
+#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT             4                                                   /**< Shift value for DMA_CH4USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK              0x10UL                                              /**< Bit mask for DMA_CH4USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT           0x00000000UL                                        /**< Mode DEFAULT for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)        /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH5USEBURSTS                    (0x1UL << 5)                                        /**< Channel 5 Useburst Set */
+#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT             5                                                   /**< Shift value for DMA_CH5USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK              0x20UL                                              /**< Bit mask for DMA_CH5USEBURSTS */
+#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT           0x00000000UL                                        /**< Mode DEFAULT for DMA_CHUSEBURSTS */
+#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)        /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
+
+/* Bit fields for DMA CHUSEBURSTC */
+#define _DMA_CHUSEBURSTC_RESETVALUE                     0x00000000UL                                 /**< Default value for DMA_CHUSEBURSTC */
+#define _DMA_CHUSEBURSTC_MASK                           0x0000003FUL                                 /**< Mask for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH0USEBURSTC                    (0x1UL << 0)                                 /**< Channel 0 Useburst Clear */
+#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT             0                                            /**< Shift value for DMA_CH0USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK              0x1UL                                        /**< Bit mask for DMA_CH0USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH1USEBURSTC                    (0x1UL << 1)                                 /**< Channel 1 Useburst Clear */
+#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT             1                                            /**< Shift value for DMA_CH1USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK              0x2UL                                        /**< Bit mask for DMA_CH1USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH2USEBURSTC                    (0x1UL << 2)                                 /**< Channel 2 Useburst Clear */
+#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT             2                                            /**< Shift value for DMA_CH2USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK              0x4UL                                        /**< Bit mask for DMA_CH2USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH3USEBURSTC                    (0x1UL << 3)                                 /**< Channel 3 Useburst Clear */
+#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT             3                                            /**< Shift value for DMA_CH3USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK              0x8UL                                        /**< Bit mask for DMA_CH3USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH4USEBURSTC                    (0x1UL << 4)                                 /**< Channel 4 Useburst Clear */
+#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT             4                                            /**< Shift value for DMA_CH4USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK              0x10UL                                       /**< Bit mask for DMA_CH4USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH5USEBURSTC                    (0x1UL << 5)                                 /**< Channel 5 Useburst Clear */
+#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT             5                                            /**< Shift value for DMA_CH5USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK              0x20UL                                       /**< Bit mask for DMA_CH5USEBURSTC */
+#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHUSEBURSTC */
+#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
+
+/* Bit fields for DMA CHREQMASKS */
+#define _DMA_CHREQMASKS_RESETVALUE                      0x00000000UL                               /**< Default value for DMA_CHREQMASKS */
+#define _DMA_CHREQMASKS_MASK                            0x0000003FUL                               /**< Mask for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH0REQMASKS                      (0x1UL << 0)                               /**< Channel 0 Request Mask Set */
+#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT               0                                          /**< Shift value for DMA_CH0REQMASKS */
+#define _DMA_CHREQMASKS_CH0REQMASKS_MASK                0x1UL                                      /**< Bit mask for DMA_CH0REQMASKS */
+#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH1REQMASKS                      (0x1UL << 1)                               /**< Channel 1 Request Mask Set */
+#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT               1                                          /**< Shift value for DMA_CH1REQMASKS */
+#define _DMA_CHREQMASKS_CH1REQMASKS_MASK                0x2UL                                      /**< Bit mask for DMA_CH1REQMASKS */
+#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH2REQMASKS                      (0x1UL << 2)                               /**< Channel 2 Request Mask Set */
+#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT               2                                          /**< Shift value for DMA_CH2REQMASKS */
+#define _DMA_CHREQMASKS_CH2REQMASKS_MASK                0x4UL                                      /**< Bit mask for DMA_CH2REQMASKS */
+#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH3REQMASKS                      (0x1UL << 3)                               /**< Channel 3 Request Mask Set */
+#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT               3                                          /**< Shift value for DMA_CH3REQMASKS */
+#define _DMA_CHREQMASKS_CH3REQMASKS_MASK                0x8UL                                      /**< Bit mask for DMA_CH3REQMASKS */
+#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH4REQMASKS                      (0x1UL << 4)                               /**< Channel 4 Request Mask Set */
+#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT               4                                          /**< Shift value for DMA_CH4REQMASKS */
+#define _DMA_CHREQMASKS_CH4REQMASKS_MASK                0x10UL                                     /**< Bit mask for DMA_CH4REQMASKS */
+#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH5REQMASKS                      (0x1UL << 5)                               /**< Channel 5 Request Mask Set */
+#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT               5                                          /**< Shift value for DMA_CH5REQMASKS */
+#define _DMA_CHREQMASKS_CH5REQMASKS_MASK                0x20UL                                     /**< Bit mask for DMA_CH5REQMASKS */
+#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKS */
+#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
+
+/* Bit fields for DMA CHREQMASKC */
+#define _DMA_CHREQMASKC_RESETVALUE                      0x00000000UL                               /**< Default value for DMA_CHREQMASKC */
+#define _DMA_CHREQMASKC_MASK                            0x0000003FUL                               /**< Mask for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH0REQMASKC                      (0x1UL << 0)                               /**< Channel 0 Request Mask Clear */
+#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT               0                                          /**< Shift value for DMA_CH0REQMASKC */
+#define _DMA_CHREQMASKC_CH0REQMASKC_MASK                0x1UL                                      /**< Bit mask for DMA_CH0REQMASKC */
+#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH1REQMASKC                      (0x1UL << 1)                               /**< Channel 1 Request Mask Clear */
+#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT               1                                          /**< Shift value for DMA_CH1REQMASKC */
+#define _DMA_CHREQMASKC_CH1REQMASKC_MASK                0x2UL                                      /**< Bit mask for DMA_CH1REQMASKC */
+#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH2REQMASKC                      (0x1UL << 2)                               /**< Channel 2 Request Mask Clear */
+#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT               2                                          /**< Shift value for DMA_CH2REQMASKC */
+#define _DMA_CHREQMASKC_CH2REQMASKC_MASK                0x4UL                                      /**< Bit mask for DMA_CH2REQMASKC */
+#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH3REQMASKC                      (0x1UL << 3)                               /**< Channel 3 Request Mask Clear */
+#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT               3                                          /**< Shift value for DMA_CH3REQMASKC */
+#define _DMA_CHREQMASKC_CH3REQMASKC_MASK                0x8UL                                      /**< Bit mask for DMA_CH3REQMASKC */
+#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH4REQMASKC                      (0x1UL << 4)                               /**< Channel 4 Request Mask Clear */
+#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT               4                                          /**< Shift value for DMA_CH4REQMASKC */
+#define _DMA_CHREQMASKC_CH4REQMASKC_MASK                0x10UL                                     /**< Bit mask for DMA_CH4REQMASKC */
+#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH5REQMASKC                      (0x1UL << 5)                               /**< Channel 5 Request Mask Clear */
+#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT               5                                          /**< Shift value for DMA_CH5REQMASKC */
+#define _DMA_CHREQMASKC_CH5REQMASKC_MASK                0x20UL                                     /**< Bit mask for DMA_CH5REQMASKC */
+#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for DMA_CHREQMASKC */
+#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
+
+/* Bit fields for DMA CHENS */
+#define _DMA_CHENS_RESETVALUE                           0x00000000UL                     /**< Default value for DMA_CHENS */
+#define _DMA_CHENS_MASK                                 0x0000003FUL                     /**< Mask for DMA_CHENS */
+#define DMA_CHENS_CH0ENS                                (0x1UL << 0)                     /**< Channel 0 Enable Set */
+#define _DMA_CHENS_CH0ENS_SHIFT                         0                                /**< Shift value for DMA_CH0ENS */
+#define _DMA_CHENS_CH0ENS_MASK                          0x1UL                            /**< Bit mask for DMA_CH0ENS */
+#define _DMA_CHENS_CH0ENS_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH0ENS_DEFAULT                        (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH1ENS                                (0x1UL << 1)                     /**< Channel 1 Enable Set */
+#define _DMA_CHENS_CH1ENS_SHIFT                         1                                /**< Shift value for DMA_CH1ENS */
+#define _DMA_CHENS_CH1ENS_MASK                          0x2UL                            /**< Bit mask for DMA_CH1ENS */
+#define _DMA_CHENS_CH1ENS_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH1ENS_DEFAULT                        (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH2ENS                                (0x1UL << 2)                     /**< Channel 2 Enable Set */
+#define _DMA_CHENS_CH2ENS_SHIFT                         2                                /**< Shift value for DMA_CH2ENS */
+#define _DMA_CHENS_CH2ENS_MASK                          0x4UL                            /**< Bit mask for DMA_CH2ENS */
+#define _DMA_CHENS_CH2ENS_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH2ENS_DEFAULT                        (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH3ENS                                (0x1UL << 3)                     /**< Channel 3 Enable Set */
+#define _DMA_CHENS_CH3ENS_SHIFT                         3                                /**< Shift value for DMA_CH3ENS */
+#define _DMA_CHENS_CH3ENS_MASK                          0x8UL                            /**< Bit mask for DMA_CH3ENS */
+#define _DMA_CHENS_CH3ENS_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH3ENS_DEFAULT                        (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH4ENS                                (0x1UL << 4)                     /**< Channel 4 Enable Set */
+#define _DMA_CHENS_CH4ENS_SHIFT                         4                                /**< Shift value for DMA_CH4ENS */
+#define _DMA_CHENS_CH4ENS_MASK                          0x10UL                           /**< Bit mask for DMA_CH4ENS */
+#define _DMA_CHENS_CH4ENS_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH4ENS_DEFAULT                        (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH5ENS                                (0x1UL << 5)                     /**< Channel 5 Enable Set */
+#define _DMA_CHENS_CH5ENS_SHIFT                         5                                /**< Shift value for DMA_CH5ENS */
+#define _DMA_CHENS_CH5ENS_MASK                          0x20UL                           /**< Bit mask for DMA_CH5ENS */
+#define _DMA_CHENS_CH5ENS_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENS */
+#define DMA_CHENS_CH5ENS_DEFAULT                        (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */
+
+/* Bit fields for DMA CHENC */
+#define _DMA_CHENC_RESETVALUE                           0x00000000UL                     /**< Default value for DMA_CHENC */
+#define _DMA_CHENC_MASK                                 0x0000003FUL                     /**< Mask for DMA_CHENC */
+#define DMA_CHENC_CH0ENC                                (0x1UL << 0)                     /**< Channel 0 Enable Clear */
+#define _DMA_CHENC_CH0ENC_SHIFT                         0                                /**< Shift value for DMA_CH0ENC */
+#define _DMA_CHENC_CH0ENC_MASK                          0x1UL                            /**< Bit mask for DMA_CH0ENC */
+#define _DMA_CHENC_CH0ENC_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH0ENC_DEFAULT                        (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH1ENC                                (0x1UL << 1)                     /**< Channel 1 Enable Clear */
+#define _DMA_CHENC_CH1ENC_SHIFT                         1                                /**< Shift value for DMA_CH1ENC */
+#define _DMA_CHENC_CH1ENC_MASK                          0x2UL                            /**< Bit mask for DMA_CH1ENC */
+#define _DMA_CHENC_CH1ENC_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH1ENC_DEFAULT                        (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH2ENC                                (0x1UL << 2)                     /**< Channel 2 Enable Clear */
+#define _DMA_CHENC_CH2ENC_SHIFT                         2                                /**< Shift value for DMA_CH2ENC */
+#define _DMA_CHENC_CH2ENC_MASK                          0x4UL                            /**< Bit mask for DMA_CH2ENC */
+#define _DMA_CHENC_CH2ENC_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH2ENC_DEFAULT                        (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH3ENC                                (0x1UL << 3)                     /**< Channel 3 Enable Clear */
+#define _DMA_CHENC_CH3ENC_SHIFT                         3                                /**< Shift value for DMA_CH3ENC */
+#define _DMA_CHENC_CH3ENC_MASK                          0x8UL                            /**< Bit mask for DMA_CH3ENC */
+#define _DMA_CHENC_CH3ENC_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH3ENC_DEFAULT                        (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH4ENC                                (0x1UL << 4)                     /**< Channel 4 Enable Clear */
+#define _DMA_CHENC_CH4ENC_SHIFT                         4                                /**< Shift value for DMA_CH4ENC */
+#define _DMA_CHENC_CH4ENC_MASK                          0x10UL                           /**< Bit mask for DMA_CH4ENC */
+#define _DMA_CHENC_CH4ENC_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH4ENC_DEFAULT                        (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH5ENC                                (0x1UL << 5)                     /**< Channel 5 Enable Clear */
+#define _DMA_CHENC_CH5ENC_SHIFT                         5                                /**< Shift value for DMA_CH5ENC */
+#define _DMA_CHENC_CH5ENC_MASK                          0x20UL                           /**< Bit mask for DMA_CH5ENC */
+#define _DMA_CHENC_CH5ENC_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for DMA_CHENC */
+#define DMA_CHENC_CH5ENC_DEFAULT                        (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */
+
+/* Bit fields for DMA CHALTS */
+#define _DMA_CHALTS_RESETVALUE                          0x00000000UL                       /**< Default value for DMA_CHALTS */
+#define _DMA_CHALTS_MASK                                0x0000003FUL                       /**< Mask for DMA_CHALTS */
+#define DMA_CHALTS_CH0ALTS                              (0x1UL << 0)                       /**< Channel 0 Alternate Structure Set */
+#define _DMA_CHALTS_CH0ALTS_SHIFT                       0                                  /**< Shift value for DMA_CH0ALTS */
+#define _DMA_CHALTS_CH0ALTS_MASK                        0x1UL                              /**< Bit mask for DMA_CH0ALTS */
+#define _DMA_CHALTS_CH0ALTS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH0ALTS_DEFAULT                      (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH1ALTS                              (0x1UL << 1)                       /**< Channel 1 Alternate Structure Set */
+#define _DMA_CHALTS_CH1ALTS_SHIFT                       1                                  /**< Shift value for DMA_CH1ALTS */
+#define _DMA_CHALTS_CH1ALTS_MASK                        0x2UL                              /**< Bit mask for DMA_CH1ALTS */
+#define _DMA_CHALTS_CH1ALTS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH1ALTS_DEFAULT                      (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH2ALTS                              (0x1UL << 2)                       /**< Channel 2 Alternate Structure Set */
+#define _DMA_CHALTS_CH2ALTS_SHIFT                       2                                  /**< Shift value for DMA_CH2ALTS */
+#define _DMA_CHALTS_CH2ALTS_MASK                        0x4UL                              /**< Bit mask for DMA_CH2ALTS */
+#define _DMA_CHALTS_CH2ALTS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH2ALTS_DEFAULT                      (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH3ALTS                              (0x1UL << 3)                       /**< Channel 3 Alternate Structure Set */
+#define _DMA_CHALTS_CH3ALTS_SHIFT                       3                                  /**< Shift value for DMA_CH3ALTS */
+#define _DMA_CHALTS_CH3ALTS_MASK                        0x8UL                              /**< Bit mask for DMA_CH3ALTS */
+#define _DMA_CHALTS_CH3ALTS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH3ALTS_DEFAULT                      (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH4ALTS                              (0x1UL << 4)                       /**< Channel 4 Alternate Structure Set */
+#define _DMA_CHALTS_CH4ALTS_SHIFT                       4                                  /**< Shift value for DMA_CH4ALTS */
+#define _DMA_CHALTS_CH4ALTS_MASK                        0x10UL                             /**< Bit mask for DMA_CH4ALTS */
+#define _DMA_CHALTS_CH4ALTS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH4ALTS_DEFAULT                      (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH5ALTS                              (0x1UL << 5)                       /**< Channel 5 Alternate Structure Set */
+#define _DMA_CHALTS_CH5ALTS_SHIFT                       5                                  /**< Shift value for DMA_CH5ALTS */
+#define _DMA_CHALTS_CH5ALTS_MASK                        0x20UL                             /**< Bit mask for DMA_CH5ALTS */
+#define _DMA_CHALTS_CH5ALTS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTS */
+#define DMA_CHALTS_CH5ALTS_DEFAULT                      (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */
+
+/* Bit fields for DMA CHALTC */
+#define _DMA_CHALTC_RESETVALUE                          0x00000000UL                       /**< Default value for DMA_CHALTC */
+#define _DMA_CHALTC_MASK                                0x0000003FUL                       /**< Mask for DMA_CHALTC */
+#define DMA_CHALTC_CH0ALTC                              (0x1UL << 0)                       /**< Channel 0 Alternate Clear */
+#define _DMA_CHALTC_CH0ALTC_SHIFT                       0                                  /**< Shift value for DMA_CH0ALTC */
+#define _DMA_CHALTC_CH0ALTC_MASK                        0x1UL                              /**< Bit mask for DMA_CH0ALTC */
+#define _DMA_CHALTC_CH0ALTC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH0ALTC_DEFAULT                      (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH1ALTC                              (0x1UL << 1)                       /**< Channel 1 Alternate Clear */
+#define _DMA_CHALTC_CH1ALTC_SHIFT                       1                                  /**< Shift value for DMA_CH1ALTC */
+#define _DMA_CHALTC_CH1ALTC_MASK                        0x2UL                              /**< Bit mask for DMA_CH1ALTC */
+#define _DMA_CHALTC_CH1ALTC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH1ALTC_DEFAULT                      (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH2ALTC                              (0x1UL << 2)                       /**< Channel 2 Alternate Clear */
+#define _DMA_CHALTC_CH2ALTC_SHIFT                       2                                  /**< Shift value for DMA_CH2ALTC */
+#define _DMA_CHALTC_CH2ALTC_MASK                        0x4UL                              /**< Bit mask for DMA_CH2ALTC */
+#define _DMA_CHALTC_CH2ALTC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH2ALTC_DEFAULT                      (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH3ALTC                              (0x1UL << 3)                       /**< Channel 3 Alternate Clear */
+#define _DMA_CHALTC_CH3ALTC_SHIFT                       3                                  /**< Shift value for DMA_CH3ALTC */
+#define _DMA_CHALTC_CH3ALTC_MASK                        0x8UL                              /**< Bit mask for DMA_CH3ALTC */
+#define _DMA_CHALTC_CH3ALTC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH3ALTC_DEFAULT                      (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH4ALTC                              (0x1UL << 4)                       /**< Channel 4 Alternate Clear */
+#define _DMA_CHALTC_CH4ALTC_SHIFT                       4                                  /**< Shift value for DMA_CH4ALTC */
+#define _DMA_CHALTC_CH4ALTC_MASK                        0x10UL                             /**< Bit mask for DMA_CH4ALTC */
+#define _DMA_CHALTC_CH4ALTC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH4ALTC_DEFAULT                      (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH5ALTC                              (0x1UL << 5)                       /**< Channel 5 Alternate Clear */
+#define _DMA_CHALTC_CH5ALTC_SHIFT                       5                                  /**< Shift value for DMA_CH5ALTC */
+#define _DMA_CHALTC_CH5ALTC_MASK                        0x20UL                             /**< Bit mask for DMA_CH5ALTC */
+#define _DMA_CHALTC_CH5ALTC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHALTC */
+#define DMA_CHALTC_CH5ALTC_DEFAULT                      (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */
+
+/* Bit fields for DMA CHPRIS */
+#define _DMA_CHPRIS_RESETVALUE                          0x00000000UL                       /**< Default value for DMA_CHPRIS */
+#define _DMA_CHPRIS_MASK                                0x0000003FUL                       /**< Mask for DMA_CHPRIS */
+#define DMA_CHPRIS_CH0PRIS                              (0x1UL << 0)                       /**< Channel 0 High Priority Set */
+#define _DMA_CHPRIS_CH0PRIS_SHIFT                       0                                  /**< Shift value for DMA_CH0PRIS */
+#define _DMA_CHPRIS_CH0PRIS_MASK                        0x1UL                              /**< Bit mask for DMA_CH0PRIS */
+#define _DMA_CHPRIS_CH0PRIS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH0PRIS_DEFAULT                      (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH1PRIS                              (0x1UL << 1)                       /**< Channel 1 High Priority Set */
+#define _DMA_CHPRIS_CH1PRIS_SHIFT                       1                                  /**< Shift value for DMA_CH1PRIS */
+#define _DMA_CHPRIS_CH1PRIS_MASK                        0x2UL                              /**< Bit mask for DMA_CH1PRIS */
+#define _DMA_CHPRIS_CH1PRIS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH1PRIS_DEFAULT                      (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH2PRIS                              (0x1UL << 2)                       /**< Channel 2 High Priority Set */
+#define _DMA_CHPRIS_CH2PRIS_SHIFT                       2                                  /**< Shift value for DMA_CH2PRIS */
+#define _DMA_CHPRIS_CH2PRIS_MASK                        0x4UL                              /**< Bit mask for DMA_CH2PRIS */
+#define _DMA_CHPRIS_CH2PRIS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH2PRIS_DEFAULT                      (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH3PRIS                              (0x1UL << 3)                       /**< Channel 3 High Priority Set */
+#define _DMA_CHPRIS_CH3PRIS_SHIFT                       3                                  /**< Shift value for DMA_CH3PRIS */
+#define _DMA_CHPRIS_CH3PRIS_MASK                        0x8UL                              /**< Bit mask for DMA_CH3PRIS */
+#define _DMA_CHPRIS_CH3PRIS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH3PRIS_DEFAULT                      (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH4PRIS                              (0x1UL << 4)                       /**< Channel 4 High Priority Set */
+#define _DMA_CHPRIS_CH4PRIS_SHIFT                       4                                  /**< Shift value for DMA_CH4PRIS */
+#define _DMA_CHPRIS_CH4PRIS_MASK                        0x10UL                             /**< Bit mask for DMA_CH4PRIS */
+#define _DMA_CHPRIS_CH4PRIS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH4PRIS_DEFAULT                      (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH5PRIS                              (0x1UL << 5)                       /**< Channel 5 High Priority Set */
+#define _DMA_CHPRIS_CH5PRIS_SHIFT                       5                                  /**< Shift value for DMA_CH5PRIS */
+#define _DMA_CHPRIS_CH5PRIS_MASK                        0x20UL                             /**< Bit mask for DMA_CH5PRIS */
+#define _DMA_CHPRIS_CH5PRIS_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIS */
+#define DMA_CHPRIS_CH5PRIS_DEFAULT                      (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */
+
+/* Bit fields for DMA CHPRIC */
+#define _DMA_CHPRIC_RESETVALUE                          0x00000000UL                       /**< Default value for DMA_CHPRIC */
+#define _DMA_CHPRIC_MASK                                0x0000003FUL                       /**< Mask for DMA_CHPRIC */
+#define DMA_CHPRIC_CH0PRIC                              (0x1UL << 0)                       /**< Channel 0 High Priority Clear */
+#define _DMA_CHPRIC_CH0PRIC_SHIFT                       0                                  /**< Shift value for DMA_CH0PRIC */
+#define _DMA_CHPRIC_CH0PRIC_MASK                        0x1UL                              /**< Bit mask for DMA_CH0PRIC */
+#define _DMA_CHPRIC_CH0PRIC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH0PRIC_DEFAULT                      (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH1PRIC                              (0x1UL << 1)                       /**< Channel 1 High Priority Clear */
+#define _DMA_CHPRIC_CH1PRIC_SHIFT                       1                                  /**< Shift value for DMA_CH1PRIC */
+#define _DMA_CHPRIC_CH1PRIC_MASK                        0x2UL                              /**< Bit mask for DMA_CH1PRIC */
+#define _DMA_CHPRIC_CH1PRIC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH1PRIC_DEFAULT                      (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH2PRIC                              (0x1UL << 2)                       /**< Channel 2 High Priority Clear */
+#define _DMA_CHPRIC_CH2PRIC_SHIFT                       2                                  /**< Shift value for DMA_CH2PRIC */
+#define _DMA_CHPRIC_CH2PRIC_MASK                        0x4UL                              /**< Bit mask for DMA_CH2PRIC */
+#define _DMA_CHPRIC_CH2PRIC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH2PRIC_DEFAULT                      (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH3PRIC                              (0x1UL << 3)                       /**< Channel 3 High Priority Clear */
+#define _DMA_CHPRIC_CH3PRIC_SHIFT                       3                                  /**< Shift value for DMA_CH3PRIC */
+#define _DMA_CHPRIC_CH3PRIC_MASK                        0x8UL                              /**< Bit mask for DMA_CH3PRIC */
+#define _DMA_CHPRIC_CH3PRIC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH3PRIC_DEFAULT                      (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH4PRIC                              (0x1UL << 4)                       /**< Channel 4 High Priority Clear */
+#define _DMA_CHPRIC_CH4PRIC_SHIFT                       4                                  /**< Shift value for DMA_CH4PRIC */
+#define _DMA_CHPRIC_CH4PRIC_MASK                        0x10UL                             /**< Bit mask for DMA_CH4PRIC */
+#define _DMA_CHPRIC_CH4PRIC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH4PRIC_DEFAULT                      (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH5PRIC                              (0x1UL << 5)                       /**< Channel 5 High Priority Clear */
+#define _DMA_CHPRIC_CH5PRIC_SHIFT                       5                                  /**< Shift value for DMA_CH5PRIC */
+#define _DMA_CHPRIC_CH5PRIC_MASK                        0x20UL                             /**< Bit mask for DMA_CH5PRIC */
+#define _DMA_CHPRIC_CH5PRIC_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for DMA_CHPRIC */
+#define DMA_CHPRIC_CH5PRIC_DEFAULT                      (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */
+
+/* Bit fields for DMA ERRORC */
+#define _DMA_ERRORC_RESETVALUE                          0x00000000UL                      /**< Default value for DMA_ERRORC */
+#define _DMA_ERRORC_MASK                                0x00000001UL                      /**< Mask for DMA_ERRORC */
+#define DMA_ERRORC_ERRORC                               (0x1UL << 0)                      /**< Bus Error Clear */
+#define _DMA_ERRORC_ERRORC_SHIFT                        0                                 /**< Shift value for DMA_ERRORC */
+#define _DMA_ERRORC_ERRORC_MASK                         0x1UL                             /**< Bit mask for DMA_ERRORC */
+#define _DMA_ERRORC_ERRORC_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for DMA_ERRORC */
+#define DMA_ERRORC_ERRORC_DEFAULT                       (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */
+
+/* Bit fields for DMA CHREQSTATUS */
+#define _DMA_CHREQSTATUS_RESETVALUE                     0x00000000UL                                 /**< Default value for DMA_CHREQSTATUS */
+#define _DMA_CHREQSTATUS_MASK                           0x0000003FUL                                 /**< Mask for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH0REQSTATUS                    (0x1UL << 0)                                 /**< Channel 0 Request Status */
+#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT             0                                            /**< Shift value for DMA_CH0REQSTATUS */
+#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK              0x1UL                                        /**< Bit mask for DMA_CH0REQSTATUS */
+#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH1REQSTATUS                    (0x1UL << 1)                                 /**< Channel 1 Request Status */
+#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT             1                                            /**< Shift value for DMA_CH1REQSTATUS */
+#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK              0x2UL                                        /**< Bit mask for DMA_CH1REQSTATUS */
+#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH2REQSTATUS                    (0x1UL << 2)                                 /**< Channel 2 Request Status */
+#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT             2                                            /**< Shift value for DMA_CH2REQSTATUS */
+#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK              0x4UL                                        /**< Bit mask for DMA_CH2REQSTATUS */
+#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH3REQSTATUS                    (0x1UL << 3)                                 /**< Channel 3 Request Status */
+#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT             3                                            /**< Shift value for DMA_CH3REQSTATUS */
+#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK              0x8UL                                        /**< Bit mask for DMA_CH3REQSTATUS */
+#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH4REQSTATUS                    (0x1UL << 4)                                 /**< Channel 4 Request Status */
+#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT             4                                            /**< Shift value for DMA_CH4REQSTATUS */
+#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK              0x10UL                                       /**< Bit mask for DMA_CH4REQSTATUS */
+#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH5REQSTATUS                    (0x1UL << 5)                                 /**< Channel 5 Request Status */
+#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT             5                                            /**< Shift value for DMA_CH5REQSTATUS */
+#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK              0x20UL                                       /**< Bit mask for DMA_CH5REQSTATUS */
+#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for DMA_CHREQSTATUS */
+#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
+
+/* Bit fields for DMA CHSREQSTATUS */
+#define _DMA_CHSREQSTATUS_RESETVALUE                    0x00000000UL                                   /**< Default value for DMA_CHSREQSTATUS */
+#define _DMA_CHSREQSTATUS_MASK                          0x0000003FUL                                   /**< Mask for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH0SREQSTATUS                  (0x1UL << 0)                                   /**< Channel 0 Single Request Status */
+#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT           0                                              /**< Shift value for DMA_CH0SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK            0x1UL                                          /**< Bit mask for DMA_CH0SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT         0x00000000UL                                   /**< Mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH1SREQSTATUS                  (0x1UL << 1)                                   /**< Channel 1 Single Request Status */
+#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT           1                                              /**< Shift value for DMA_CH1SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK            0x2UL                                          /**< Bit mask for DMA_CH1SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT         0x00000000UL                                   /**< Mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH2SREQSTATUS                  (0x1UL << 2)                                   /**< Channel 2 Single Request Status */
+#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT           2                                              /**< Shift value for DMA_CH2SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK            0x4UL                                          /**< Bit mask for DMA_CH2SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT         0x00000000UL                                   /**< Mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH3SREQSTATUS                  (0x1UL << 3)                                   /**< Channel 3 Single Request Status */
+#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT           3                                              /**< Shift value for DMA_CH3SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK            0x8UL                                          /**< Bit mask for DMA_CH3SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT         0x00000000UL                                   /**< Mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH4SREQSTATUS                  (0x1UL << 4)                                   /**< Channel 4 Single Request Status */
+#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT           4                                              /**< Shift value for DMA_CH4SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK            0x10UL                                         /**< Bit mask for DMA_CH4SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT         0x00000000UL                                   /**< Mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH5SREQSTATUS                  (0x1UL << 5)                                   /**< Channel 5 Single Request Status */
+#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT           5                                              /**< Shift value for DMA_CH5SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK            0x20UL                                         /**< Bit mask for DMA_CH5SREQSTATUS */
+#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT         0x00000000UL                                   /**< Mode DEFAULT for DMA_CHSREQSTATUS */
+#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
+
+/* Bit fields for DMA IF */
+#define _DMA_IF_RESETVALUE                              0x00000000UL                   /**< Default value for DMA_IF */
+#define _DMA_IF_MASK                                    0x8000003FUL                   /**< Mask for DMA_IF */
+#define DMA_IF_CH0DONE                                  (0x1UL << 0)                   /**< DMA Channel 0 Complete Interrupt Flag */
+#define _DMA_IF_CH0DONE_SHIFT                           0                              /**< Shift value for DMA_CH0DONE */
+#define _DMA_IF_CH0DONE_MASK                            0x1UL                          /**< Bit mask for DMA_CH0DONE */
+#define _DMA_IF_CH0DONE_DEFAULT                         0x00000000UL                   /**< Mode DEFAULT for DMA_IF */
+#define DMA_IF_CH0DONE_DEFAULT                          (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */
+#define DMA_IF_CH1DONE                                  (0x1UL << 1)                   /**< DMA Channel 1 Complete Interrupt Flag */
+#define _DMA_IF_CH1DONE_SHIFT                           1                              /**< Shift value for DMA_CH1DONE */
+#define _DMA_IF_CH1DONE_MASK                            0x2UL                          /**< Bit mask for DMA_CH1DONE */
+#define _DMA_IF_CH1DONE_DEFAULT                         0x00000000UL                   /**< Mode DEFAULT for DMA_IF */
+#define DMA_IF_CH1DONE_DEFAULT                          (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */
+#define DMA_IF_CH2DONE                                  (0x1UL << 2)                   /**< DMA Channel 2 Complete Interrupt Flag */
+#define _DMA_IF_CH2DONE_SHIFT                           2                              /**< Shift value for DMA_CH2DONE */
+#define _DMA_IF_CH2DONE_MASK                            0x4UL                          /**< Bit mask for DMA_CH2DONE */
+#define _DMA_IF_CH2DONE_DEFAULT                         0x00000000UL                   /**< Mode DEFAULT for DMA_IF */
+#define DMA_IF_CH2DONE_DEFAULT                          (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */
+#define DMA_IF_CH3DONE                                  (0x1UL << 3)                   /**< DMA Channel 3 Complete Interrupt Flag */
+#define _DMA_IF_CH3DONE_SHIFT                           3                              /**< Shift value for DMA_CH3DONE */
+#define _DMA_IF_CH3DONE_MASK                            0x8UL                          /**< Bit mask for DMA_CH3DONE */
+#define _DMA_IF_CH3DONE_DEFAULT                         0x00000000UL                   /**< Mode DEFAULT for DMA_IF */
+#define DMA_IF_CH3DONE_DEFAULT                          (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */
+#define DMA_IF_CH4DONE                                  (0x1UL << 4)                   /**< DMA Channel 4 Complete Interrupt Flag */
+#define _DMA_IF_CH4DONE_SHIFT                           4                              /**< Shift value for DMA_CH4DONE */
+#define _DMA_IF_CH4DONE_MASK                            0x10UL                         /**< Bit mask for DMA_CH4DONE */
+#define _DMA_IF_CH4DONE_DEFAULT                         0x00000000UL                   /**< Mode DEFAULT for DMA_IF */
+#define DMA_IF_CH4DONE_DEFAULT                          (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */
+#define DMA_IF_CH5DONE                                  (0x1UL << 5)                   /**< DMA Channel 5 Complete Interrupt Flag */
+#define _DMA_IF_CH5DONE_SHIFT                           5                              /**< Shift value for DMA_CH5DONE */
+#define _DMA_IF_CH5DONE_MASK                            0x20UL                         /**< Bit mask for DMA_CH5DONE */
+#define _DMA_IF_CH5DONE_DEFAULT                         0x00000000UL                   /**< Mode DEFAULT for DMA_IF */
+#define DMA_IF_CH5DONE_DEFAULT                          (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */
+#define DMA_IF_ERR                                      (0x1UL << 31)                  /**< DMA Error Interrupt Flag */
+#define _DMA_IF_ERR_SHIFT                               31                             /**< Shift value for DMA_ERR */
+#define _DMA_IF_ERR_MASK                                0x80000000UL                   /**< Bit mask for DMA_ERR */
+#define _DMA_IF_ERR_DEFAULT                             0x00000000UL                   /**< Mode DEFAULT for DMA_IF */
+#define DMA_IF_ERR_DEFAULT                              (_DMA_IF_ERR_DEFAULT << 31)    /**< Shifted mode DEFAULT for DMA_IF */
+
+/* Bit fields for DMA IFS */
+#define _DMA_IFS_RESETVALUE                             0x00000000UL                    /**< Default value for DMA_IFS */
+#define _DMA_IFS_MASK                                   0x8000003FUL                    /**< Mask for DMA_IFS */
+#define DMA_IFS_CH0DONE                                 (0x1UL << 0)                    /**< DMA Channel 0 Complete Interrupt Flag Set */
+#define _DMA_IFS_CH0DONE_SHIFT                          0                               /**< Shift value for DMA_CH0DONE */
+#define _DMA_IFS_CH0DONE_MASK                           0x1UL                           /**< Bit mask for DMA_CH0DONE */
+#define _DMA_IFS_CH0DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH0DONE_DEFAULT                         (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH1DONE                                 (0x1UL << 1)                    /**< DMA Channel 1 Complete Interrupt Flag Set */
+#define _DMA_IFS_CH1DONE_SHIFT                          1                               /**< Shift value for DMA_CH1DONE */
+#define _DMA_IFS_CH1DONE_MASK                           0x2UL                           /**< Bit mask for DMA_CH1DONE */
+#define _DMA_IFS_CH1DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH1DONE_DEFAULT                         (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH2DONE                                 (0x1UL << 2)                    /**< DMA Channel 2 Complete Interrupt Flag Set */
+#define _DMA_IFS_CH2DONE_SHIFT                          2                               /**< Shift value for DMA_CH2DONE */
+#define _DMA_IFS_CH2DONE_MASK                           0x4UL                           /**< Bit mask for DMA_CH2DONE */
+#define _DMA_IFS_CH2DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH2DONE_DEFAULT                         (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH3DONE                                 (0x1UL << 3)                    /**< DMA Channel 3 Complete Interrupt Flag Set */
+#define _DMA_IFS_CH3DONE_SHIFT                          3                               /**< Shift value for DMA_CH3DONE */
+#define _DMA_IFS_CH3DONE_MASK                           0x8UL                           /**< Bit mask for DMA_CH3DONE */
+#define _DMA_IFS_CH3DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH3DONE_DEFAULT                         (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH4DONE                                 (0x1UL << 4)                    /**< DMA Channel 4 Complete Interrupt Flag Set */
+#define _DMA_IFS_CH4DONE_SHIFT                          4                               /**< Shift value for DMA_CH4DONE */
+#define _DMA_IFS_CH4DONE_MASK                           0x10UL                          /**< Bit mask for DMA_CH4DONE */
+#define _DMA_IFS_CH4DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH4DONE_DEFAULT                         (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH5DONE                                 (0x1UL << 5)                    /**< DMA Channel 5 Complete Interrupt Flag Set */
+#define _DMA_IFS_CH5DONE_SHIFT                          5                               /**< Shift value for DMA_CH5DONE */
+#define _DMA_IFS_CH5DONE_MASK                           0x20UL                          /**< Bit mask for DMA_CH5DONE */
+#define _DMA_IFS_CH5DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFS */
+#define DMA_IFS_CH5DONE_DEFAULT                         (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */
+#define DMA_IFS_ERR                                     (0x1UL << 31)                   /**< DMA Error Interrupt Flag Set */
+#define _DMA_IFS_ERR_SHIFT                              31                              /**< Shift value for DMA_ERR */
+#define _DMA_IFS_ERR_MASK                               0x80000000UL                    /**< Bit mask for DMA_ERR */
+#define _DMA_IFS_ERR_DEFAULT                            0x00000000UL                    /**< Mode DEFAULT for DMA_IFS */
+#define DMA_IFS_ERR_DEFAULT                             (_DMA_IFS_ERR_DEFAULT << 31)    /**< Shifted mode DEFAULT for DMA_IFS */
+
+/* Bit fields for DMA IFC */
+#define _DMA_IFC_RESETVALUE                             0x00000000UL                    /**< Default value for DMA_IFC */
+#define _DMA_IFC_MASK                                   0x8000003FUL                    /**< Mask for DMA_IFC */
+#define DMA_IFC_CH0DONE                                 (0x1UL << 0)                    /**< DMA Channel 0 Complete Interrupt Flag Clear */
+#define _DMA_IFC_CH0DONE_SHIFT                          0                               /**< Shift value for DMA_CH0DONE */
+#define _DMA_IFC_CH0DONE_MASK                           0x1UL                           /**< Bit mask for DMA_CH0DONE */
+#define _DMA_IFC_CH0DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH0DONE_DEFAULT                         (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH1DONE                                 (0x1UL << 1)                    /**< DMA Channel 1 Complete Interrupt Flag Clear */
+#define _DMA_IFC_CH1DONE_SHIFT                          1                               /**< Shift value for DMA_CH1DONE */
+#define _DMA_IFC_CH1DONE_MASK                           0x2UL                           /**< Bit mask for DMA_CH1DONE */
+#define _DMA_IFC_CH1DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH1DONE_DEFAULT                         (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH2DONE                                 (0x1UL << 2)                    /**< DMA Channel 2 Complete Interrupt Flag Clear */
+#define _DMA_IFC_CH2DONE_SHIFT                          2                               /**< Shift value for DMA_CH2DONE */
+#define _DMA_IFC_CH2DONE_MASK                           0x4UL                           /**< Bit mask for DMA_CH2DONE */
+#define _DMA_IFC_CH2DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH2DONE_DEFAULT                         (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH3DONE                                 (0x1UL << 3)                    /**< DMA Channel 3 Complete Interrupt Flag Clear */
+#define _DMA_IFC_CH3DONE_SHIFT                          3                               /**< Shift value for DMA_CH3DONE */
+#define _DMA_IFC_CH3DONE_MASK                           0x8UL                           /**< Bit mask for DMA_CH3DONE */
+#define _DMA_IFC_CH3DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH3DONE_DEFAULT                         (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH4DONE                                 (0x1UL << 4)                    /**< DMA Channel 4 Complete Interrupt Flag Clear */
+#define _DMA_IFC_CH4DONE_SHIFT                          4                               /**< Shift value for DMA_CH4DONE */
+#define _DMA_IFC_CH4DONE_MASK                           0x10UL                          /**< Bit mask for DMA_CH4DONE */
+#define _DMA_IFC_CH4DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH4DONE_DEFAULT                         (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH5DONE                                 (0x1UL << 5)                    /**< DMA Channel 5 Complete Interrupt Flag Clear */
+#define _DMA_IFC_CH5DONE_SHIFT                          5                               /**< Shift value for DMA_CH5DONE */
+#define _DMA_IFC_CH5DONE_MASK                           0x20UL                          /**< Bit mask for DMA_CH5DONE */
+#define _DMA_IFC_CH5DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IFC */
+#define DMA_IFC_CH5DONE_DEFAULT                         (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */
+#define DMA_IFC_ERR                                     (0x1UL << 31)                   /**< DMA Error Interrupt Flag Clear */
+#define _DMA_IFC_ERR_SHIFT                              31                              /**< Shift value for DMA_ERR */
+#define _DMA_IFC_ERR_MASK                               0x80000000UL                    /**< Bit mask for DMA_ERR */
+#define _DMA_IFC_ERR_DEFAULT                            0x00000000UL                    /**< Mode DEFAULT for DMA_IFC */
+#define DMA_IFC_ERR_DEFAULT                             (_DMA_IFC_ERR_DEFAULT << 31)    /**< Shifted mode DEFAULT for DMA_IFC */
+
+/* Bit fields for DMA IEN */
+#define _DMA_IEN_RESETVALUE                             0x00000000UL                    /**< Default value for DMA_IEN */
+#define _DMA_IEN_MASK                                   0x8000003FUL                    /**< Mask for DMA_IEN */
+#define DMA_IEN_CH0DONE                                 (0x1UL << 0)                    /**< DMA Channel 0 Complete Interrupt Enable */
+#define _DMA_IEN_CH0DONE_SHIFT                          0                               /**< Shift value for DMA_CH0DONE */
+#define _DMA_IEN_CH0DONE_MASK                           0x1UL                           /**< Bit mask for DMA_CH0DONE */
+#define _DMA_IEN_CH0DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH0DONE_DEFAULT                         (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH1DONE                                 (0x1UL << 1)                    /**< DMA Channel 1 Complete Interrupt Enable */
+#define _DMA_IEN_CH1DONE_SHIFT                          1                               /**< Shift value for DMA_CH1DONE */
+#define _DMA_IEN_CH1DONE_MASK                           0x2UL                           /**< Bit mask for DMA_CH1DONE */
+#define _DMA_IEN_CH1DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH1DONE_DEFAULT                         (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH2DONE                                 (0x1UL << 2)                    /**< DMA Channel 2 Complete Interrupt Enable */
+#define _DMA_IEN_CH2DONE_SHIFT                          2                               /**< Shift value for DMA_CH2DONE */
+#define _DMA_IEN_CH2DONE_MASK                           0x4UL                           /**< Bit mask for DMA_CH2DONE */
+#define _DMA_IEN_CH2DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH2DONE_DEFAULT                         (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH3DONE                                 (0x1UL << 3)                    /**< DMA Channel 3 Complete Interrupt Enable */
+#define _DMA_IEN_CH3DONE_SHIFT                          3                               /**< Shift value for DMA_CH3DONE */
+#define _DMA_IEN_CH3DONE_MASK                           0x8UL                           /**< Bit mask for DMA_CH3DONE */
+#define _DMA_IEN_CH3DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH3DONE_DEFAULT                         (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH4DONE                                 (0x1UL << 4)                    /**< DMA Channel 4 Complete Interrupt Enable */
+#define _DMA_IEN_CH4DONE_SHIFT                          4                               /**< Shift value for DMA_CH4DONE */
+#define _DMA_IEN_CH4DONE_MASK                           0x10UL                          /**< Bit mask for DMA_CH4DONE */
+#define _DMA_IEN_CH4DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH4DONE_DEFAULT                         (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH5DONE                                 (0x1UL << 5)                    /**< DMA Channel 5 Complete Interrupt Enable */
+#define _DMA_IEN_CH5DONE_SHIFT                          5                               /**< Shift value for DMA_CH5DONE */
+#define _DMA_IEN_CH5DONE_MASK                           0x20UL                          /**< Bit mask for DMA_CH5DONE */
+#define _DMA_IEN_CH5DONE_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for DMA_IEN */
+#define DMA_IEN_CH5DONE_DEFAULT                         (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */
+#define DMA_IEN_ERR                                     (0x1UL << 31)                   /**< DMA Error Interrupt Flag Enable */
+#define _DMA_IEN_ERR_SHIFT                              31                              /**< Shift value for DMA_ERR */
+#define _DMA_IEN_ERR_MASK                               0x80000000UL                    /**< Bit mask for DMA_ERR */
+#define _DMA_IEN_ERR_DEFAULT                            0x00000000UL                    /**< Mode DEFAULT for DMA_IEN */
+#define DMA_IEN_ERR_DEFAULT                             (_DMA_IEN_ERR_DEFAULT << 31)    /**< Shifted mode DEFAULT for DMA_IEN */
+
+/* Bit fields for DMA CH_CTRL */
+#define _DMA_CH_CTRL_RESETVALUE                         0x00000000UL                                  /**< Default value for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_MASK                               0x003F000FUL                                  /**< Mask for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_SHIFT                       0                                             /**< Shift value for DMA_SIGSEL */
+#define _DMA_CH_CTRL_SIGSEL_MASK                        0xFUL                                         /**< Bit mask for DMA_SIGSEL */
+#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE                  0x00000000UL                                  /**< Mode ADC0SINGLE for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV               0x00000000UL                                  /**< Mode USART0RXDATAV for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV               0x00000000UL                                  /**< Mode USART1RXDATAV for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV              0x00000000UL                                  /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                 0x00000000UL                                  /**< Mode I2C0RXDATAV for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF                  0x00000000UL                                  /**< Mode TIMER0UFOF for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF                  0x00000000UL                                  /**< Mode TIMER1UFOF for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF                  0x00000000UL                                  /**< Mode TIMER2UFOF for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_MSCWDATA                    0x00000000UL                                  /**< Mode MSCWDATA for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_AESDATAWR                   0x00000000UL                                  /**< Mode AESDATAWR for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN                    0x00000001UL                                  /**< Mode ADC0SCAN for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_USART0TXBL                  0x00000001UL                                  /**< Mode USART0TXBL for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_USART1TXBL                  0x00000001UL                                  /**< Mode USART1TXBL for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL                 0x00000001UL                                  /**< Mode LEUART0TXBL for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL                    0x00000001UL                                  /**< Mode I2C0TXBL for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0                   0x00000001UL                                  /**< Mode TIMER0CC0 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0                   0x00000001UL                                  /**< Mode TIMER1CC0 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0                   0x00000001UL                                  /**< Mode TIMER2CC0 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR                0x00000001UL                                  /**< Mode AESXORDATAWR for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY               0x00000002UL                                  /**< Mode USART0TXEMPTY for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY               0x00000002UL                                  /**< Mode USART1TXEMPTY for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY              0x00000002UL                                  /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1                   0x00000002UL                                  /**< Mode TIMER0CC1 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1                   0x00000002UL                                  /**< Mode TIMER1CC1 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1                   0x00000002UL                                  /**< Mode TIMER2CC1 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_AESDATARD                   0x00000002UL                                  /**< Mode AESDATARD for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT          0x00000003UL                                  /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2                   0x00000003UL                                  /**< Mode TIMER0CC2 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2                   0x00000003UL                                  /**< Mode TIMER1CC2 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2                   0x00000003UL                                  /**< Mode TIMER2CC2 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_AESKEYWR                    0x00000003UL                                  /**< Mode AESKEYWR for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT             0x00000004UL                                  /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE                   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)         /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)      /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)      /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV               (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)     /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                  (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)        /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)         /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)         /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)         /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_MSCWDATA                     (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)           /**< Shifted mode MSCWDATA for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_AESDATAWR                    (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)          /**< Shifted mode AESDATAWR for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_ADC0SCAN                     (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)           /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_USART0TXBL                   (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)         /**< Shifted mode USART0TXBL for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_USART1TXBL                   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)         /**< Shifted mode USART1TXBL for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL                  (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)        /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_I2C0TXBL                     (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)           /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER0CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)          /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER1CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)          /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER2CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)          /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR                 (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)       /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)      /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)      /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY               (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)     /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER0CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)          /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER1CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)          /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER2CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)          /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_AESDATARD                    (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)          /**< Shifted mode AESDATARD for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT           (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER0CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)          /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER1CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)          /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_TIMER2CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)          /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_AESKEYWR                     (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)           /**< Shifted mode AESKEYWR for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT              (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)    /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_SHIFT                    16                                            /**< Shift value for DMA_SOURCESEL */
+#define _DMA_CH_CTRL_SOURCESEL_MASK                     0x3F0000UL                                    /**< Bit mask for DMA_SOURCESEL */
+#define _DMA_CH_CTRL_SOURCESEL_NONE                     0x00000000UL                                  /**< Mode NONE for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_ADC0                     0x00000008UL                                  /**< Mode ADC0 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_USART0                   0x0000000CUL                                  /**< Mode USART0 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_USART1                   0x0000000DUL                                  /**< Mode USART1 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_LEUART0                  0x00000010UL                                  /**< Mode LEUART0 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_I2C0                     0x00000014UL                                  /**< Mode I2C0 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_TIMER0                   0x00000018UL                                  /**< Mode TIMER0 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_TIMER1                   0x00000019UL                                  /**< Mode TIMER1 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_TIMER2                   0x0000001AUL                                  /**< Mode TIMER2 for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_MSC                      0x00000030UL                                  /**< Mode MSC for DMA_CH_CTRL */
+#define _DMA_CH_CTRL_SOURCESEL_AES                      0x00000031UL                                  /**< Mode AES for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_NONE                      (_DMA_CH_CTRL_SOURCESEL_NONE << 16)           /**< Shifted mode NONE for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_ADC0                      (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)           /**< Shifted mode ADC0 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_USART0                    (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)         /**< Shifted mode USART0 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_USART1                    (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)         /**< Shifted mode USART1 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_LEUART0                   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)        /**< Shifted mode LEUART0 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_I2C0                      (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)           /**< Shifted mode I2C0 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_TIMER0                    (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)         /**< Shifted mode TIMER0 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_TIMER1                    (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)         /**< Shifted mode TIMER1 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_TIMER2                    (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)         /**< Shifted mode TIMER2 for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_MSC                       (_DMA_CH_CTRL_SOURCESEL_MSC << 16)            /**< Shifted mode MSC for DMA_CH_CTRL */
+#define DMA_CH_CTRL_SOURCESEL_AES                       (_DMA_CH_CTRL_SOURCESEL_AES << 16)            /**< Shifted mode AES for DMA_CH_CTRL */
+
+/** @} End of group EFM32HG_DMA */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_dma_ch.h

@@ -0,0 +1,57 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_DMA_CH register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief DMA_CH EFM32HG DMA CH
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL; /**< Channel Control Register  */
+} DMA_CH_TypeDef;
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_dma_descriptor.h

@@ -0,0 +1,63 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_DMA_DESCRIPTOR register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_DMA_DESCRIPTOR
+ * @{
+ ******************************************************************************/
+typedef struct {
+  /* Note! Use of double __IOM (volatile) qualifier to ensure that both */
+  /* pointer and referenced memory are declared volatile. */
+  __IOM void * __IOM SRCEND;   /**< DMA source address end */
+  __IOM void * __IOM DSTEND;   /**< DMA destination address end */
+  __IOM uint32_t     CTRL;     /**< DMA control register */
+  __IOM uint32_t     USER;     /**< DMA padding register, available for user */
+} DMA_DESCRIPTOR_TypeDef;      /** @} */
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_dmactrl.h

@@ -0,0 +1,153 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_DMACTRL register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_DMACTRL_BitFields
+ * @{
+ ******************************************************************************/
+#define _DMA_CTRL_DST_INC_MASK                         0xC0000000UL  /**< Data increment for destination, bit mask */
+#define _DMA_CTRL_DST_INC_SHIFT                        30            /**< Data increment for destination, shift value */
+#define _DMA_CTRL_DST_INC_BYTE                         0x00          /**< Byte/8-bit increment */
+#define _DMA_CTRL_DST_INC_HALFWORD                     0x01          /**< Half word/16-bit increment */
+#define _DMA_CTRL_DST_INC_WORD                         0x02          /**< Word/32-bit increment */
+#define _DMA_CTRL_DST_INC_NONE                         0x03          /**< No increment */
+#define DMA_CTRL_DST_INC_BYTE                          0x00000000UL  /**< Byte/8-bit increment */
+#define DMA_CTRL_DST_INC_HALFWORD                      0x40000000UL  /**< Half word/16-bit increment */
+#define DMA_CTRL_DST_INC_WORD                          0x80000000UL  /**< Word/32-bit increment */
+#define DMA_CTRL_DST_INC_NONE                          0xC0000000UL  /**< No increment */
+#define _DMA_CTRL_DST_SIZE_MASK                        0x30000000UL  /**< Data size for destination - MUST be the same as source, bit mask */
+#define _DMA_CTRL_DST_SIZE_SHIFT                       28            /**< Data size for destination - MUST be the same as source, shift value */
+#define _DMA_CTRL_DST_SIZE_BYTE                        0x00          /**< Byte/8-bit data size */
+#define _DMA_CTRL_DST_SIZE_HALFWORD                    0x01          /**< Half word/16-bit data size */
+#define _DMA_CTRL_DST_SIZE_WORD                        0x02          /**< Word/32-bit data size */
+#define _DMA_CTRL_DST_SIZE_RSVD                        0x03          /**< Reserved */
+#define DMA_CTRL_DST_SIZE_BYTE                         0x00000000UL  /**< Byte/8-bit data size */
+#define DMA_CTRL_DST_SIZE_HALFWORD                     0x10000000UL  /**< Half word/16-bit data size */
+#define DMA_CTRL_DST_SIZE_WORD                         0x20000000UL  /**< Word/32-bit data size */
+#define DMA_CTRL_DST_SIZE_RSVD                         0x30000000UL  /**< Reserved - do not use */
+#define _DMA_CTRL_SRC_INC_MASK                         0x0C000000UL  /**< Data increment for source, bit mask */
+#define _DMA_CTRL_SRC_INC_SHIFT                        26            /**< Data increment for source, shift value */
+#define _DMA_CTRL_SRC_INC_BYTE                         0x00          /**< Byte/8-bit increment */
+#define _DMA_CTRL_SRC_INC_HALFWORD                     0x01          /**< Half word/16-bit increment */
+#define _DMA_CTRL_SRC_INC_WORD                         0x02          /**< Word/32-bit increment */
+#define _DMA_CTRL_SRC_INC_NONE                         0x03          /**< No increment */
+#define DMA_CTRL_SRC_INC_BYTE                          0x00000000UL  /**< Byte/8-bit increment */
+#define DMA_CTRL_SRC_INC_HALFWORD                      0x04000000UL  /**< Half word/16-bit increment */
+#define DMA_CTRL_SRC_INC_WORD                          0x08000000UL  /**< Word/32-bit increment */
+#define DMA_CTRL_SRC_INC_NONE                          0x0C000000UL  /**< No increment */
+#define _DMA_CTRL_SRC_SIZE_MASK                        0x03000000UL  /**< Data size for source - MUST be the same as destination, bit mask */
+#define _DMA_CTRL_SRC_SIZE_SHIFT                       24            /**< Data size for source - MUST be the same as destination, shift value */
+#define _DMA_CTRL_SRC_SIZE_BYTE                        0x00          /**< Byte/8-bit data size */
+#define _DMA_CTRL_SRC_SIZE_HALFWORD                    0x01          /**< Half word/16-bit data size */
+#define _DMA_CTRL_SRC_SIZE_WORD                        0x02          /**< Word/32-bit data size */
+#define _DMA_CTRL_SRC_SIZE_RSVD                        0x03          /**< Reserved */
+#define DMA_CTRL_SRC_SIZE_BYTE                         0x00000000UL  /**< Byte/8-bit data size */
+#define DMA_CTRL_SRC_SIZE_HALFWORD                     0x01000000UL  /**< Half word/16-bit data size */
+#define DMA_CTRL_SRC_SIZE_WORD                         0x02000000UL  /**< Word/32-bit data size */
+#define DMA_CTRL_SRC_SIZE_RSVD                         0x03000000UL  /**< Reserved - do not use */
+#define _DMA_CTRL_DST_PROT_CTRL_MASK                   0x00E00000UL  /**< Protection flag for destination, bit mask */
+#define _DMA_CTRL_DST_PROT_CTRL_SHIFT                  21            /**< Protection flag for destination, shift value */
+#define DMA_CTRL_DST_PROT_PRIVILEGED                   0x00200000UL  /**< Privileged mode for destination */
+#define DMA_CTRL_DST_PROT_NON_PRIVILEGED               0x00000000UL  /**< Non-privileged mode for estination */
+#define _DMA_CTRL_SRC_PROT_CTRL_MASK                   0x001C0000UL  /**< Protection flag for source, bit mask */
+#define _DMA_CTRL_SRC_PROT_CTRL_SHIFT                  18            /**< Protection flag for source, shift value */
+#define DMA_CTRL_SRC_PROT_PRIVILEGED                   0x00040000UL  /**< Privileged mode for destination */
+#define DMA_CTRL_SRC_PROT_NON_PRIVILEGED               0x00000000UL  /**< Non-privileged mode for estination */
+#define _DMA_CTRL_PROT_NON_PRIVILEGED                  0x00          /**< Protection bits to indicate non-privileged access */
+#define _DMA_CTRL_PROT_PRIVILEGED                      0x01          /**< Protection bits to indicate privileged access */
+#define _DMA_CTRL_R_POWER_MASK                         0x0003C000UL  /**< DMA arbitration mask */
+#define _DMA_CTRL_R_POWER_SHIFT                        14            /**< Number of DMA cycles before controller does new arbitration in 2^R */
+#define _DMA_CTRL_R_POWER_1                            0x00          /**< Arbitrate after each transfer */
+#define _DMA_CTRL_R_POWER_2                            0x01          /**< Arbitrate after every 2 transfers */
+#define _DMA_CTRL_R_POWER_4                            0x02          /**< Arbitrate after every 4 transfers */
+#define _DMA_CTRL_R_POWER_8                            0x03          /**< Arbitrate after every 8 transfers */
+#define _DMA_CTRL_R_POWER_16                           0x04          /**< Arbitrate after every 16 transfers */
+#define _DMA_CTRL_R_POWER_32                           0x05          /**< Arbitrate after every 32 transfers */
+#define _DMA_CTRL_R_POWER_64                           0x06          /**< Arbitrate after every 64 transfers */
+#define _DMA_CTRL_R_POWER_128                          0x07          /**< Arbitrate after every 128 transfers */
+#define _DMA_CTRL_R_POWER_256                          0x08          /**< Arbitrate after every 256 transfers */
+#define _DMA_CTRL_R_POWER_512                          0x09          /**< Arbitrate after every 512 transfers */
+#define _DMA_CTRL_R_POWER_1024                         0x0a          /**< Arbitrate after every 1024 transfers */
+#define DMA_CTRL_R_POWER_1                             0x00000000UL  /**< Arbitrate after each transfer */
+#define DMA_CTRL_R_POWER_2                             0x00004000UL  /**< Arbitrate after every 2 transfers */
+#define DMA_CTRL_R_POWER_4                             0x00008000UL  /**< Arbitrate after every 4 transfers */
+#define DMA_CTRL_R_POWER_8                             0x0000c000UL  /**< Arbitrate after every 8 transfers */
+#define DMA_CTRL_R_POWER_16                            0x00010000UL  /**< Arbitrate after every 16 transfers */
+#define DMA_CTRL_R_POWER_32                            0x00014000UL  /**< Arbitrate after every 32 transfers */
+#define DMA_CTRL_R_POWER_64                            0x00018000UL  /**< Arbitrate after every 64 transfers */
+#define DMA_CTRL_R_POWER_128                           0x0001c000UL  /**< Arbitrate after every 128 transfers */
+#define DMA_CTRL_R_POWER_256                           0x00020000UL  /**< Arbitrate after every 256 transfers */
+#define DMA_CTRL_R_POWER_512                           0x00024000UL  /**< Arbitrate after every 512 transfers */
+#define DMA_CTRL_R_POWER_1024                          0x00028000UL  /**< Arbitrate after every 1024 transfers */
+#define _DMA_CTRL_N_MINUS_1_MASK                       0x00003FF0UL  /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */
+#define _DMA_CTRL_N_MINUS_1_SHIFT                      4             /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */
+#define _DMA_CTRL_NEXT_USEBURST_MASK                   0x00000008UL  /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */
+#define _DMA_CTRL_NEXT_USEBURST_SHIFT                  3             /**< DMA useburst shift */
+#define _DMA_CTRL_CYCLE_CTRL_MASK                      0x00000007UL  /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */
+#define _DMA_CTRL_CYCLE_CTRL_SHIFT                     0             /**< DMA Cycle control bit shift */
+#define _DMA_CTRL_CYCLE_CTRL_INVALID                   0x00          /**< Invalid cycle type  */
+#define _DMA_CTRL_CYCLE_CTRL_BASIC                     0x01          /**< Basic cycle type */
+#define _DMA_CTRL_CYCLE_CTRL_AUTO                      0x02          /**< Auto cycle type */
+#define _DMA_CTRL_CYCLE_CTRL_PINGPONG                  0x03          /**< PingPong cycle type */
+#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER        0x04          /**< Memory scatter gather cycle type */
+#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT    0x05          /**< Memory scatter gather using alternate structure  */
+#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER        0x06          /**< Peripheral scatter gather cycle type */
+#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT    0x07          /**< Peripheral scatter gather cycle type using alternate structure */
+#define DMA_CTRL_CYCLE_CTRL_INVALID                    0x00000000UL  /**< Invalid cycle type */
+#define DMA_CTRL_CYCLE_CTRL_BASIC                      0x00000001UL  /**< Basic cycle type */
+#define DMA_CTRL_CYCLE_CTRL_AUTO                       0x00000002UL  /**< Auto cycle type */
+#define DMA_CTRL_CYCLE_CTRL_PINGPONG                   0x00000003UL  /**< PingPong cycle type */
+#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER         0x000000004UL /**< Memory scatter gather cycle type */
+#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT     0x000000005UL /**< Memory scatter gather using alternate structure  */
+#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER         0x000000006UL /**< Peripheral scatter gather cycle type */
+#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT     0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
+
+/** @} End of group EFM32HG_DMA */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_dmareq.h

@@ -0,0 +1,89 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_DMAREQ register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_DMAREQ_BitFields
+ * @{
+ ******************************************************************************/
+#define DMAREQ_ADC0_SINGLE            ((8 << 16) + 0)  /**< DMA channel select for ADC0_SINGLE */
+#define DMAREQ_ADC0_SCAN              ((8 << 16) + 1)  /**< DMA channel select for ADC0_SCAN */
+#define DMAREQ_USART0_RXDATAV         ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
+#define DMAREQ_USART0_TXBL            ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
+#define DMAREQ_USART0_TXEMPTY         ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
+#define DMAREQ_USART1_RXDATAV         ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
+#define DMAREQ_USART1_TXBL            ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
+#define DMAREQ_USART1_TXEMPTY         ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
+#define DMAREQ_USART1_RXDATAVRIGHT    ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
+#define DMAREQ_USART1_TXBLRIGHT       ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
+#define DMAREQ_LEUART0_RXDATAV        ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
+#define DMAREQ_LEUART0_TXBL           ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
+#define DMAREQ_LEUART0_TXEMPTY        ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
+#define DMAREQ_I2C0_RXDATAV           ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
+#define DMAREQ_I2C0_TXBL              ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
+#define DMAREQ_TIMER0_UFOF            ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
+#define DMAREQ_TIMER0_CC0             ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
+#define DMAREQ_TIMER0_CC1             ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
+#define DMAREQ_TIMER0_CC2             ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
+#define DMAREQ_TIMER1_UFOF            ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
+#define DMAREQ_TIMER1_CC0             ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
+#define DMAREQ_TIMER1_CC1             ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
+#define DMAREQ_TIMER1_CC2             ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
+#define DMAREQ_TIMER2_UFOF            ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
+#define DMAREQ_TIMER2_CC0             ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
+#define DMAREQ_TIMER2_CC1             ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
+#define DMAREQ_TIMER2_CC2             ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
+#define DMAREQ_MSC_WDATA              ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
+#define DMAREQ_AES_DATAWR             ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */
+#define DMAREQ_AES_XORDATAWR          ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */
+#define DMAREQ_AES_DATARD             ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */
+#define DMAREQ_AES_KEYWR              ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
+
+/** @} End of group EFM32HG_DMAREQ */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_emu.h

@@ -0,0 +1,118 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_EMU register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_EMU
+ * @{
+ * @brief EFM32HG_EMU Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;          /**< Control Register  */
+
+  uint32_t       RESERVED0[1U]; /**< Reserved for future use **/
+  __IOM uint32_t LOCK;          /**< Configuration Lock Register  */
+
+  uint32_t       RESERVED1[6U]; /**< Reserved for future use **/
+  __IOM uint32_t AUXCTRL;       /**< Auxiliary Control Register  */
+} EMU_TypeDef;                  /**< EMU Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_EMU_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for EMU CTRL */
+#define _EMU_CTRL_RESETVALUE           0x00000000UL                      /**< Default value for EMU_CTRL */
+#define _EMU_CTRL_MASK                 0x0000000FUL                      /**< Mask for EMU_CTRL */
+#define EMU_CTRL_EMVREG                (0x1UL << 0)                      /**< Energy Mode Voltage Regulator Control */
+#define _EMU_CTRL_EMVREG_SHIFT         0                                 /**< Shift value for EMU_EMVREG */
+#define _EMU_CTRL_EMVREG_MASK          0x1UL                             /**< Bit mask for EMU_EMVREG */
+#define _EMU_CTRL_EMVREG_DEFAULT       0x00000000UL                      /**< Mode DEFAULT for EMU_CTRL */
+#define _EMU_CTRL_EMVREG_REDUCED       0x00000000UL                      /**< Mode REDUCED for EMU_CTRL */
+#define _EMU_CTRL_EMVREG_FULL          0x00000001UL                      /**< Mode FULL for EMU_CTRL */
+#define EMU_CTRL_EMVREG_DEFAULT        (_EMU_CTRL_EMVREG_DEFAULT << 0)   /**< Shifted mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EMVREG_REDUCED        (_EMU_CTRL_EMVREG_REDUCED << 0)   /**< Shifted mode REDUCED for EMU_CTRL */
+#define EMU_CTRL_EMVREG_FULL           (_EMU_CTRL_EMVREG_FULL << 0)      /**< Shifted mode FULL for EMU_CTRL */
+#define EMU_CTRL_EM2BLOCK              (0x1UL << 1)                      /**< Energy Mode 2 Block */
+#define _EMU_CTRL_EM2BLOCK_SHIFT       1                                 /**< Shift value for EMU_EM2BLOCK */
+#define _EMU_CTRL_EM2BLOCK_MASK        0x2UL                             /**< Bit mask for EMU_EM2BLOCK */
+#define _EMU_CTRL_EM2BLOCK_DEFAULT     0x00000000UL                      /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EM2BLOCK_DEFAULT      (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
+#define _EMU_CTRL_EM4CTRL_SHIFT        2                                 /**< Shift value for EMU_EM4CTRL */
+#define _EMU_CTRL_EM4CTRL_MASK         0xCUL                             /**< Bit mask for EMU_EM4CTRL */
+#define _EMU_CTRL_EM4CTRL_DEFAULT      0x00000000UL                      /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EM4CTRL_DEFAULT       (_EMU_CTRL_EM4CTRL_DEFAULT << 2)  /**< Shifted mode DEFAULT for EMU_CTRL */
+
+/* Bit fields for EMU LOCK */
+#define _EMU_LOCK_RESETVALUE           0x00000000UL                      /**< Default value for EMU_LOCK */
+#define _EMU_LOCK_MASK                 0x0000FFFFUL                      /**< Mask for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_SHIFT        0                                 /**< Shift value for EMU_LOCKKEY */
+#define _EMU_LOCK_LOCKKEY_MASK         0xFFFFUL                          /**< Bit mask for EMU_LOCKKEY */
+#define _EMU_LOCK_LOCKKEY_DEFAULT      0x00000000UL                      /**< Mode DEFAULT for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_UNLOCKED     0x00000000UL                      /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK         0x00000000UL                      /**< Mode LOCK for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCKED       0x00000001UL                      /**< Mode LOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_UNLOCK       0x0000ADE8UL                      /**< Mode UNLOCK for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_DEFAULT       (_EMU_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_UNLOCKED      (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK          (_EMU_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCKED        (_EMU_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_UNLOCK        (_EMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for EMU_LOCK */
+
+/* Bit fields for EMU AUXCTRL */
+#define _EMU_AUXCTRL_RESETVALUE        0x00000000UL                       /**< Default value for EMU_AUXCTRL */
+#define _EMU_AUXCTRL_MASK              0x00000001UL                       /**< Mask for EMU_AUXCTRL */
+#define EMU_AUXCTRL_HRCCLR             (0x1UL << 0)                       /**< Hard Reset Cause Clear */
+#define _EMU_AUXCTRL_HRCCLR_SHIFT      0                                  /**< Shift value for EMU_HRCCLR */
+#define _EMU_AUXCTRL_HRCCLR_MASK       0x1UL                              /**< Bit mask for EMU_HRCCLR */
+#define _EMU_AUXCTRL_HRCCLR_DEFAULT    0x00000000UL                       /**< Mode DEFAULT for EMU_AUXCTRL */
+#define EMU_AUXCTRL_HRCCLR_DEFAULT     (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */
+
+/** @} End of group EFM32HG_EMU */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_gpio_p.h

@@ -0,0 +1,65 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_GPIO_P register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief GPIO_P EFM32HG GPIO P
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;     /**< Port Control Register  */
+  __IOM uint32_t MODEL;    /**< Port Pin Mode Low Register  */
+  __IOM uint32_t MODEH;    /**< Port Pin Mode High Register  */
+  __IOM uint32_t DOUT;     /**< Port Data Out Register  */
+  __OM uint32_t  DOUTSET;  /**< Port Data Out Set Register  */
+  __OM uint32_t  DOUTCLR;  /**< Port Data Out Clear Register  */
+  __OM uint32_t  DOUTTGL;  /**< Port Data Out Toggle Register  */
+  __IM uint32_t  DIN;      /**< Port Data In Register  */
+  __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register  */
+} GPIO_P_TypeDef;
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_i2c.h

@@ -0,0 +1,717 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_I2C register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_I2C
+ * @{
+ * @brief EFM32HG_I2C Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;      /**< Control Register  */
+  __IOM uint32_t CMD;       /**< Command Register  */
+  __IM uint32_t  STATE;     /**< State Register  */
+  __IM uint32_t  STATUS;    /**< Status Register  */
+  __IOM uint32_t CLKDIV;    /**< Clock Division Register  */
+  __IOM uint32_t SADDR;     /**< Slave Address Register  */
+  __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register  */
+  __IM uint32_t  RXDATA;    /**< Receive Buffer Data Register  */
+  __IM uint32_t  RXDATAP;   /**< Receive Buffer Data Peek Register  */
+  __IOM uint32_t TXDATA;    /**< Transmit Buffer Data Register  */
+  __IM uint32_t  IF;        /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;       /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;       /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;       /**< Interrupt Enable Register  */
+  __IOM uint32_t ROUTE;     /**< I/O Routing Register  */
+} I2C_TypeDef;              /**< I2C Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_I2C_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for I2C CTRL */
+#define _I2C_CTRL_RESETVALUE              0x00000000UL                     /**< Default value for I2C_CTRL */
+#define _I2C_CTRL_MASK                    0x0007B37FUL                     /**< Mask for I2C_CTRL */
+#define I2C_CTRL_EN                       (0x1UL << 0)                     /**< I2C Enable */
+#define _I2C_CTRL_EN_SHIFT                0                                /**< Shift value for I2C_EN */
+#define _I2C_CTRL_EN_MASK                 0x1UL                            /**< Bit mask for I2C_EN */
+#define _I2C_CTRL_EN_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_EN_DEFAULT               (_I2C_CTRL_EN_DEFAULT << 0)      /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SLAVE                    (0x1UL << 1)                     /**< Addressable as Slave */
+#define _I2C_CTRL_SLAVE_SHIFT             1                                /**< Shift value for I2C_SLAVE */
+#define _I2C_CTRL_SLAVE_MASK              0x2UL                            /**< Bit mask for I2C_SLAVE */
+#define _I2C_CTRL_SLAVE_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SLAVE_DEFAULT            (_I2C_CTRL_SLAVE_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOACK                  (0x1UL << 2)                     /**< Automatic Acknowledge */
+#define _I2C_CTRL_AUTOACK_SHIFT           2                                /**< Shift value for I2C_AUTOACK */
+#define _I2C_CTRL_AUTOACK_MASK            0x4UL                            /**< Bit mask for I2C_AUTOACK */
+#define _I2C_CTRL_AUTOACK_DEFAULT         0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOACK_DEFAULT          (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSE                   (0x1UL << 3)                     /**< Automatic STOP when Empty */
+#define _I2C_CTRL_AUTOSE_SHIFT            3                                /**< Shift value for I2C_AUTOSE */
+#define _I2C_CTRL_AUTOSE_MASK             0x8UL                            /**< Bit mask for I2C_AUTOSE */
+#define _I2C_CTRL_AUTOSE_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSE_DEFAULT           (_I2C_CTRL_AUTOSE_DEFAULT << 3)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSN                   (0x1UL << 4)                     /**< Automatic STOP on NACK */
+#define _I2C_CTRL_AUTOSN_SHIFT            4                                /**< Shift value for I2C_AUTOSN */
+#define _I2C_CTRL_AUTOSN_MASK             0x10UL                           /**< Bit mask for I2C_AUTOSN */
+#define _I2C_CTRL_AUTOSN_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSN_DEFAULT           (_I2C_CTRL_AUTOSN_DEFAULT << 4)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_ARBDIS                   (0x1UL << 5)                     /**< Arbitration Disable */
+#define _I2C_CTRL_ARBDIS_SHIFT            5                                /**< Shift value for I2C_ARBDIS */
+#define _I2C_CTRL_ARBDIS_MASK             0x20UL                           /**< Bit mask for I2C_ARBDIS */
+#define _I2C_CTRL_ARBDIS_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_ARBDIS_DEFAULT           (_I2C_CTRL_ARBDIS_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GCAMEN                   (0x1UL << 6)                     /**< General Call Address Match Enable */
+#define _I2C_CTRL_GCAMEN_SHIFT            6                                /**< Shift value for I2C_GCAMEN */
+#define _I2C_CTRL_GCAMEN_MASK             0x40UL                           /**< Bit mask for I2C_GCAMEN */
+#define _I2C_CTRL_GCAMEN_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GCAMEN_DEFAULT           (_I2C_CTRL_GCAMEN_DEFAULT << 6)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLHR_SHIFT              8                                /**< Shift value for I2C_CLHR */
+#define _I2C_CTRL_CLHR_MASK               0x300UL                          /**< Bit mask for I2C_CLHR */
+#define _I2C_CTRL_CLHR_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLHR_STANDARD           0x00000000UL                     /**< Mode STANDARD for I2C_CTRL */
+#define _I2C_CTRL_CLHR_ASYMMETRIC         0x00000001UL                     /**< Mode ASYMMETRIC for I2C_CTRL */
+#define _I2C_CTRL_CLHR_FAST               0x00000002UL                     /**< Mode FAST for I2C_CTRL */
+#define I2C_CTRL_CLHR_DEFAULT             (_I2C_CTRL_CLHR_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CLHR_STANDARD            (_I2C_CTRL_CLHR_STANDARD << 8)   /**< Shifted mode STANDARD for I2C_CTRL */
+#define I2C_CTRL_CLHR_ASYMMETRIC          (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
+#define I2C_CTRL_CLHR_FAST                (_I2C_CTRL_CLHR_FAST << 8)       /**< Shifted mode FAST for I2C_CTRL */
+#define _I2C_CTRL_BITO_SHIFT              12                               /**< Shift value for I2C_BITO */
+#define _I2C_CTRL_BITO_MASK               0x3000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_CTRL_BITO_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_BITO_OFF                0x00000000UL                     /**< Mode OFF for I2C_CTRL */
+#define _I2C_CTRL_BITO_40PCC              0x00000001UL                     /**< Mode 40PCC for I2C_CTRL */
+#define _I2C_CTRL_BITO_80PCC              0x00000002UL                     /**< Mode 80PCC for I2C_CTRL */
+#define _I2C_CTRL_BITO_160PCC             0x00000003UL                     /**< Mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_DEFAULT             (_I2C_CTRL_BITO_DEFAULT << 12)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_BITO_OFF                 (_I2C_CTRL_BITO_OFF << 12)       /**< Shifted mode OFF for I2C_CTRL */
+#define I2C_CTRL_BITO_40PCC               (_I2C_CTRL_BITO_40PCC << 12)     /**< Shifted mode 40PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_80PCC               (_I2C_CTRL_BITO_80PCC << 12)     /**< Shifted mode 80PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_160PCC              (_I2C_CTRL_BITO_160PCC << 12)    /**< Shifted mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_GIBITO                   (0x1UL << 15)                    /**< Go Idle on Bus Idle Timeout  */
+#define _I2C_CTRL_GIBITO_SHIFT            15                               /**< Shift value for I2C_GIBITO */
+#define _I2C_CTRL_GIBITO_MASK             0x8000UL                         /**< Bit mask for I2C_GIBITO */
+#define _I2C_CTRL_GIBITO_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GIBITO_DEFAULT           (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLTO_SHIFT              16                               /**< Shift value for I2C_CLTO */
+#define _I2C_CTRL_CLTO_MASK               0x70000UL                        /**< Bit mask for I2C_CLTO */
+#define _I2C_CTRL_CLTO_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLTO_OFF                0x00000000UL                     /**< Mode OFF for I2C_CTRL */
+#define _I2C_CTRL_CLTO_40PCC              0x00000001UL                     /**< Mode 40PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_80PCC              0x00000002UL                     /**< Mode 80PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_160PCC             0x00000003UL                     /**< Mode 160PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_320PPC             0x00000004UL                     /**< Mode 320PPC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_1024PPC            0x00000005UL                     /**< Mode 1024PPC for I2C_CTRL */
+#define I2C_CTRL_CLTO_DEFAULT             (_I2C_CTRL_CLTO_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CLTO_OFF                 (_I2C_CTRL_CLTO_OFF << 16)       /**< Shifted mode OFF for I2C_CTRL */
+#define I2C_CTRL_CLTO_40PCC               (_I2C_CTRL_CLTO_40PCC << 16)     /**< Shifted mode 40PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_80PCC               (_I2C_CTRL_CLTO_80PCC << 16)     /**< Shifted mode 80PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_160PCC              (_I2C_CTRL_CLTO_160PCC << 16)    /**< Shifted mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_320PPC              (_I2C_CTRL_CLTO_320PPC << 16)    /**< Shifted mode 320PPC for I2C_CTRL */
+#define I2C_CTRL_CLTO_1024PPC             (_I2C_CTRL_CLTO_1024PPC << 16)   /**< Shifted mode 1024PPC for I2C_CTRL */
+
+/* Bit fields for I2C CMD */
+#define _I2C_CMD_RESETVALUE               0x00000000UL                    /**< Default value for I2C_CMD */
+#define _I2C_CMD_MASK                     0x000000FFUL                    /**< Mask for I2C_CMD */
+#define I2C_CMD_START                     (0x1UL << 0)                    /**< Send start condition */
+#define _I2C_CMD_START_SHIFT              0                               /**< Shift value for I2C_START */
+#define _I2C_CMD_START_MASK               0x1UL                           /**< Bit mask for I2C_START */
+#define _I2C_CMD_START_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_START_DEFAULT             (_I2C_CMD_START_DEFAULT << 0)   /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_STOP                      (0x1UL << 1)                    /**< Send stop condition */
+#define _I2C_CMD_STOP_SHIFT               1                               /**< Shift value for I2C_STOP */
+#define _I2C_CMD_STOP_MASK                0x2UL                           /**< Bit mask for I2C_STOP */
+#define _I2C_CMD_STOP_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_STOP_DEFAULT              (_I2C_CMD_STOP_DEFAULT << 1)    /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ACK                       (0x1UL << 2)                    /**< Send ACK */
+#define _I2C_CMD_ACK_SHIFT                2                               /**< Shift value for I2C_ACK */
+#define _I2C_CMD_ACK_MASK                 0x4UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_CMD_ACK_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ACK_DEFAULT               (_I2C_CMD_ACK_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_NACK                      (0x1UL << 3)                    /**< Send NACK */
+#define _I2C_CMD_NACK_SHIFT               3                               /**< Shift value for I2C_NACK */
+#define _I2C_CMD_NACK_MASK                0x8UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_CMD_NACK_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_NACK_DEFAULT              (_I2C_CMD_NACK_DEFAULT << 3)    /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CONT                      (0x1UL << 4)                    /**< Continue transmission */
+#define _I2C_CMD_CONT_SHIFT               4                               /**< Shift value for I2C_CONT */
+#define _I2C_CMD_CONT_MASK                0x10UL                          /**< Bit mask for I2C_CONT */
+#define _I2C_CMD_CONT_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CONT_DEFAULT              (_I2C_CMD_CONT_DEFAULT << 4)    /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ABORT                     (0x1UL << 5)                    /**< Abort transmission */
+#define _I2C_CMD_ABORT_SHIFT              5                               /**< Shift value for I2C_ABORT */
+#define _I2C_CMD_ABORT_MASK               0x20UL                          /**< Bit mask for I2C_ABORT */
+#define _I2C_CMD_ABORT_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ABORT_DEFAULT             (_I2C_CMD_ABORT_DEFAULT << 5)   /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARTX                   (0x1UL << 6)                    /**< Clear TX */
+#define _I2C_CMD_CLEARTX_SHIFT            6                               /**< Shift value for I2C_CLEARTX */
+#define _I2C_CMD_CLEARTX_MASK             0x40UL                          /**< Bit mask for I2C_CLEARTX */
+#define _I2C_CMD_CLEARTX_DEFAULT          0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARTX_DEFAULT           (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARPC                   (0x1UL << 7)                    /**< Clear Pending Commands */
+#define _I2C_CMD_CLEARPC_SHIFT            7                               /**< Shift value for I2C_CLEARPC */
+#define _I2C_CMD_CLEARPC_MASK             0x80UL                          /**< Bit mask for I2C_CLEARPC */
+#define _I2C_CMD_CLEARPC_DEFAULT          0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARPC_DEFAULT           (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
+
+/* Bit fields for I2C STATE */
+#define _I2C_STATE_RESETVALUE             0x00000001UL                          /**< Default value for I2C_STATE */
+#define _I2C_STATE_MASK                   0x000000FFUL                          /**< Mask for I2C_STATE */
+#define I2C_STATE_BUSY                    (0x1UL << 0)                          /**< Bus Busy */
+#define _I2C_STATE_BUSY_SHIFT             0                                     /**< Shift value for I2C_BUSY */
+#define _I2C_STATE_BUSY_MASK              0x1UL                                 /**< Bit mask for I2C_BUSY */
+#define _I2C_STATE_BUSY_DEFAULT           0x00000001UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSY_DEFAULT            (_I2C_STATE_BUSY_DEFAULT << 0)        /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_MASTER                  (0x1UL << 1)                          /**< Master */
+#define _I2C_STATE_MASTER_SHIFT           1                                     /**< Shift value for I2C_MASTER */
+#define _I2C_STATE_MASTER_MASK            0x2UL                                 /**< Bit mask for I2C_MASTER */
+#define _I2C_STATE_MASTER_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_MASTER_DEFAULT          (_I2C_STATE_MASTER_DEFAULT << 1)      /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_TRANSMITTER             (0x1UL << 2)                          /**< Transmitter */
+#define _I2C_STATE_TRANSMITTER_SHIFT      2                                     /**< Shift value for I2C_TRANSMITTER */
+#define _I2C_STATE_TRANSMITTER_MASK       0x4UL                                 /**< Bit mask for I2C_TRANSMITTER */
+#define _I2C_STATE_TRANSMITTER_DEFAULT    0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_TRANSMITTER_DEFAULT     (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_NACKED                  (0x1UL << 3)                          /**< Nack Received */
+#define _I2C_STATE_NACKED_SHIFT           3                                     /**< Shift value for I2C_NACKED */
+#define _I2C_STATE_NACKED_MASK            0x8UL                                 /**< Bit mask for I2C_NACKED */
+#define _I2C_STATE_NACKED_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_NACKED_DEFAULT          (_I2C_STATE_NACKED_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSHOLD                 (0x1UL << 4)                          /**< Bus Held */
+#define _I2C_STATE_BUSHOLD_SHIFT          4                                     /**< Shift value for I2C_BUSHOLD */
+#define _I2C_STATE_BUSHOLD_MASK           0x10UL                                /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_STATE_BUSHOLD_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSHOLD_DEFAULT         (_I2C_STATE_BUSHOLD_DEFAULT << 4)     /**< Shifted mode DEFAULT for I2C_STATE */
+#define _I2C_STATE_STATE_SHIFT            5                                     /**< Shift value for I2C_STATE */
+#define _I2C_STATE_STATE_MASK             0xE0UL                                /**< Bit mask for I2C_STATE */
+#define _I2C_STATE_STATE_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define _I2C_STATE_STATE_IDLE             0x00000000UL                          /**< Mode IDLE for I2C_STATE */
+#define _I2C_STATE_STATE_WAIT             0x00000001UL                          /**< Mode WAIT for I2C_STATE */
+#define _I2C_STATE_STATE_START            0x00000002UL                          /**< Mode START for I2C_STATE */
+#define _I2C_STATE_STATE_ADDR             0x00000003UL                          /**< Mode ADDR for I2C_STATE */
+#define _I2C_STATE_STATE_ADDRACK          0x00000004UL                          /**< Mode ADDRACK for I2C_STATE */
+#define _I2C_STATE_STATE_DATA             0x00000005UL                          /**< Mode DATA for I2C_STATE */
+#define _I2C_STATE_STATE_DATAACK          0x00000006UL                          /**< Mode DATAACK for I2C_STATE */
+#define I2C_STATE_STATE_DEFAULT           (_I2C_STATE_STATE_DEFAULT << 5)       /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_STATE_IDLE              (_I2C_STATE_STATE_IDLE << 5)          /**< Shifted mode IDLE for I2C_STATE */
+#define I2C_STATE_STATE_WAIT              (_I2C_STATE_STATE_WAIT << 5)          /**< Shifted mode WAIT for I2C_STATE */
+#define I2C_STATE_STATE_START             (_I2C_STATE_STATE_START << 5)         /**< Shifted mode START for I2C_STATE */
+#define I2C_STATE_STATE_ADDR              (_I2C_STATE_STATE_ADDR << 5)          /**< Shifted mode ADDR for I2C_STATE */
+#define I2C_STATE_STATE_ADDRACK           (_I2C_STATE_STATE_ADDRACK << 5)       /**< Shifted mode ADDRACK for I2C_STATE */
+#define I2C_STATE_STATE_DATA              (_I2C_STATE_STATE_DATA << 5)          /**< Shifted mode DATA for I2C_STATE */
+#define I2C_STATE_STATE_DATAACK           (_I2C_STATE_STATE_DATAACK << 5)       /**< Shifted mode DATAACK for I2C_STATE */
+
+/* Bit fields for I2C STATUS */
+#define _I2C_STATUS_RESETVALUE            0x00000080UL                       /**< Default value for I2C_STATUS */
+#define _I2C_STATUS_MASK                  0x000001FFUL                       /**< Mask for I2C_STATUS */
+#define I2C_STATUS_PSTART                 (0x1UL << 0)                       /**< Pending START */
+#define _I2C_STATUS_PSTART_SHIFT          0                                  /**< Shift value for I2C_PSTART */
+#define _I2C_STATUS_PSTART_MASK           0x1UL                              /**< Bit mask for I2C_PSTART */
+#define _I2C_STATUS_PSTART_DEFAULT        0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTART_DEFAULT         (_I2C_STATUS_PSTART_DEFAULT << 0)  /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTOP                  (0x1UL << 1)                       /**< Pending STOP */
+#define _I2C_STATUS_PSTOP_SHIFT           1                                  /**< Shift value for I2C_PSTOP */
+#define _I2C_STATUS_PSTOP_MASK            0x2UL                              /**< Bit mask for I2C_PSTOP */
+#define _I2C_STATUS_PSTOP_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTOP_DEFAULT          (_I2C_STATUS_PSTOP_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PACK                   (0x1UL << 2)                       /**< Pending ACK */
+#define _I2C_STATUS_PACK_SHIFT            2                                  /**< Shift value for I2C_PACK */
+#define _I2C_STATUS_PACK_MASK             0x4UL                              /**< Bit mask for I2C_PACK */
+#define _I2C_STATUS_PACK_DEFAULT          0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PACK_DEFAULT           (_I2C_STATUS_PACK_DEFAULT << 2)    /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PNACK                  (0x1UL << 3)                       /**< Pending NACK */
+#define _I2C_STATUS_PNACK_SHIFT           3                                  /**< Shift value for I2C_PNACK */
+#define _I2C_STATUS_PNACK_MASK            0x8UL                              /**< Bit mask for I2C_PNACK */
+#define _I2C_STATUS_PNACK_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PNACK_DEFAULT          (_I2C_STATUS_PNACK_DEFAULT << 3)   /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PCONT                  (0x1UL << 4)                       /**< Pending continue */
+#define _I2C_STATUS_PCONT_SHIFT           4                                  /**< Shift value for I2C_PCONT */
+#define _I2C_STATUS_PCONT_MASK            0x10UL                             /**< Bit mask for I2C_PCONT */
+#define _I2C_STATUS_PCONT_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PCONT_DEFAULT          (_I2C_STATUS_PCONT_DEFAULT << 4)   /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PABORT                 (0x1UL << 5)                       /**< Pending abort */
+#define _I2C_STATUS_PABORT_SHIFT          5                                  /**< Shift value for I2C_PABORT */
+#define _I2C_STATUS_PABORT_MASK           0x20UL                             /**< Bit mask for I2C_PABORT */
+#define _I2C_STATUS_PABORT_DEFAULT        0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PABORT_DEFAULT         (_I2C_STATUS_PABORT_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXC                    (0x1UL << 6)                       /**< TX Complete */
+#define _I2C_STATUS_TXC_SHIFT             6                                  /**< Shift value for I2C_TXC */
+#define _I2C_STATUS_TXC_MASK              0x40UL                             /**< Bit mask for I2C_TXC */
+#define _I2C_STATUS_TXC_DEFAULT           0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXC_DEFAULT            (_I2C_STATUS_TXC_DEFAULT << 6)     /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBL                   (0x1UL << 7)                       /**< TX Buffer Level */
+#define _I2C_STATUS_TXBL_SHIFT            7                                  /**< Shift value for I2C_TXBL */
+#define _I2C_STATUS_TXBL_MASK             0x80UL                             /**< Bit mask for I2C_TXBL */
+#define _I2C_STATUS_TXBL_DEFAULT          0x00000001UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBL_DEFAULT           (_I2C_STATUS_TXBL_DEFAULT << 7)    /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXDATAV                (0x1UL << 8)                       /**< RX Data Valid */
+#define _I2C_STATUS_RXDATAV_SHIFT         8                                  /**< Shift value for I2C_RXDATAV */
+#define _I2C_STATUS_RXDATAV_MASK          0x100UL                            /**< Bit mask for I2C_RXDATAV */
+#define _I2C_STATUS_RXDATAV_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXDATAV_DEFAULT        (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
+
+/* Bit fields for I2C CLKDIV */
+#define _I2C_CLKDIV_RESETVALUE            0x00000000UL                   /**< Default value for I2C_CLKDIV */
+#define _I2C_CLKDIV_MASK                  0x000001FFUL                   /**< Mask for I2C_CLKDIV */
+#define _I2C_CLKDIV_DIV_SHIFT             0                              /**< Shift value for I2C_DIV */
+#define _I2C_CLKDIV_DIV_MASK              0x1FFUL                        /**< Bit mask for I2C_DIV */
+#define _I2C_CLKDIV_DIV_DEFAULT           0x00000000UL                   /**< Mode DEFAULT for I2C_CLKDIV */
+#define I2C_CLKDIV_DIV_DEFAULT            (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
+
+/* Bit fields for I2C SADDR */
+#define _I2C_SADDR_RESETVALUE             0x00000000UL                   /**< Default value for I2C_SADDR */
+#define _I2C_SADDR_MASK                   0x000000FEUL                   /**< Mask for I2C_SADDR */
+#define _I2C_SADDR_ADDR_SHIFT             1                              /**< Shift value for I2C_ADDR */
+#define _I2C_SADDR_ADDR_MASK              0xFEUL                         /**< Bit mask for I2C_ADDR */
+#define _I2C_SADDR_ADDR_DEFAULT           0x00000000UL                   /**< Mode DEFAULT for I2C_SADDR */
+#define I2C_SADDR_ADDR_DEFAULT            (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
+
+/* Bit fields for I2C SADDRMASK */
+#define _I2C_SADDRMASK_RESETVALUE         0x00000000UL                       /**< Default value for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_MASK               0x000000FEUL                       /**< Mask for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_MASK_SHIFT         1                                  /**< Shift value for I2C_MASK */
+#define _I2C_SADDRMASK_MASK_MASK          0xFEUL                             /**< Bit mask for I2C_MASK */
+#define _I2C_SADDRMASK_MASK_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for I2C_SADDRMASK */
+#define I2C_SADDRMASK_MASK_DEFAULT        (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
+
+/* Bit fields for I2C RXDATA */
+#define _I2C_RXDATA_RESETVALUE            0x00000000UL                      /**< Default value for I2C_RXDATA */
+#define _I2C_RXDATA_MASK                  0x000000FFUL                      /**< Mask for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_SHIFT          0                                 /**< Shift value for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_MASK           0xFFUL                            /**< Bit mask for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_DEFAULT        0x00000000UL                      /**< Mode DEFAULT for I2C_RXDATA */
+#define I2C_RXDATA_RXDATA_DEFAULT         (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
+
+/* Bit fields for I2C RXDATAP */
+#define _I2C_RXDATAP_RESETVALUE           0x00000000UL                        /**< Default value for I2C_RXDATAP */
+#define _I2C_RXDATAP_MASK                 0x000000FFUL                        /**< Mask for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_SHIFT        0                                   /**< Shift value for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_MASK         0xFFUL                              /**< Bit mask for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_DEFAULT      0x00000000UL                        /**< Mode DEFAULT for I2C_RXDATAP */
+#define I2C_RXDATAP_RXDATAP_DEFAULT       (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
+
+/* Bit fields for I2C TXDATA */
+#define _I2C_TXDATA_RESETVALUE            0x00000000UL                      /**< Default value for I2C_TXDATA */
+#define _I2C_TXDATA_MASK                  0x000000FFUL                      /**< Mask for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_SHIFT          0                                 /**< Shift value for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_MASK           0xFFUL                            /**< Bit mask for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_DEFAULT        0x00000000UL                      /**< Mode DEFAULT for I2C_TXDATA */
+#define I2C_TXDATA_TXDATA_DEFAULT         (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
+
+/* Bit fields for I2C IF */
+#define _I2C_IF_RESETVALUE                0x00000010UL                    /**< Default value for I2C_IF */
+#define _I2C_IF_MASK                      0x0001FFFFUL                    /**< Mask for I2C_IF */
+#define I2C_IF_START                      (0x1UL << 0)                    /**< START condition Interrupt Flag */
+#define _I2C_IF_START_SHIFT               0                               /**< Shift value for I2C_START */
+#define _I2C_IF_START_MASK                0x1UL                           /**< Bit mask for I2C_START */
+#define _I2C_IF_START_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_START_DEFAULT              (_I2C_IF_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RSTART                     (0x1UL << 1)                    /**< Repeated START condition Interrupt Flag */
+#define _I2C_IF_RSTART_SHIFT              1                               /**< Shift value for I2C_RSTART */
+#define _I2C_IF_RSTART_MASK               0x2UL                           /**< Bit mask for I2C_RSTART */
+#define _I2C_IF_RSTART_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RSTART_DEFAULT             (_I2C_IF_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ADDR                       (0x1UL << 2)                    /**< Address Interrupt Flag */
+#define _I2C_IF_ADDR_SHIFT                2                               /**< Shift value for I2C_ADDR */
+#define _I2C_IF_ADDR_MASK                 0x4UL                           /**< Bit mask for I2C_ADDR */
+#define _I2C_IF_ADDR_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ADDR_DEFAULT               (_I2C_IF_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXC                        (0x1UL << 3)                    /**< Transfer Completed Interrupt Flag */
+#define _I2C_IF_TXC_SHIFT                 3                               /**< Shift value for I2C_TXC */
+#define _I2C_IF_TXC_MASK                  0x8UL                           /**< Bit mask for I2C_TXC */
+#define _I2C_IF_TXC_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXC_DEFAULT                (_I2C_IF_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXBL                       (0x1UL << 4)                    /**< Transmit Buffer Level Interrupt Flag */
+#define _I2C_IF_TXBL_SHIFT                4                               /**< Shift value for I2C_TXBL */
+#define _I2C_IF_TXBL_MASK                 0x10UL                          /**< Bit mask for I2C_TXBL */
+#define _I2C_IF_TXBL_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXBL_DEFAULT               (_I2C_IF_TXBL_DEFAULT << 4)     /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXDATAV                    (0x1UL << 5)                    /**< Receive Data Valid Interrupt Flag */
+#define _I2C_IF_RXDATAV_SHIFT             5                               /**< Shift value for I2C_RXDATAV */
+#define _I2C_IF_RXDATAV_MASK              0x20UL                          /**< Bit mask for I2C_RXDATAV */
+#define _I2C_IF_RXDATAV_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXDATAV_DEFAULT            (_I2C_IF_RXDATAV_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ACK                        (0x1UL << 6)                    /**< Acknowledge Received Interrupt Flag */
+#define _I2C_IF_ACK_SHIFT                 6                               /**< Shift value for I2C_ACK */
+#define _I2C_IF_ACK_MASK                  0x40UL                          /**< Bit mask for I2C_ACK */
+#define _I2C_IF_ACK_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ACK_DEFAULT                (_I2C_IF_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_NACK                       (0x1UL << 7)                    /**< Not Acknowledge Received Interrupt Flag */
+#define _I2C_IF_NACK_SHIFT                7                               /**< Shift value for I2C_NACK */
+#define _I2C_IF_NACK_MASK                 0x80UL                          /**< Bit mask for I2C_NACK */
+#define _I2C_IF_NACK_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_NACK_DEFAULT               (_I2C_IF_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_MSTOP                      (0x1UL << 8)                    /**< Master STOP Condition Interrupt Flag */
+#define _I2C_IF_MSTOP_SHIFT               8                               /**< Shift value for I2C_MSTOP */
+#define _I2C_IF_MSTOP_MASK                0x100UL                         /**< Bit mask for I2C_MSTOP */
+#define _I2C_IF_MSTOP_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_MSTOP_DEFAULT              (_I2C_IF_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ARBLOST                    (0x1UL << 9)                    /**< Arbitration Lost Interrupt Flag */
+#define _I2C_IF_ARBLOST_SHIFT             9                               /**< Shift value for I2C_ARBLOST */
+#define _I2C_IF_ARBLOST_MASK              0x200UL                         /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IF_ARBLOST_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ARBLOST_DEFAULT            (_I2C_IF_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSERR                     (0x1UL << 10)                   /**< Bus Error Interrupt Flag */
+#define _I2C_IF_BUSERR_SHIFT              10                              /**< Shift value for I2C_BUSERR */
+#define _I2C_IF_BUSERR_MASK               0x400UL                         /**< Bit mask for I2C_BUSERR */
+#define _I2C_IF_BUSERR_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSERR_DEFAULT             (_I2C_IF_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSHOLD                    (0x1UL << 11)                   /**< Bus Held Interrupt Flag */
+#define _I2C_IF_BUSHOLD_SHIFT             11                              /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IF_BUSHOLD_MASK              0x800UL                         /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IF_BUSHOLD_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSHOLD_DEFAULT            (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXOF                       (0x1UL << 12)                   /**< Transmit Buffer Overflow Interrupt Flag */
+#define _I2C_IF_TXOF_SHIFT                12                              /**< Shift value for I2C_TXOF */
+#define _I2C_IF_TXOF_MASK                 0x1000UL                        /**< Bit mask for I2C_TXOF */
+#define _I2C_IF_TXOF_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXOF_DEFAULT               (_I2C_IF_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXUF                       (0x1UL << 13)                   /**< Receive Buffer Underflow Interrupt Flag */
+#define _I2C_IF_RXUF_SHIFT                13                              /**< Shift value for I2C_RXUF */
+#define _I2C_IF_RXUF_MASK                 0x2000UL                        /**< Bit mask for I2C_RXUF */
+#define _I2C_IF_RXUF_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXUF_DEFAULT               (_I2C_IF_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BITO                       (0x1UL << 14)                   /**< Bus Idle Timeout Interrupt Flag */
+#define _I2C_IF_BITO_SHIFT                14                              /**< Shift value for I2C_BITO */
+#define _I2C_IF_BITO_MASK                 0x4000UL                        /**< Bit mask for I2C_BITO */
+#define _I2C_IF_BITO_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BITO_DEFAULT               (_I2C_IF_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_CLTO                       (0x1UL << 15)                   /**< Clock Low Timeout Interrupt Flag */
+#define _I2C_IF_CLTO_SHIFT                15                              /**< Shift value for I2C_CLTO */
+#define _I2C_IF_CLTO_MASK                 0x8000UL                        /**< Bit mask for I2C_CLTO */
+#define _I2C_IF_CLTO_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_CLTO_DEFAULT               (_I2C_IF_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_SSTOP                      (0x1UL << 16)                   /**< Slave STOP condition Interrupt Flag */
+#define _I2C_IF_SSTOP_SHIFT               16                              /**< Shift value for I2C_SSTOP */
+#define _I2C_IF_SSTOP_MASK                0x10000UL                       /**< Bit mask for I2C_SSTOP */
+#define _I2C_IF_SSTOP_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_SSTOP_DEFAULT              (_I2C_IF_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IF */
+
+/* Bit fields for I2C IFS */
+#define _I2C_IFS_RESETVALUE               0x00000000UL                     /**< Default value for I2C_IFS */
+#define _I2C_IFS_MASK                     0x0001FFCFUL                     /**< Mask for I2C_IFS */
+#define I2C_IFS_START                     (0x1UL << 0)                     /**< Set START Interrupt Flag */
+#define _I2C_IFS_START_SHIFT              0                                /**< Shift value for I2C_START */
+#define _I2C_IFS_START_MASK               0x1UL                            /**< Bit mask for I2C_START */
+#define _I2C_IFS_START_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_START_DEFAULT             (_I2C_IFS_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RSTART                    (0x1UL << 1)                     /**< Set Repeated START Interrupt Flag */
+#define _I2C_IFS_RSTART_SHIFT             1                                /**< Shift value for I2C_RSTART */
+#define _I2C_IFS_RSTART_MASK              0x2UL                            /**< Bit mask for I2C_RSTART */
+#define _I2C_IFS_RSTART_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RSTART_DEFAULT            (_I2C_IFS_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ADDR                      (0x1UL << 2)                     /**< Set Address Interrupt Flag */
+#define _I2C_IFS_ADDR_SHIFT               2                                /**< Shift value for I2C_ADDR */
+#define _I2C_IFS_ADDR_MASK                0x4UL                            /**< Bit mask for I2C_ADDR */
+#define _I2C_IFS_ADDR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ADDR_DEFAULT              (_I2C_IFS_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXC                       (0x1UL << 3)                     /**< Set Transfer Completed Interrupt Flag */
+#define _I2C_IFS_TXC_SHIFT                3                                /**< Shift value for I2C_TXC */
+#define _I2C_IFS_TXC_MASK                 0x8UL                            /**< Bit mask for I2C_TXC */
+#define _I2C_IFS_TXC_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXC_DEFAULT               (_I2C_IFS_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ACK                       (0x1UL << 6)                     /**< Set Acknowledge Received Interrupt Flag */
+#define _I2C_IFS_ACK_SHIFT                6                                /**< Shift value for I2C_ACK */
+#define _I2C_IFS_ACK_MASK                 0x40UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_IFS_ACK_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ACK_DEFAULT               (_I2C_IFS_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_NACK                      (0x1UL << 7)                     /**< Set Not Acknowledge Received Interrupt Flag */
+#define _I2C_IFS_NACK_SHIFT               7                                /**< Shift value for I2C_NACK */
+#define _I2C_IFS_NACK_MASK                0x80UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_IFS_NACK_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_NACK_DEFAULT              (_I2C_IFS_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_MSTOP                     (0x1UL << 8)                     /**< Set MSTOP Interrupt Flag */
+#define _I2C_IFS_MSTOP_SHIFT              8                                /**< Shift value for I2C_MSTOP */
+#define _I2C_IFS_MSTOP_MASK               0x100UL                          /**< Bit mask for I2C_MSTOP */
+#define _I2C_IFS_MSTOP_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_MSTOP_DEFAULT             (_I2C_IFS_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ARBLOST                   (0x1UL << 9)                     /**< Set Arbitration Lost Interrupt Flag */
+#define _I2C_IFS_ARBLOST_SHIFT            9                                /**< Shift value for I2C_ARBLOST */
+#define _I2C_IFS_ARBLOST_MASK             0x200UL                          /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IFS_ARBLOST_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ARBLOST_DEFAULT           (_I2C_IFS_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSERR                    (0x1UL << 10)                    /**< Set Bus Error Interrupt Flag */
+#define _I2C_IFS_BUSERR_SHIFT             10                               /**< Shift value for I2C_BUSERR */
+#define _I2C_IFS_BUSERR_MASK              0x400UL                          /**< Bit mask for I2C_BUSERR */
+#define _I2C_IFS_BUSERR_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSERR_DEFAULT            (_I2C_IFS_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSHOLD                   (0x1UL << 11)                    /**< Set Bus Held Interrupt Flag */
+#define _I2C_IFS_BUSHOLD_SHIFT            11                               /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IFS_BUSHOLD_MASK             0x800UL                          /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IFS_BUSHOLD_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSHOLD_DEFAULT           (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXOF                      (0x1UL << 12)                    /**< Set Transmit Buffer Overflow Interrupt Flag */
+#define _I2C_IFS_TXOF_SHIFT               12                               /**< Shift value for I2C_TXOF */
+#define _I2C_IFS_TXOF_MASK                0x1000UL                         /**< Bit mask for I2C_TXOF */
+#define _I2C_IFS_TXOF_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXOF_DEFAULT              (_I2C_IFS_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXUF                      (0x1UL << 13)                    /**< Set Receive Buffer Underflow Interrupt Flag */
+#define _I2C_IFS_RXUF_SHIFT               13                               /**< Shift value for I2C_RXUF */
+#define _I2C_IFS_RXUF_MASK                0x2000UL                         /**< Bit mask for I2C_RXUF */
+#define _I2C_IFS_RXUF_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXUF_DEFAULT              (_I2C_IFS_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BITO                      (0x1UL << 14)                    /**< Set Bus Idle Timeout Interrupt Flag */
+#define _I2C_IFS_BITO_SHIFT               14                               /**< Shift value for I2C_BITO */
+#define _I2C_IFS_BITO_MASK                0x4000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_IFS_BITO_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BITO_DEFAULT              (_I2C_IFS_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLTO                      (0x1UL << 15)                    /**< Set Clock Low Interrupt Flag */
+#define _I2C_IFS_CLTO_SHIFT               15                               /**< Shift value for I2C_CLTO */
+#define _I2C_IFS_CLTO_MASK                0x8000UL                         /**< Bit mask for I2C_CLTO */
+#define _I2C_IFS_CLTO_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLTO_DEFAULT              (_I2C_IFS_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_SSTOP                     (0x1UL << 16)                    /**< Set SSTOP Interrupt Flag */
+#define _I2C_IFS_SSTOP_SHIFT              16                               /**< Shift value for I2C_SSTOP */
+#define _I2C_IFS_SSTOP_MASK               0x10000UL                        /**< Bit mask for I2C_SSTOP */
+#define _I2C_IFS_SSTOP_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_SSTOP_DEFAULT             (_I2C_IFS_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IFS */
+
+/* Bit fields for I2C IFC */
+#define _I2C_IFC_RESETVALUE               0x00000000UL                     /**< Default value for I2C_IFC */
+#define _I2C_IFC_MASK                     0x0001FFCFUL                     /**< Mask for I2C_IFC */
+#define I2C_IFC_START                     (0x1UL << 0)                     /**< Clear START Interrupt Flag */
+#define _I2C_IFC_START_SHIFT              0                                /**< Shift value for I2C_START */
+#define _I2C_IFC_START_MASK               0x1UL                            /**< Bit mask for I2C_START */
+#define _I2C_IFC_START_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_START_DEFAULT             (_I2C_IFC_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RSTART                    (0x1UL << 1)                     /**< Clear Repeated START Interrupt Flag */
+#define _I2C_IFC_RSTART_SHIFT             1                                /**< Shift value for I2C_RSTART */
+#define _I2C_IFC_RSTART_MASK              0x2UL                            /**< Bit mask for I2C_RSTART */
+#define _I2C_IFC_RSTART_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RSTART_DEFAULT            (_I2C_IFC_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ADDR                      (0x1UL << 2)                     /**< Clear Address Interrupt Flag */
+#define _I2C_IFC_ADDR_SHIFT               2                                /**< Shift value for I2C_ADDR */
+#define _I2C_IFC_ADDR_MASK                0x4UL                            /**< Bit mask for I2C_ADDR */
+#define _I2C_IFC_ADDR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ADDR_DEFAULT              (_I2C_IFC_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXC                       (0x1UL << 3)                     /**< Clear Transfer Completed Interrupt Flag */
+#define _I2C_IFC_TXC_SHIFT                3                                /**< Shift value for I2C_TXC */
+#define _I2C_IFC_TXC_MASK                 0x8UL                            /**< Bit mask for I2C_TXC */
+#define _I2C_IFC_TXC_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXC_DEFAULT               (_I2C_IFC_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ACK                       (0x1UL << 6)                     /**< Clear Acknowledge Received Interrupt Flag */
+#define _I2C_IFC_ACK_SHIFT                6                                /**< Shift value for I2C_ACK */
+#define _I2C_IFC_ACK_MASK                 0x40UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_IFC_ACK_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ACK_DEFAULT               (_I2C_IFC_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_NACK                      (0x1UL << 7)                     /**< Clear Not Acknowledge Received Interrupt Flag */
+#define _I2C_IFC_NACK_SHIFT               7                                /**< Shift value for I2C_NACK */
+#define _I2C_IFC_NACK_MASK                0x80UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_IFC_NACK_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_NACK_DEFAULT              (_I2C_IFC_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_MSTOP                     (0x1UL << 8)                     /**< Clear MSTOP Interrupt Flag */
+#define _I2C_IFC_MSTOP_SHIFT              8                                /**< Shift value for I2C_MSTOP */
+#define _I2C_IFC_MSTOP_MASK               0x100UL                          /**< Bit mask for I2C_MSTOP */
+#define _I2C_IFC_MSTOP_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_MSTOP_DEFAULT             (_I2C_IFC_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ARBLOST                   (0x1UL << 9)                     /**< Clear Arbitration Lost Interrupt Flag */
+#define _I2C_IFC_ARBLOST_SHIFT            9                                /**< Shift value for I2C_ARBLOST */
+#define _I2C_IFC_ARBLOST_MASK             0x200UL                          /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IFC_ARBLOST_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ARBLOST_DEFAULT           (_I2C_IFC_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSERR                    (0x1UL << 10)                    /**< Clear Bus Error Interrupt Flag */
+#define _I2C_IFC_BUSERR_SHIFT             10                               /**< Shift value for I2C_BUSERR */
+#define _I2C_IFC_BUSERR_MASK              0x400UL                          /**< Bit mask for I2C_BUSERR */
+#define _I2C_IFC_BUSERR_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSERR_DEFAULT            (_I2C_IFC_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSHOLD                   (0x1UL << 11)                    /**< Clear Bus Held Interrupt Flag */
+#define _I2C_IFC_BUSHOLD_SHIFT            11                               /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IFC_BUSHOLD_MASK             0x800UL                          /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IFC_BUSHOLD_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSHOLD_DEFAULT           (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXOF                      (0x1UL << 12)                    /**< Clear Transmit Buffer Overflow Interrupt Flag */
+#define _I2C_IFC_TXOF_SHIFT               12                               /**< Shift value for I2C_TXOF */
+#define _I2C_IFC_TXOF_MASK                0x1000UL                         /**< Bit mask for I2C_TXOF */
+#define _I2C_IFC_TXOF_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXOF_DEFAULT              (_I2C_IFC_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXUF                      (0x1UL << 13)                    /**< Clear Receive Buffer Underflow Interrupt Flag */
+#define _I2C_IFC_RXUF_SHIFT               13                               /**< Shift value for I2C_RXUF */
+#define _I2C_IFC_RXUF_MASK                0x2000UL                         /**< Bit mask for I2C_RXUF */
+#define _I2C_IFC_RXUF_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXUF_DEFAULT              (_I2C_IFC_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BITO                      (0x1UL << 14)                    /**< Clear Bus Idle Timeout Interrupt Flag */
+#define _I2C_IFC_BITO_SHIFT               14                               /**< Shift value for I2C_BITO */
+#define _I2C_IFC_BITO_MASK                0x4000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_IFC_BITO_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BITO_DEFAULT              (_I2C_IFC_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLTO                      (0x1UL << 15)                    /**< Clear Clock Low Interrupt Flag */
+#define _I2C_IFC_CLTO_SHIFT               15                               /**< Shift value for I2C_CLTO */
+#define _I2C_IFC_CLTO_MASK                0x8000UL                         /**< Bit mask for I2C_CLTO */
+#define _I2C_IFC_CLTO_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLTO_DEFAULT              (_I2C_IFC_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_SSTOP                     (0x1UL << 16)                    /**< Clear SSTOP Interrupt Flag */
+#define _I2C_IFC_SSTOP_SHIFT              16                               /**< Shift value for I2C_SSTOP */
+#define _I2C_IFC_SSTOP_MASK               0x10000UL                        /**< Bit mask for I2C_SSTOP */
+#define _I2C_IFC_SSTOP_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_SSTOP_DEFAULT             (_I2C_IFC_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IFC */
+
+/* Bit fields for I2C IEN */
+#define _I2C_IEN_RESETVALUE               0x00000000UL                     /**< Default value for I2C_IEN */
+#define _I2C_IEN_MASK                     0x0001FFFFUL                     /**< Mask for I2C_IEN */
+#define I2C_IEN_START                     (0x1UL << 0)                     /**< START Condition Interrupt Enable */
+#define _I2C_IEN_START_SHIFT              0                                /**< Shift value for I2C_START */
+#define _I2C_IEN_START_MASK               0x1UL                            /**< Bit mask for I2C_START */
+#define _I2C_IEN_START_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_START_DEFAULT             (_I2C_IEN_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RSTART                    (0x1UL << 1)                     /**< Repeated START condition Interrupt Enable */
+#define _I2C_IEN_RSTART_SHIFT             1                                /**< Shift value for I2C_RSTART */
+#define _I2C_IEN_RSTART_MASK              0x2UL                            /**< Bit mask for I2C_RSTART */
+#define _I2C_IEN_RSTART_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RSTART_DEFAULT            (_I2C_IEN_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ADDR                      (0x1UL << 2)                     /**< Address Interrupt Enable */
+#define _I2C_IEN_ADDR_SHIFT               2                                /**< Shift value for I2C_ADDR */
+#define _I2C_IEN_ADDR_MASK                0x4UL                            /**< Bit mask for I2C_ADDR */
+#define _I2C_IEN_ADDR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ADDR_DEFAULT              (_I2C_IEN_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXC                       (0x1UL << 3)                     /**< Transfer Completed Interrupt Enable */
+#define _I2C_IEN_TXC_SHIFT                3                                /**< Shift value for I2C_TXC */
+#define _I2C_IEN_TXC_MASK                 0x8UL                            /**< Bit mask for I2C_TXC */
+#define _I2C_IEN_TXC_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXC_DEFAULT               (_I2C_IEN_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXBL                      (0x1UL << 4)                     /**< Transmit Buffer level Interrupt Enable */
+#define _I2C_IEN_TXBL_SHIFT               4                                /**< Shift value for I2C_TXBL */
+#define _I2C_IEN_TXBL_MASK                0x10UL                           /**< Bit mask for I2C_TXBL */
+#define _I2C_IEN_TXBL_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXBL_DEFAULT              (_I2C_IEN_TXBL_DEFAULT << 4)     /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXDATAV                   (0x1UL << 5)                     /**< Receive Data Valid Interrupt Enable */
+#define _I2C_IEN_RXDATAV_SHIFT            5                                /**< Shift value for I2C_RXDATAV */
+#define _I2C_IEN_RXDATAV_MASK             0x20UL                           /**< Bit mask for I2C_RXDATAV */
+#define _I2C_IEN_RXDATAV_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXDATAV_DEFAULT           (_I2C_IEN_RXDATAV_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ACK                       (0x1UL << 6)                     /**< Acknowledge Received Interrupt Enable */
+#define _I2C_IEN_ACK_SHIFT                6                                /**< Shift value for I2C_ACK */
+#define _I2C_IEN_ACK_MASK                 0x40UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_IEN_ACK_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ACK_DEFAULT               (_I2C_IEN_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_NACK                      (0x1UL << 7)                     /**< Not Acknowledge Received Interrupt Enable */
+#define _I2C_IEN_NACK_SHIFT               7                                /**< Shift value for I2C_NACK */
+#define _I2C_IEN_NACK_MASK                0x80UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_IEN_NACK_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_NACK_DEFAULT              (_I2C_IEN_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_MSTOP                     (0x1UL << 8)                     /**< MSTOP Interrupt Enable */
+#define _I2C_IEN_MSTOP_SHIFT              8                                /**< Shift value for I2C_MSTOP */
+#define _I2C_IEN_MSTOP_MASK               0x100UL                          /**< Bit mask for I2C_MSTOP */
+#define _I2C_IEN_MSTOP_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_MSTOP_DEFAULT             (_I2C_IEN_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ARBLOST                   (0x1UL << 9)                     /**< Arbitration Lost Interrupt Enable */
+#define _I2C_IEN_ARBLOST_SHIFT            9                                /**< Shift value for I2C_ARBLOST */
+#define _I2C_IEN_ARBLOST_MASK             0x200UL                          /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IEN_ARBLOST_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ARBLOST_DEFAULT           (_I2C_IEN_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSERR                    (0x1UL << 10)                    /**< Bus Error Interrupt Enable */
+#define _I2C_IEN_BUSERR_SHIFT             10                               /**< Shift value for I2C_BUSERR */
+#define _I2C_IEN_BUSERR_MASK              0x400UL                          /**< Bit mask for I2C_BUSERR */
+#define _I2C_IEN_BUSERR_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSERR_DEFAULT            (_I2C_IEN_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSHOLD                   (0x1UL << 11)                    /**< Bus Held Interrupt Enable */
+#define _I2C_IEN_BUSHOLD_SHIFT            11                               /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IEN_BUSHOLD_MASK             0x800UL                          /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IEN_BUSHOLD_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSHOLD_DEFAULT           (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXOF                      (0x1UL << 12)                    /**< Transmit Buffer Overflow Interrupt Enable */
+#define _I2C_IEN_TXOF_SHIFT               12                               /**< Shift value for I2C_TXOF */
+#define _I2C_IEN_TXOF_MASK                0x1000UL                         /**< Bit mask for I2C_TXOF */
+#define _I2C_IEN_TXOF_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXOF_DEFAULT              (_I2C_IEN_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXUF                      (0x1UL << 13)                    /**< Receive Buffer Underflow Interrupt Enable */
+#define _I2C_IEN_RXUF_SHIFT               13                               /**< Shift value for I2C_RXUF */
+#define _I2C_IEN_RXUF_MASK                0x2000UL                         /**< Bit mask for I2C_RXUF */
+#define _I2C_IEN_RXUF_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXUF_DEFAULT              (_I2C_IEN_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BITO                      (0x1UL << 14)                    /**< Bus Idle Timeout Interrupt Enable */
+#define _I2C_IEN_BITO_SHIFT               14                               /**< Shift value for I2C_BITO */
+#define _I2C_IEN_BITO_MASK                0x4000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_IEN_BITO_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BITO_DEFAULT              (_I2C_IEN_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLTO                      (0x1UL << 15)                    /**< Clock Low Interrupt Enable */
+#define _I2C_IEN_CLTO_SHIFT               15                               /**< Shift value for I2C_CLTO */
+#define _I2C_IEN_CLTO_MASK                0x8000UL                         /**< Bit mask for I2C_CLTO */
+#define _I2C_IEN_CLTO_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLTO_DEFAULT              (_I2C_IEN_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SSTOP                     (0x1UL << 16)                    /**< SSTOP Interrupt Enable */
+#define _I2C_IEN_SSTOP_SHIFT              16                               /**< Shift value for I2C_SSTOP */
+#define _I2C_IEN_SSTOP_MASK               0x10000UL                        /**< Bit mask for I2C_SSTOP */
+#define _I2C_IEN_SSTOP_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SSTOP_DEFAULT             (_I2C_IEN_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IEN */
+
+/* Bit fields for I2C ROUTE */
+#define _I2C_ROUTE_RESETVALUE             0x00000000UL                       /**< Default value for I2C_ROUTE */
+#define _I2C_ROUTE_MASK                   0x00000703UL                       /**< Mask for I2C_ROUTE */
+#define I2C_ROUTE_SDAPEN                  (0x1UL << 0)                       /**< SDA Pin Enable */
+#define _I2C_ROUTE_SDAPEN_SHIFT           0                                  /**< Shift value for I2C_SDAPEN */
+#define _I2C_ROUTE_SDAPEN_MASK            0x1UL                              /**< Bit mask for I2C_SDAPEN */
+#define _I2C_ROUTE_SDAPEN_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_ROUTE */
+#define I2C_ROUTE_SDAPEN_DEFAULT          (_I2C_ROUTE_SDAPEN_DEFAULT << 0)   /**< Shifted mode DEFAULT for I2C_ROUTE */
+#define I2C_ROUTE_SCLPEN                  (0x1UL << 1)                       /**< SCL Pin Enable */
+#define _I2C_ROUTE_SCLPEN_SHIFT           1                                  /**< Shift value for I2C_SCLPEN */
+#define _I2C_ROUTE_SCLPEN_MASK            0x2UL                              /**< Bit mask for I2C_SCLPEN */
+#define _I2C_ROUTE_SCLPEN_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_ROUTE */
+#define I2C_ROUTE_SCLPEN_DEFAULT          (_I2C_ROUTE_SCLPEN_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_ROUTE */
+#define _I2C_ROUTE_LOCATION_SHIFT         8                                  /**< Shift value for I2C_LOCATION */
+#define _I2C_ROUTE_LOCATION_MASK          0x700UL                            /**< Bit mask for I2C_LOCATION */
+#define _I2C_ROUTE_LOCATION_LOC0          0x00000000UL                       /**< Mode LOC0 for I2C_ROUTE */
+#define _I2C_ROUTE_LOCATION_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for I2C_ROUTE */
+#define _I2C_ROUTE_LOCATION_LOC1          0x00000001UL                       /**< Mode LOC1 for I2C_ROUTE */
+#define _I2C_ROUTE_LOCATION_LOC2          0x00000002UL                       /**< Mode LOC2 for I2C_ROUTE */
+#define _I2C_ROUTE_LOCATION_LOC3          0x00000003UL                       /**< Mode LOC3 for I2C_ROUTE */
+#define _I2C_ROUTE_LOCATION_LOC4          0x00000004UL                       /**< Mode LOC4 for I2C_ROUTE */
+#define _I2C_ROUTE_LOCATION_LOC5          0x00000005UL                       /**< Mode LOC5 for I2C_ROUTE */
+#define _I2C_ROUTE_LOCATION_LOC6          0x00000006UL                       /**< Mode LOC6 for I2C_ROUTE */
+#define I2C_ROUTE_LOCATION_LOC0           (_I2C_ROUTE_LOCATION_LOC0 << 8)    /**< Shifted mode LOC0 for I2C_ROUTE */
+#define I2C_ROUTE_LOCATION_DEFAULT        (_I2C_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */
+#define I2C_ROUTE_LOCATION_LOC1           (_I2C_ROUTE_LOCATION_LOC1 << 8)    /**< Shifted mode LOC1 for I2C_ROUTE */
+#define I2C_ROUTE_LOCATION_LOC2           (_I2C_ROUTE_LOCATION_LOC2 << 8)    /**< Shifted mode LOC2 for I2C_ROUTE */
+#define I2C_ROUTE_LOCATION_LOC3           (_I2C_ROUTE_LOCATION_LOC3 << 8)    /**< Shifted mode LOC3 for I2C_ROUTE */
+#define I2C_ROUTE_LOCATION_LOC4           (_I2C_ROUTE_LOCATION_LOC4 << 8)    /**< Shifted mode LOC4 for I2C_ROUTE */
+#define I2C_ROUTE_LOCATION_LOC5           (_I2C_ROUTE_LOCATION_LOC5 << 8)    /**< Shifted mode LOC5 for I2C_ROUTE */
+#define I2C_ROUTE_LOCATION_LOC6           (_I2C_ROUTE_LOCATION_LOC6 << 8)    /**< Shifted mode LOC6 for I2C_ROUTE */
+
+/** @} End of group EFM32HG_I2C */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_idac.h

@@ -0,0 +1,164 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_IDAC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_IDAC
+ * @{
+ * @brief EFM32HG_IDAC Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;       /**< Control Register  */
+  __IOM uint32_t CURPROG;    /**< Current Programming Register  */
+  __IOM uint32_t CAL;        /**< Calibration Register  */
+  __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configauration Register  */
+} IDAC_TypeDef;              /**< IDAC Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_IDAC_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for IDAC CTRL */
+#define _IDAC_CTRL_RESETVALUE                       0x00000000UL                          /**< Default value for IDAC_CTRL */
+#define _IDAC_CTRL_MASK                             0x0074001FUL                          /**< Mask for IDAC_CTRL */
+#define IDAC_CTRL_EN                                (0x1UL << 0)                          /**< Current DAC Enable */
+#define _IDAC_CTRL_EN_SHIFT                         0                                     /**< Shift value for IDAC_EN */
+#define _IDAC_CTRL_EN_MASK                          0x1UL                                 /**< Bit mask for IDAC_EN */
+#define _IDAC_CTRL_EN_DEFAULT                       0x00000000UL                          /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_EN_DEFAULT                        (_IDAC_CTRL_EN_DEFAULT << 0)          /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_CURSINK                           (0x1UL << 1)                          /**< Current Sink Enable */
+#define _IDAC_CTRL_CURSINK_SHIFT                    1                                     /**< Shift value for IDAC_CURSINK */
+#define _IDAC_CTRL_CURSINK_MASK                     0x2UL                                 /**< Bit mask for IDAC_CURSINK */
+#define _IDAC_CTRL_CURSINK_DEFAULT                  0x00000000UL                          /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_CURSINK_DEFAULT                   (_IDAC_CTRL_CURSINK_DEFAULT << 1)     /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_MINOUTTRANS                       (0x1UL << 2)                          /**< Minimum Output Transition Enable */
+#define _IDAC_CTRL_MINOUTTRANS_SHIFT                2                                     /**< Shift value for IDAC_MINOUTTRANS */
+#define _IDAC_CTRL_MINOUTTRANS_MASK                 0x4UL                                 /**< Bit mask for IDAC_MINOUTTRANS */
+#define _IDAC_CTRL_MINOUTTRANS_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_MINOUTTRANS_DEFAULT               (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_OUTEN                             (0x1UL << 3)                          /**< Output Enable */
+#define _IDAC_CTRL_OUTEN_SHIFT                      3                                     /**< Shift value for IDAC_OUTEN */
+#define _IDAC_CTRL_OUTEN_MASK                       0x8UL                                 /**< Bit mask for IDAC_OUTEN */
+#define _IDAC_CTRL_OUTEN_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_OUTEN_DEFAULT                     (_IDAC_CTRL_OUTEN_DEFAULT << 3)       /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_OUTMODE                           (0x1UL << 4)                          /**< Output Modes */
+#define _IDAC_CTRL_OUTMODE_SHIFT                    4                                     /**< Shift value for IDAC_OUTMODE */
+#define _IDAC_CTRL_OUTMODE_MASK                     0x10UL                                /**< Bit mask for IDAC_OUTMODE */
+#define _IDAC_CTRL_OUTMODE_DEFAULT                  0x00000000UL                          /**< Mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_OUTMODE_PIN                      0x00000000UL                          /**< Mode PIN for IDAC_CTRL */
+#define _IDAC_CTRL_OUTMODE_ADC                      0x00000001UL                          /**< Mode ADC for IDAC_CTRL */
+#define IDAC_CTRL_OUTMODE_DEFAULT                   (_IDAC_CTRL_OUTMODE_DEFAULT << 4)     /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_OUTMODE_PIN                       (_IDAC_CTRL_OUTMODE_PIN << 4)         /**< Shifted mode PIN for IDAC_CTRL */
+#define IDAC_CTRL_OUTMODE_ADC                       (_IDAC_CTRL_OUTMODE_ADC << 4)         /**< Shifted mode ADC for IDAC_CTRL */
+#define IDAC_CTRL_OUTENPRS                          (0x1UL << 18)                         /**< PRS Controlled Output Enable */
+#define _IDAC_CTRL_OUTENPRS_SHIFT                   18                                    /**< Shift value for IDAC_OUTENPRS */
+#define _IDAC_CTRL_OUTENPRS_MASK                    0x40000UL                             /**< Bit mask for IDAC_OUTENPRS */
+#define _IDAC_CTRL_OUTENPRS_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_OUTENPRS_DEFAULT                  (_IDAC_CTRL_OUTENPRS_DEFAULT << 18)   /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_SHIFT                     20                                    /**< Shift value for IDAC_PRSSEL */
+#define _IDAC_CTRL_PRSSEL_MASK                      0x700000UL                            /**< Bit mask for IDAC_PRSSEL */
+#define _IDAC_CTRL_PRSSEL_DEFAULT                   0x00000000UL                          /**< Mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH0                    0x00000000UL                          /**< Mode PRSCH0 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH1                    0x00000001UL                          /**< Mode PRSCH1 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH2                    0x00000002UL                          /**< Mode PRSCH2 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH3                    0x00000003UL                          /**< Mode PRSCH3 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH4                    0x00000004UL                          /**< Mode PRSCH4 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH5                    0x00000005UL                          /**< Mode PRSCH5 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_DEFAULT                    (_IDAC_CTRL_PRSSEL_DEFAULT << 20)     /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH0                     (_IDAC_CTRL_PRSSEL_PRSCH0 << 20)      /**< Shifted mode PRSCH0 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH1                     (_IDAC_CTRL_PRSSEL_PRSCH1 << 20)      /**< Shifted mode PRSCH1 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH2                     (_IDAC_CTRL_PRSSEL_PRSCH2 << 20)      /**< Shifted mode PRSCH2 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH3                     (_IDAC_CTRL_PRSSEL_PRSCH3 << 20)      /**< Shifted mode PRSCH3 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH4                     (_IDAC_CTRL_PRSSEL_PRSCH4 << 20)      /**< Shifted mode PRSCH4 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH5                     (_IDAC_CTRL_PRSSEL_PRSCH5 << 20)      /**< Shifted mode PRSCH5 for IDAC_CTRL */
+
+/* Bit fields for IDAC CURPROG */
+#define _IDAC_CURPROG_RESETVALUE                    0x00000000UL                          /**< Default value for IDAC_CURPROG */
+#define _IDAC_CURPROG_MASK                          0x00001F03UL                          /**< Mask for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_SHIFT                0                                     /**< Shift value for IDAC_RANGESEL */
+#define _IDAC_CURPROG_RANGESEL_MASK                 0x3UL                                 /**< Bit mask for IDAC_RANGESEL */
+#define _IDAC_CURPROG_RANGESEL_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE0               0x00000000UL                          /**< Mode RANGE0 for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE1               0x00000001UL                          /**< Mode RANGE1 for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE2               0x00000002UL                          /**< Mode RANGE2 for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE3               0x00000003UL                          /**< Mode RANGE3 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_DEFAULT               (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE0                (_IDAC_CURPROG_RANGESEL_RANGE0 << 0)  /**< Shifted mode RANGE0 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE1                (_IDAC_CURPROG_RANGESEL_RANGE1 << 0)  /**< Shifted mode RANGE1 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE2                (_IDAC_CURPROG_RANGESEL_RANGE2 << 0)  /**< Shifted mode RANGE2 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE3                (_IDAC_CURPROG_RANGESEL_RANGE3 << 0)  /**< Shifted mode RANGE3 for IDAC_CURPROG */
+#define _IDAC_CURPROG_STEPSEL_SHIFT                 8                                     /**< Shift value for IDAC_STEPSEL */
+#define _IDAC_CURPROG_STEPSEL_MASK                  0x1F00UL                              /**< Bit mask for IDAC_STEPSEL */
+#define _IDAC_CURPROG_STEPSEL_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for IDAC_CURPROG */
+#define IDAC_CURPROG_STEPSEL_DEFAULT                (_IDAC_CURPROG_STEPSEL_DEFAULT << 8)  /**< Shifted mode DEFAULT for IDAC_CURPROG */
+
+/* Bit fields for IDAC CAL */
+#define _IDAC_CAL_RESETVALUE                        0x00000000UL                    /**< Default value for IDAC_CAL */
+#define _IDAC_CAL_MASK                              0x0000007FUL                    /**< Mask for IDAC_CAL */
+#define _IDAC_CAL_TUNING_SHIFT                      0                               /**< Shift value for IDAC_TUNING */
+#define _IDAC_CAL_TUNING_MASK                       0x7FUL                          /**< Bit mask for IDAC_TUNING */
+#define _IDAC_CAL_TUNING_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for IDAC_CAL */
+#define IDAC_CAL_TUNING_DEFAULT                     (_IDAC_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CAL */
+
+/* Bit fields for IDAC DUTYCONFIG */
+#define _IDAC_DUTYCONFIG_RESETVALUE                 0x00000000UL                                    /**< Default value for IDAC_DUTYCONFIG */
+#define _IDAC_DUTYCONFIG_MASK                       0x00000003UL                                    /**< Mask for IDAC_DUTYCONFIG */
+#define IDAC_DUTYCONFIG_DUTYCYCLEEN                 (0x1UL << 0)                                    /**< Duty Cycle Enable. */
+#define _IDAC_DUTYCONFIG_DUTYCYCLEEN_SHIFT          0                                               /**< Shift value for IDAC_DUTYCYCLEEN */
+#define _IDAC_DUTYCONFIG_DUTYCYCLEEN_MASK           0x1UL                                           /**< Bit mask for IDAC_DUTYCYCLEEN */
+#define _IDAC_DUTYCONFIG_DUTYCYCLEEN_DEFAULT        0x00000000UL                                    /**< Mode DEFAULT for IDAC_DUTYCONFIG */
+#define IDAC_DUTYCONFIG_DUTYCYCLEEN_DEFAULT         (_IDAC_DUTYCONFIG_DUTYCYCLEEN_DEFAULT << 0)     /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
+#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS             (0x1UL << 1)                                    /**< EM2/EM3 Duty Cycle Disable. */
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT      1                                               /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK       0x2UL                                           /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT    0x00000000UL                                    /**< Mode DEFAULT for IDAC_DUTYCONFIG */
+#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT     (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
+
+/** @} End of group EFM32HG_IDAC */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_leuart.h

@@ -0,0 +1,705 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_LEUART register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_LEUART
+ * @{
+ * @brief EFM32HG_LEUART Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;           /**< Control Register  */
+  __IOM uint32_t CMD;            /**< Command Register  */
+  __IM uint32_t  STATUS;         /**< Status Register  */
+  __IOM uint32_t CLKDIV;         /**< Clock Control Register  */
+  __IOM uint32_t STARTFRAME;     /**< Start Frame Register  */
+  __IOM uint32_t SIGFRAME;       /**< Signal Frame Register  */
+  __IM uint32_t  RXDATAX;        /**< Receive Buffer Data Extended Register  */
+  __IM uint32_t  RXDATA;         /**< Receive Buffer Data Register  */
+  __IM uint32_t  RXDATAXP;       /**< Receive Buffer Data Extended Peek Register  */
+  __IOM uint32_t TXDATAX;        /**< Transmit Buffer Data Extended Register  */
+  __IOM uint32_t TXDATA;         /**< Transmit Buffer Data Register  */
+  __IM uint32_t  IF;             /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;            /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;            /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;            /**< Interrupt Enable Register  */
+  __IOM uint32_t PULSECTRL;      /**< Pulse Control Register  */
+
+  __IOM uint32_t FREEZE;         /**< Freeze Register  */
+  __IM uint32_t  SYNCBUSY;       /**< Synchronization Busy Register  */
+
+  uint32_t       RESERVED0[3U];  /**< Reserved for future use **/
+  __IOM uint32_t ROUTE;          /**< I/O Routing Register  */
+  uint32_t       RESERVED1[21U]; /**< Reserved for future use **/
+  __IOM uint32_t INPUT;          /**< LEUART Input Register  */
+} LEUART_TypeDef;                /**< LEUART Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_LEUART_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for LEUART CTRL */
+#define _LEUART_CTRL_RESETVALUE                  0x00000000UL                         /**< Default value for LEUART_CTRL */
+#define _LEUART_CTRL_MASK                        0x0000FFFFUL                         /**< Mask for LEUART_CTRL */
+#define LEUART_CTRL_AUTOTRI                      (0x1UL << 0)                         /**< Automatic Transmitter Tristate */
+#define _LEUART_CTRL_AUTOTRI_SHIFT               0                                    /**< Shift value for LEUART_AUTOTRI */
+#define _LEUART_CTRL_AUTOTRI_MASK                0x1UL                                /**< Bit mask for LEUART_AUTOTRI */
+#define _LEUART_CTRL_AUTOTRI_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_AUTOTRI_DEFAULT              (_LEUART_CTRL_AUTOTRI_DEFAULT << 0)  /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS                     (0x1UL << 1)                         /**< Data-Bit Mode */
+#define _LEUART_CTRL_DATABITS_SHIFT              1                                    /**< Shift value for LEUART_DATABITS */
+#define _LEUART_CTRL_DATABITS_MASK               0x2UL                                /**< Bit mask for LEUART_DATABITS */
+#define _LEUART_CTRL_DATABITS_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_DATABITS_EIGHT              0x00000000UL                         /**< Mode EIGHT for LEUART_CTRL */
+#define _LEUART_CTRL_DATABITS_NINE               0x00000001UL                         /**< Mode NINE for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS_DEFAULT             (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS_EIGHT               (_LEUART_CTRL_DATABITS_EIGHT << 1)   /**< Shifted mode EIGHT for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS_NINE                (_LEUART_CTRL_DATABITS_NINE << 1)    /**< Shifted mode NINE for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_SHIFT                2                                    /**< Shift value for LEUART_PARITY */
+#define _LEUART_CTRL_PARITY_MASK                 0xCUL                                /**< Bit mask for LEUART_PARITY */
+#define _LEUART_CTRL_PARITY_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_NONE                 0x00000000UL                         /**< Mode NONE for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_EVEN                 0x00000002UL                         /**< Mode EVEN for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_ODD                  0x00000003UL                         /**< Mode ODD for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_DEFAULT               (_LEUART_CTRL_PARITY_DEFAULT << 2)   /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_NONE                  (_LEUART_CTRL_PARITY_NONE << 2)      /**< Shifted mode NONE for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_EVEN                  (_LEUART_CTRL_PARITY_EVEN << 2)      /**< Shifted mode EVEN for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_ODD                   (_LEUART_CTRL_PARITY_ODD << 2)       /**< Shifted mode ODD for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS                     (0x1UL << 4)                         /**< Stop-Bit Mode */
+#define _LEUART_CTRL_STOPBITS_SHIFT              4                                    /**< Shift value for LEUART_STOPBITS */
+#define _LEUART_CTRL_STOPBITS_MASK               0x10UL                               /**< Bit mask for LEUART_STOPBITS */
+#define _LEUART_CTRL_STOPBITS_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_STOPBITS_ONE                0x00000000UL                         /**< Mode ONE for LEUART_CTRL */
+#define _LEUART_CTRL_STOPBITS_TWO                0x00000001UL                         /**< Mode TWO for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS_DEFAULT             (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS_ONE                 (_LEUART_CTRL_STOPBITS_ONE << 4)     /**< Shifted mode ONE for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS_TWO                 (_LEUART_CTRL_STOPBITS_TWO << 4)     /**< Shifted mode TWO for LEUART_CTRL */
+#define LEUART_CTRL_INV                          (0x1UL << 5)                         /**< Invert Input And Output */
+#define _LEUART_CTRL_INV_SHIFT                   5                                    /**< Shift value for LEUART_INV */
+#define _LEUART_CTRL_INV_MASK                    0x20UL                               /**< Bit mask for LEUART_INV */
+#define _LEUART_CTRL_INV_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_INV_DEFAULT                  (_LEUART_CTRL_INV_DEFAULT << 5)      /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_ERRSDMA                      (0x1UL << 6)                         /**< Clear RX DMA On Error */
+#define _LEUART_CTRL_ERRSDMA_SHIFT               6                                    /**< Shift value for LEUART_ERRSDMA */
+#define _LEUART_CTRL_ERRSDMA_MASK                0x40UL                               /**< Bit mask for LEUART_ERRSDMA */
+#define _LEUART_CTRL_ERRSDMA_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_ERRSDMA_DEFAULT              (_LEUART_CTRL_ERRSDMA_DEFAULT << 6)  /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_LOOPBK                       (0x1UL << 7)                         /**< Loopback Enable */
+#define _LEUART_CTRL_LOOPBK_SHIFT                7                                    /**< Shift value for LEUART_LOOPBK */
+#define _LEUART_CTRL_LOOPBK_MASK                 0x80UL                               /**< Bit mask for LEUART_LOOPBK */
+#define _LEUART_CTRL_LOOPBK_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_LOOPBK_DEFAULT               (_LEUART_CTRL_LOOPBK_DEFAULT << 7)   /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_SFUBRX                       (0x1UL << 8)                         /**< Start-Frame UnBlock RX */
+#define _LEUART_CTRL_SFUBRX_SHIFT                8                                    /**< Shift value for LEUART_SFUBRX */
+#define _LEUART_CTRL_SFUBRX_MASK                 0x100UL                              /**< Bit mask for LEUART_SFUBRX */
+#define _LEUART_CTRL_SFUBRX_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_SFUBRX_DEFAULT               (_LEUART_CTRL_SFUBRX_DEFAULT << 8)   /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPM                          (0x1UL << 9)                         /**< Multi-Processor Mode */
+#define _LEUART_CTRL_MPM_SHIFT                   9                                    /**< Shift value for LEUART_MPM */
+#define _LEUART_CTRL_MPM_MASK                    0x200UL                              /**< Bit mask for LEUART_MPM */
+#define _LEUART_CTRL_MPM_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPM_DEFAULT                  (_LEUART_CTRL_MPM_DEFAULT << 9)      /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPAB                         (0x1UL << 10)                        /**< Multi-Processor Address-Bit */
+#define _LEUART_CTRL_MPAB_SHIFT                  10                                   /**< Shift value for LEUART_MPAB */
+#define _LEUART_CTRL_MPAB_MASK                   0x400UL                              /**< Bit mask for LEUART_MPAB */
+#define _LEUART_CTRL_MPAB_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPAB_DEFAULT                 (_LEUART_CTRL_MPAB_DEFAULT << 10)    /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_BIT8DV                       (0x1UL << 11)                        /**< Bit 8 Default Value */
+#define _LEUART_CTRL_BIT8DV_SHIFT                11                                   /**< Shift value for LEUART_BIT8DV */
+#define _LEUART_CTRL_BIT8DV_MASK                 0x800UL                              /**< Bit mask for LEUART_BIT8DV */
+#define _LEUART_CTRL_BIT8DV_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_BIT8DV_DEFAULT               (_LEUART_CTRL_BIT8DV_DEFAULT << 11)  /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_RXDMAWU                      (0x1UL << 12)                        /**< RX DMA Wakeup */
+#define _LEUART_CTRL_RXDMAWU_SHIFT               12                                   /**< Shift value for LEUART_RXDMAWU */
+#define _LEUART_CTRL_RXDMAWU_MASK                0x1000UL                             /**< Bit mask for LEUART_RXDMAWU */
+#define _LEUART_CTRL_RXDMAWU_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_RXDMAWU_DEFAULT              (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_TXDMAWU                      (0x1UL << 13)                        /**< TX DMA Wakeup */
+#define _LEUART_CTRL_TXDMAWU_SHIFT               13                                   /**< Shift value for LEUART_TXDMAWU */
+#define _LEUART_CTRL_TXDMAWU_MASK                0x2000UL                             /**< Bit mask for LEUART_TXDMAWU */
+#define _LEUART_CTRL_TXDMAWU_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_TXDMAWU_DEFAULT              (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_SHIFT               14                                   /**< Shift value for LEUART_TXDELAY */
+#define _LEUART_CTRL_TXDELAY_MASK                0xC000UL                             /**< Bit mask for LEUART_TXDELAY */
+#define _LEUART_CTRL_TXDELAY_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_NONE                0x00000000UL                         /**< Mode NONE for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_SINGLE              0x00000001UL                         /**< Mode SINGLE for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_DOUBLE              0x00000002UL                         /**< Mode DOUBLE for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_TRIPLE              0x00000003UL                         /**< Mode TRIPLE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_DEFAULT              (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_NONE                 (_LEUART_CTRL_TXDELAY_NONE << 14)    /**< Shifted mode NONE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_SINGLE               (_LEUART_CTRL_TXDELAY_SINGLE << 14)  /**< Shifted mode SINGLE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_DOUBLE               (_LEUART_CTRL_TXDELAY_DOUBLE << 14)  /**< Shifted mode DOUBLE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_TRIPLE               (_LEUART_CTRL_TXDELAY_TRIPLE << 14)  /**< Shifted mode TRIPLE for LEUART_CTRL */
+
+/* Bit fields for LEUART CMD */
+#define _LEUART_CMD_RESETVALUE                   0x00000000UL                          /**< Default value for LEUART_CMD */
+#define _LEUART_CMD_MASK                         0x000000FFUL                          /**< Mask for LEUART_CMD */
+#define LEUART_CMD_RXEN                          (0x1UL << 0)                          /**< Receiver Enable */
+#define _LEUART_CMD_RXEN_SHIFT                   0                                     /**< Shift value for LEUART_RXEN */
+#define _LEUART_CMD_RXEN_MASK                    0x1UL                                 /**< Bit mask for LEUART_RXEN */
+#define _LEUART_CMD_RXEN_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXEN_DEFAULT                  (_LEUART_CMD_RXEN_DEFAULT << 0)       /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXDIS                         (0x1UL << 1)                          /**< Receiver Disable */
+#define _LEUART_CMD_RXDIS_SHIFT                  1                                     /**< Shift value for LEUART_RXDIS */
+#define _LEUART_CMD_RXDIS_MASK                   0x2UL                                 /**< Bit mask for LEUART_RXDIS */
+#define _LEUART_CMD_RXDIS_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXDIS_DEFAULT                 (_LEUART_CMD_RXDIS_DEFAULT << 1)      /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXEN                          (0x1UL << 2)                          /**< Transmitter Enable */
+#define _LEUART_CMD_TXEN_SHIFT                   2                                     /**< Shift value for LEUART_TXEN */
+#define _LEUART_CMD_TXEN_MASK                    0x4UL                                 /**< Bit mask for LEUART_TXEN */
+#define _LEUART_CMD_TXEN_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXEN_DEFAULT                  (_LEUART_CMD_TXEN_DEFAULT << 2)       /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXDIS                         (0x1UL << 3)                          /**< Transmitter Disable */
+#define _LEUART_CMD_TXDIS_SHIFT                  3                                     /**< Shift value for LEUART_TXDIS */
+#define _LEUART_CMD_TXDIS_MASK                   0x8UL                                 /**< Bit mask for LEUART_TXDIS */
+#define _LEUART_CMD_TXDIS_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXDIS_DEFAULT                 (_LEUART_CMD_TXDIS_DEFAULT << 3)      /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKEN                     (0x1UL << 4)                          /**< Receiver Block Enable */
+#define _LEUART_CMD_RXBLOCKEN_SHIFT              4                                     /**< Shift value for LEUART_RXBLOCKEN */
+#define _LEUART_CMD_RXBLOCKEN_MASK               0x10UL                                /**< Bit mask for LEUART_RXBLOCKEN */
+#define _LEUART_CMD_RXBLOCKEN_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKEN_DEFAULT             (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKDIS                    (0x1UL << 5)                          /**< Receiver Block Disable */
+#define _LEUART_CMD_RXBLOCKDIS_SHIFT             5                                     /**< Shift value for LEUART_RXBLOCKDIS */
+#define _LEUART_CMD_RXBLOCKDIS_MASK              0x20UL                                /**< Bit mask for LEUART_RXBLOCKDIS */
+#define _LEUART_CMD_RXBLOCKDIS_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKDIS_DEFAULT            (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARTX                       (0x1UL << 6)                          /**< Clear TX */
+#define _LEUART_CMD_CLEARTX_SHIFT                6                                     /**< Shift value for LEUART_CLEARTX */
+#define _LEUART_CMD_CLEARTX_MASK                 0x40UL                                /**< Bit mask for LEUART_CLEARTX */
+#define _LEUART_CMD_CLEARTX_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARTX_DEFAULT               (_LEUART_CMD_CLEARTX_DEFAULT << 6)    /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARRX                       (0x1UL << 7)                          /**< Clear RX */
+#define _LEUART_CMD_CLEARRX_SHIFT                7                                     /**< Shift value for LEUART_CLEARRX */
+#define _LEUART_CMD_CLEARRX_MASK                 0x80UL                                /**< Bit mask for LEUART_CLEARRX */
+#define _LEUART_CMD_CLEARRX_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARRX_DEFAULT               (_LEUART_CMD_CLEARRX_DEFAULT << 7)    /**< Shifted mode DEFAULT for LEUART_CMD */
+
+/* Bit fields for LEUART STATUS */
+#define _LEUART_STATUS_RESETVALUE                0x00000010UL                          /**< Default value for LEUART_STATUS */
+#define _LEUART_STATUS_MASK                      0x0000003FUL                          /**< Mask for LEUART_STATUS */
+#define LEUART_STATUS_RXENS                      (0x1UL << 0)                          /**< Receiver Enable Status */
+#define _LEUART_STATUS_RXENS_SHIFT               0                                     /**< Shift value for LEUART_RXENS */
+#define _LEUART_STATUS_RXENS_MASK                0x1UL                                 /**< Bit mask for LEUART_RXENS */
+#define _LEUART_STATUS_RXENS_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXENS_DEFAULT              (_LEUART_STATUS_RXENS_DEFAULT << 0)   /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXENS                      (0x1UL << 1)                          /**< Transmitter Enable Status */
+#define _LEUART_STATUS_TXENS_SHIFT               1                                     /**< Shift value for LEUART_TXENS */
+#define _LEUART_STATUS_TXENS_MASK                0x2UL                                 /**< Bit mask for LEUART_TXENS */
+#define _LEUART_STATUS_TXENS_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXENS_DEFAULT              (_LEUART_STATUS_TXENS_DEFAULT << 1)   /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXBLOCK                    (0x1UL << 2)                          /**< Block Incoming Data */
+#define _LEUART_STATUS_RXBLOCK_SHIFT             2                                     /**< Shift value for LEUART_RXBLOCK */
+#define _LEUART_STATUS_RXBLOCK_MASK              0x4UL                                 /**< Bit mask for LEUART_RXBLOCK */
+#define _LEUART_STATUS_RXBLOCK_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXBLOCK_DEFAULT            (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXC                        (0x1UL << 3)                          /**< TX Complete */
+#define _LEUART_STATUS_TXC_SHIFT                 3                                     /**< Shift value for LEUART_TXC */
+#define _LEUART_STATUS_TXC_MASK                  0x8UL                                 /**< Bit mask for LEUART_TXC */
+#define _LEUART_STATUS_TXC_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXC_DEFAULT                (_LEUART_STATUS_TXC_DEFAULT << 3)     /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXBL                       (0x1UL << 4)                          /**< TX Buffer Level */
+#define _LEUART_STATUS_TXBL_SHIFT                4                                     /**< Shift value for LEUART_TXBL */
+#define _LEUART_STATUS_TXBL_MASK                 0x10UL                                /**< Bit mask for LEUART_TXBL */
+#define _LEUART_STATUS_TXBL_DEFAULT              0x00000001UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXBL_DEFAULT               (_LEUART_STATUS_TXBL_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXDATAV                    (0x1UL << 5)                          /**< RX Data Valid */
+#define _LEUART_STATUS_RXDATAV_SHIFT             5                                     /**< Shift value for LEUART_RXDATAV */
+#define _LEUART_STATUS_RXDATAV_MASK              0x20UL                                /**< Bit mask for LEUART_RXDATAV */
+#define _LEUART_STATUS_RXDATAV_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXDATAV_DEFAULT            (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */
+
+/* Bit fields for LEUART CLKDIV */
+#define _LEUART_CLKDIV_RESETVALUE                0x00000000UL                      /**< Default value for LEUART_CLKDIV */
+#define _LEUART_CLKDIV_MASK                      0x00007FF8UL                      /**< Mask for LEUART_CLKDIV */
+#define _LEUART_CLKDIV_DIV_SHIFT                 3                                 /**< Shift value for LEUART_DIV */
+#define _LEUART_CLKDIV_DIV_MASK                  0x7FF8UL                          /**< Bit mask for LEUART_DIV */
+#define _LEUART_CLKDIV_DIV_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LEUART_CLKDIV */
+#define LEUART_CLKDIV_DIV_DEFAULT                (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */
+
+/* Bit fields for LEUART STARTFRAME */
+#define _LEUART_STARTFRAME_RESETVALUE            0x00000000UL                                 /**< Default value for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_MASK                  0x000001FFUL                                 /**< Mask for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_STARTFRAME_SHIFT      0                                            /**< Shift value for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_STARTFRAME_MASK       0x1FFUL                                      /**< Bit mask for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT    0x00000000UL                                 /**< Mode DEFAULT for LEUART_STARTFRAME */
+#define LEUART_STARTFRAME_STARTFRAME_DEFAULT     (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */
+
+/* Bit fields for LEUART SIGFRAME */
+#define _LEUART_SIGFRAME_RESETVALUE              0x00000000UL                             /**< Default value for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_MASK                    0x000001FFUL                             /**< Mask for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_SIGFRAME_SHIFT          0                                        /**< Shift value for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_SIGFRAME_MASK           0x1FFUL                                  /**< Bit mask for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for LEUART_SIGFRAME */
+#define LEUART_SIGFRAME_SIGFRAME_DEFAULT         (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */
+
+/* Bit fields for LEUART RXDATAX */
+#define _LEUART_RXDATAX_RESETVALUE               0x00000000UL                          /**< Default value for LEUART_RXDATAX */
+#define _LEUART_RXDATAX_MASK                     0x0000C1FFUL                          /**< Mask for LEUART_RXDATAX */
+#define _LEUART_RXDATAX_RXDATA_SHIFT             0                                     /**< Shift value for LEUART_RXDATA */
+#define _LEUART_RXDATAX_RXDATA_MASK              0x1FFUL                               /**< Bit mask for LEUART_RXDATA */
+#define _LEUART_RXDATAX_RXDATA_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_RXDATA_DEFAULT            (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_PERR                      (0x1UL << 14)                         /**< Receive Data Parity Error */
+#define _LEUART_RXDATAX_PERR_SHIFT               14                                    /**< Shift value for LEUART_PERR */
+#define _LEUART_RXDATAX_PERR_MASK                0x4000UL                              /**< Bit mask for LEUART_PERR */
+#define _LEUART_RXDATAX_PERR_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_PERR_DEFAULT              (_LEUART_RXDATAX_PERR_DEFAULT << 14)  /**< Shifted mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_FERR                      (0x1UL << 15)                         /**< Receive Data Framing Error */
+#define _LEUART_RXDATAX_FERR_SHIFT               15                                    /**< Shift value for LEUART_FERR */
+#define _LEUART_RXDATAX_FERR_MASK                0x8000UL                              /**< Bit mask for LEUART_FERR */
+#define _LEUART_RXDATAX_FERR_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_FERR_DEFAULT              (_LEUART_RXDATAX_FERR_DEFAULT << 15)  /**< Shifted mode DEFAULT for LEUART_RXDATAX */
+
+/* Bit fields for LEUART RXDATA */
+#define _LEUART_RXDATA_RESETVALUE                0x00000000UL                         /**< Default value for LEUART_RXDATA */
+#define _LEUART_RXDATA_MASK                      0x000000FFUL                         /**< Mask for LEUART_RXDATA */
+#define _LEUART_RXDATA_RXDATA_SHIFT              0                                    /**< Shift value for LEUART_RXDATA */
+#define _LEUART_RXDATA_RXDATA_MASK               0xFFUL                               /**< Bit mask for LEUART_RXDATA */
+#define _LEUART_RXDATA_RXDATA_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for LEUART_RXDATA */
+#define LEUART_RXDATA_RXDATA_DEFAULT             (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */
+
+/* Bit fields for LEUART RXDATAXP */
+#define _LEUART_RXDATAXP_RESETVALUE              0x00000000UL                            /**< Default value for LEUART_RXDATAXP */
+#define _LEUART_RXDATAXP_MASK                    0x0000C1FFUL                            /**< Mask for LEUART_RXDATAXP */
+#define _LEUART_RXDATAXP_RXDATAP_SHIFT           0                                       /**< Shift value for LEUART_RXDATAP */
+#define _LEUART_RXDATAXP_RXDATAP_MASK            0x1FFUL                                 /**< Bit mask for LEUART_RXDATAP */
+#define _LEUART_RXDATAXP_RXDATAP_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_RXDATAP_DEFAULT          (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_PERRP                    (0x1UL << 14)                           /**< Receive Data Parity Error Peek */
+#define _LEUART_RXDATAXP_PERRP_SHIFT             14                                      /**< Shift value for LEUART_PERRP */
+#define _LEUART_RXDATAXP_PERRP_MASK              0x4000UL                                /**< Bit mask for LEUART_PERRP */
+#define _LEUART_RXDATAXP_PERRP_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_PERRP_DEFAULT            (_LEUART_RXDATAXP_PERRP_DEFAULT << 14)  /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_FERRP                    (0x1UL << 15)                           /**< Receive Data Framing Error Peek */
+#define _LEUART_RXDATAXP_FERRP_SHIFT             15                                      /**< Shift value for LEUART_FERRP */
+#define _LEUART_RXDATAXP_FERRP_MASK              0x8000UL                                /**< Bit mask for LEUART_FERRP */
+#define _LEUART_RXDATAXP_FERRP_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_FERRP_DEFAULT            (_LEUART_RXDATAXP_FERRP_DEFAULT << 15)  /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
+
+/* Bit fields for LEUART TXDATAX */
+#define _LEUART_TXDATAX_RESETVALUE               0x00000000UL                            /**< Default value for LEUART_TXDATAX */
+#define _LEUART_TXDATAX_MASK                     0x0000E1FFUL                            /**< Mask for LEUART_TXDATAX */
+#define _LEUART_TXDATAX_TXDATA_SHIFT             0                                       /**< Shift value for LEUART_TXDATA */
+#define _LEUART_TXDATAX_TXDATA_MASK              0x1FFUL                                 /**< Bit mask for LEUART_TXDATA */
+#define _LEUART_TXDATAX_TXDATA_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXDATA_DEFAULT            (_LEUART_TXDATAX_TXDATA_DEFAULT << 0)   /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXBREAK                   (0x1UL << 13)                           /**< Transmit Data As Break */
+#define _LEUART_TXDATAX_TXBREAK_SHIFT            13                                      /**< Shift value for LEUART_TXBREAK */
+#define _LEUART_TXDATAX_TXBREAK_MASK             0x2000UL                                /**< Bit mask for LEUART_TXBREAK */
+#define _LEUART_TXDATAX_TXBREAK_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXBREAK_DEFAULT           (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXDISAT                   (0x1UL << 14)                           /**< Disable TX After Transmission */
+#define _LEUART_TXDATAX_TXDISAT_SHIFT            14                                      /**< Shift value for LEUART_TXDISAT */
+#define _LEUART_TXDATAX_TXDISAT_MASK             0x4000UL                                /**< Bit mask for LEUART_TXDISAT */
+#define _LEUART_TXDATAX_TXDISAT_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXDISAT_DEFAULT           (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_RXENAT                    (0x1UL << 15)                           /**< Enable RX After Transmission */
+#define _LEUART_TXDATAX_RXENAT_SHIFT             15                                      /**< Shift value for LEUART_RXENAT */
+#define _LEUART_TXDATAX_RXENAT_MASK              0x8000UL                                /**< Bit mask for LEUART_RXENAT */
+#define _LEUART_TXDATAX_RXENAT_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_RXENAT_DEFAULT            (_LEUART_TXDATAX_RXENAT_DEFAULT << 15)  /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+
+/* Bit fields for LEUART TXDATA */
+#define _LEUART_TXDATA_RESETVALUE                0x00000000UL                         /**< Default value for LEUART_TXDATA */
+#define _LEUART_TXDATA_MASK                      0x000000FFUL                         /**< Mask for LEUART_TXDATA */
+#define _LEUART_TXDATA_TXDATA_SHIFT              0                                    /**< Shift value for LEUART_TXDATA */
+#define _LEUART_TXDATA_TXDATA_MASK               0xFFUL                               /**< Bit mask for LEUART_TXDATA */
+#define _LEUART_TXDATA_TXDATA_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for LEUART_TXDATA */
+#define LEUART_TXDATA_TXDATA_DEFAULT             (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */
+
+/* Bit fields for LEUART IF */
+#define _LEUART_IF_RESETVALUE                    0x00000002UL                      /**< Default value for LEUART_IF */
+#define _LEUART_IF_MASK                          0x000007FFUL                      /**< Mask for LEUART_IF */
+#define LEUART_IF_TXC                            (0x1UL << 0)                      /**< TX Complete Interrupt Flag */
+#define _LEUART_IF_TXC_SHIFT                     0                                 /**< Shift value for LEUART_TXC */
+#define _LEUART_IF_TXC_MASK                      0x1UL                             /**< Bit mask for LEUART_TXC */
+#define _LEUART_IF_TXC_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXC_DEFAULT                    (_LEUART_IF_TXC_DEFAULT << 0)     /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXBL                           (0x1UL << 1)                      /**< TX Buffer Level Interrupt Flag */
+#define _LEUART_IF_TXBL_SHIFT                    1                                 /**< Shift value for LEUART_TXBL */
+#define _LEUART_IF_TXBL_MASK                     0x2UL                             /**< Bit mask for LEUART_TXBL */
+#define _LEUART_IF_TXBL_DEFAULT                  0x00000001UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXBL_DEFAULT                   (_LEUART_IF_TXBL_DEFAULT << 1)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXDATAV                        (0x1UL << 2)                      /**< RX Data Valid Interrupt Flag */
+#define _LEUART_IF_RXDATAV_SHIFT                 2                                 /**< Shift value for LEUART_RXDATAV */
+#define _LEUART_IF_RXDATAV_MASK                  0x4UL                             /**< Bit mask for LEUART_RXDATAV */
+#define _LEUART_IF_RXDATAV_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXDATAV_DEFAULT                (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXOF                           (0x1UL << 3)                      /**< RX Overflow Interrupt Flag */
+#define _LEUART_IF_RXOF_SHIFT                    3                                 /**< Shift value for LEUART_RXOF */
+#define _LEUART_IF_RXOF_MASK                     0x8UL                             /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IF_RXOF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXOF_DEFAULT                   (_LEUART_IF_RXOF_DEFAULT << 3)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXUF                           (0x1UL << 4)                      /**< RX Underflow Interrupt Flag */
+#define _LEUART_IF_RXUF_SHIFT                    4                                 /**< Shift value for LEUART_RXUF */
+#define _LEUART_IF_RXUF_MASK                     0x10UL                            /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IF_RXUF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXUF_DEFAULT                   (_LEUART_IF_RXUF_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXOF                           (0x1UL << 5)                      /**< TX Overflow Interrupt Flag */
+#define _LEUART_IF_TXOF_SHIFT                    5                                 /**< Shift value for LEUART_TXOF */
+#define _LEUART_IF_TXOF_MASK                     0x20UL                            /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IF_TXOF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXOF_DEFAULT                   (_LEUART_IF_TXOF_DEFAULT << 5)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_PERR                           (0x1UL << 6)                      /**< Parity Error Interrupt Flag */
+#define _LEUART_IF_PERR_SHIFT                    6                                 /**< Shift value for LEUART_PERR */
+#define _LEUART_IF_PERR_MASK                     0x40UL                            /**< Bit mask for LEUART_PERR */
+#define _LEUART_IF_PERR_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_PERR_DEFAULT                   (_LEUART_IF_PERR_DEFAULT << 6)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_FERR                           (0x1UL << 7)                      /**< Framing Error Interrupt Flag */
+#define _LEUART_IF_FERR_SHIFT                    7                                 /**< Shift value for LEUART_FERR */
+#define _LEUART_IF_FERR_MASK                     0x80UL                            /**< Bit mask for LEUART_FERR */
+#define _LEUART_IF_FERR_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_FERR_DEFAULT                   (_LEUART_IF_FERR_DEFAULT << 7)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_MPAF                           (0x1UL << 8)                      /**< Multi-Processor Address Frame Interrupt Flag */
+#define _LEUART_IF_MPAF_SHIFT                    8                                 /**< Shift value for LEUART_MPAF */
+#define _LEUART_IF_MPAF_MASK                     0x100UL                           /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IF_MPAF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_MPAF_DEFAULT                   (_LEUART_IF_MPAF_DEFAULT << 8)    /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_STARTF                         (0x1UL << 9)                      /**< Start Frame Interrupt Flag */
+#define _LEUART_IF_STARTF_SHIFT                  9                                 /**< Shift value for LEUART_STARTF */
+#define _LEUART_IF_STARTF_MASK                   0x200UL                           /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IF_STARTF_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_STARTF_DEFAULT                 (_LEUART_IF_STARTF_DEFAULT << 9)  /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_SIGF                           (0x1UL << 10)                     /**< Signal Frame Interrupt Flag */
+#define _LEUART_IF_SIGF_SHIFT                    10                                /**< Shift value for LEUART_SIGF */
+#define _LEUART_IF_SIGF_MASK                     0x400UL                           /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IF_SIGF_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_SIGF_DEFAULT                   (_LEUART_IF_SIGF_DEFAULT << 10)   /**< Shifted mode DEFAULT for LEUART_IF */
+
+/* Bit fields for LEUART IFS */
+#define _LEUART_IFS_RESETVALUE                   0x00000000UL                      /**< Default value for LEUART_IFS */
+#define _LEUART_IFS_MASK                         0x000007F9UL                      /**< Mask for LEUART_IFS */
+#define LEUART_IFS_TXC                           (0x1UL << 0)                      /**< Set TX Complete Interrupt Flag */
+#define _LEUART_IFS_TXC_SHIFT                    0                                 /**< Shift value for LEUART_TXC */
+#define _LEUART_IFS_TXC_MASK                     0x1UL                             /**< Bit mask for LEUART_TXC */
+#define _LEUART_IFS_TXC_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_TXC_DEFAULT                   (_LEUART_IFS_TXC_DEFAULT << 0)    /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXOF                          (0x1UL << 3)                      /**< Set RX Overflow Interrupt Flag */
+#define _LEUART_IFS_RXOF_SHIFT                   3                                 /**< Shift value for LEUART_RXOF */
+#define _LEUART_IFS_RXOF_MASK                    0x8UL                             /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IFS_RXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXOF_DEFAULT                  (_LEUART_IFS_RXOF_DEFAULT << 3)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXUF                          (0x1UL << 4)                      /**< Set RX Underflow Interrupt Flag */
+#define _LEUART_IFS_RXUF_SHIFT                   4                                 /**< Shift value for LEUART_RXUF */
+#define _LEUART_IFS_RXUF_MASK                    0x10UL                            /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IFS_RXUF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXUF_DEFAULT                  (_LEUART_IFS_RXUF_DEFAULT << 4)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_TXOF                          (0x1UL << 5)                      /**< Set TX Overflow Interrupt Flag */
+#define _LEUART_IFS_TXOF_SHIFT                   5                                 /**< Shift value for LEUART_TXOF */
+#define _LEUART_IFS_TXOF_MASK                    0x20UL                            /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IFS_TXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_TXOF_DEFAULT                  (_LEUART_IFS_TXOF_DEFAULT << 5)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_PERR                          (0x1UL << 6)                      /**< Set Parity Error Interrupt Flag */
+#define _LEUART_IFS_PERR_SHIFT                   6                                 /**< Shift value for LEUART_PERR */
+#define _LEUART_IFS_PERR_MASK                    0x40UL                            /**< Bit mask for LEUART_PERR */
+#define _LEUART_IFS_PERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_PERR_DEFAULT                  (_LEUART_IFS_PERR_DEFAULT << 6)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_FERR                          (0x1UL << 7)                      /**< Set Framing Error Interrupt Flag */
+#define _LEUART_IFS_FERR_SHIFT                   7                                 /**< Shift value for LEUART_FERR */
+#define _LEUART_IFS_FERR_MASK                    0x80UL                            /**< Bit mask for LEUART_FERR */
+#define _LEUART_IFS_FERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_FERR_DEFAULT                  (_LEUART_IFS_FERR_DEFAULT << 7)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_MPAF                          (0x1UL << 8)                      /**< Set Multi-Processor Address Frame Interrupt Flag */
+#define _LEUART_IFS_MPAF_SHIFT                   8                                 /**< Shift value for LEUART_MPAF */
+#define _LEUART_IFS_MPAF_MASK                    0x100UL                           /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IFS_MPAF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_MPAF_DEFAULT                  (_LEUART_IFS_MPAF_DEFAULT << 8)   /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_STARTF                        (0x1UL << 9)                      /**< Set Start Frame Interrupt Flag */
+#define _LEUART_IFS_STARTF_SHIFT                 9                                 /**< Shift value for LEUART_STARTF */
+#define _LEUART_IFS_STARTF_MASK                  0x200UL                           /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IFS_STARTF_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_STARTF_DEFAULT                (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_SIGF                          (0x1UL << 10)                     /**< Set Signal Frame Interrupt Flag */
+#define _LEUART_IFS_SIGF_SHIFT                   10                                /**< Shift value for LEUART_SIGF */
+#define _LEUART_IFS_SIGF_MASK                    0x400UL                           /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IFS_SIGF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_SIGF_DEFAULT                  (_LEUART_IFS_SIGF_DEFAULT << 10)  /**< Shifted mode DEFAULT for LEUART_IFS */
+
+/* Bit fields for LEUART IFC */
+#define _LEUART_IFC_RESETVALUE                   0x00000000UL                      /**< Default value for LEUART_IFC */
+#define _LEUART_IFC_MASK                         0x000007F9UL                      /**< Mask for LEUART_IFC */
+#define LEUART_IFC_TXC                           (0x1UL << 0)                      /**< Clear TX Complete Interrupt Flag */
+#define _LEUART_IFC_TXC_SHIFT                    0                                 /**< Shift value for LEUART_TXC */
+#define _LEUART_IFC_TXC_MASK                     0x1UL                             /**< Bit mask for LEUART_TXC */
+#define _LEUART_IFC_TXC_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_TXC_DEFAULT                   (_LEUART_IFC_TXC_DEFAULT << 0)    /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXOF                          (0x1UL << 3)                      /**< Clear RX Overflow Interrupt Flag */
+#define _LEUART_IFC_RXOF_SHIFT                   3                                 /**< Shift value for LEUART_RXOF */
+#define _LEUART_IFC_RXOF_MASK                    0x8UL                             /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IFC_RXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXOF_DEFAULT                  (_LEUART_IFC_RXOF_DEFAULT << 3)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXUF                          (0x1UL << 4)                      /**< Clear RX Underflow Interrupt Flag */
+#define _LEUART_IFC_RXUF_SHIFT                   4                                 /**< Shift value for LEUART_RXUF */
+#define _LEUART_IFC_RXUF_MASK                    0x10UL                            /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IFC_RXUF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXUF_DEFAULT                  (_LEUART_IFC_RXUF_DEFAULT << 4)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_TXOF                          (0x1UL << 5)                      /**< Clear TX Overflow Interrupt Flag */
+#define _LEUART_IFC_TXOF_SHIFT                   5                                 /**< Shift value for LEUART_TXOF */
+#define _LEUART_IFC_TXOF_MASK                    0x20UL                            /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IFC_TXOF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_TXOF_DEFAULT                  (_LEUART_IFC_TXOF_DEFAULT << 5)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_PERR                          (0x1UL << 6)                      /**< Clear Parity Error Interrupt Flag */
+#define _LEUART_IFC_PERR_SHIFT                   6                                 /**< Shift value for LEUART_PERR */
+#define _LEUART_IFC_PERR_MASK                    0x40UL                            /**< Bit mask for LEUART_PERR */
+#define _LEUART_IFC_PERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_PERR_DEFAULT                  (_LEUART_IFC_PERR_DEFAULT << 6)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_FERR                          (0x1UL << 7)                      /**< Clear Framing Error Interrupt Flag */
+#define _LEUART_IFC_FERR_SHIFT                   7                                 /**< Shift value for LEUART_FERR */
+#define _LEUART_IFC_FERR_MASK                    0x80UL                            /**< Bit mask for LEUART_FERR */
+#define _LEUART_IFC_FERR_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_FERR_DEFAULT                  (_LEUART_IFC_FERR_DEFAULT << 7)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_MPAF                          (0x1UL << 8)                      /**< Clear Multi-Processor Address Frame Interrupt Flag */
+#define _LEUART_IFC_MPAF_SHIFT                   8                                 /**< Shift value for LEUART_MPAF */
+#define _LEUART_IFC_MPAF_MASK                    0x100UL                           /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IFC_MPAF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_MPAF_DEFAULT                  (_LEUART_IFC_MPAF_DEFAULT << 8)   /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_STARTF                        (0x1UL << 9)                      /**< Clear Start-Frame Interrupt Flag */
+#define _LEUART_IFC_STARTF_SHIFT                 9                                 /**< Shift value for LEUART_STARTF */
+#define _LEUART_IFC_STARTF_MASK                  0x200UL                           /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IFC_STARTF_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_STARTF_DEFAULT                (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_SIGF                          (0x1UL << 10)                     /**< Clear Signal-Frame Interrupt Flag */
+#define _LEUART_IFC_SIGF_SHIFT                   10                                /**< Shift value for LEUART_SIGF */
+#define _LEUART_IFC_SIGF_MASK                    0x400UL                           /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IFC_SIGF_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_SIGF_DEFAULT                  (_LEUART_IFC_SIGF_DEFAULT << 10)  /**< Shifted mode DEFAULT for LEUART_IFC */
+
+/* Bit fields for LEUART IEN */
+#define _LEUART_IEN_RESETVALUE                   0x00000000UL                       /**< Default value for LEUART_IEN */
+#define _LEUART_IEN_MASK                         0x000007FFUL                       /**< Mask for LEUART_IEN */
+#define LEUART_IEN_TXC                           (0x1UL << 0)                       /**< TX Complete Interrupt Enable */
+#define _LEUART_IEN_TXC_SHIFT                    0                                  /**< Shift value for LEUART_TXC */
+#define _LEUART_IEN_TXC_MASK                     0x1UL                              /**< Bit mask for LEUART_TXC */
+#define _LEUART_IEN_TXC_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXC_DEFAULT                   (_LEUART_IEN_TXC_DEFAULT << 0)     /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXBL                          (0x1UL << 1)                       /**< TX Buffer Level Interrupt Enable */
+#define _LEUART_IEN_TXBL_SHIFT                   1                                  /**< Shift value for LEUART_TXBL */
+#define _LEUART_IEN_TXBL_MASK                    0x2UL                              /**< Bit mask for LEUART_TXBL */
+#define _LEUART_IEN_TXBL_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXBL_DEFAULT                  (_LEUART_IEN_TXBL_DEFAULT << 1)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXDATAV                       (0x1UL << 2)                       /**< RX Data Valid Interrupt Enable */
+#define _LEUART_IEN_RXDATAV_SHIFT                2                                  /**< Shift value for LEUART_RXDATAV */
+#define _LEUART_IEN_RXDATAV_MASK                 0x4UL                              /**< Bit mask for LEUART_RXDATAV */
+#define _LEUART_IEN_RXDATAV_DEFAULT              0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXDATAV_DEFAULT               (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXOF                          (0x1UL << 3)                       /**< RX Overflow Interrupt Enable */
+#define _LEUART_IEN_RXOF_SHIFT                   3                                  /**< Shift value for LEUART_RXOF */
+#define _LEUART_IEN_RXOF_MASK                    0x8UL                              /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IEN_RXOF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXOF_DEFAULT                  (_LEUART_IEN_RXOF_DEFAULT << 3)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXUF                          (0x1UL << 4)                       /**< RX Underflow Interrupt Enable */
+#define _LEUART_IEN_RXUF_SHIFT                   4                                  /**< Shift value for LEUART_RXUF */
+#define _LEUART_IEN_RXUF_MASK                    0x10UL                             /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IEN_RXUF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXUF_DEFAULT                  (_LEUART_IEN_RXUF_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXOF                          (0x1UL << 5)                       /**< TX Overflow Interrupt Enable */
+#define _LEUART_IEN_TXOF_SHIFT                   5                                  /**< Shift value for LEUART_TXOF */
+#define _LEUART_IEN_TXOF_MASK                    0x20UL                             /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IEN_TXOF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXOF_DEFAULT                  (_LEUART_IEN_TXOF_DEFAULT << 5)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_PERR                          (0x1UL << 6)                       /**< Parity Error Interrupt Enable */
+#define _LEUART_IEN_PERR_SHIFT                   6                                  /**< Shift value for LEUART_PERR */
+#define _LEUART_IEN_PERR_MASK                    0x40UL                             /**< Bit mask for LEUART_PERR */
+#define _LEUART_IEN_PERR_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_PERR_DEFAULT                  (_LEUART_IEN_PERR_DEFAULT << 6)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_FERR                          (0x1UL << 7)                       /**< Framing Error Interrupt Enable */
+#define _LEUART_IEN_FERR_SHIFT                   7                                  /**< Shift value for LEUART_FERR */
+#define _LEUART_IEN_FERR_MASK                    0x80UL                             /**< Bit mask for LEUART_FERR */
+#define _LEUART_IEN_FERR_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_FERR_DEFAULT                  (_LEUART_IEN_FERR_DEFAULT << 7)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_MPAF                          (0x1UL << 8)                       /**< Multi-Processor Address Frame Interrupt Enable */
+#define _LEUART_IEN_MPAF_SHIFT                   8                                  /**< Shift value for LEUART_MPAF */
+#define _LEUART_IEN_MPAF_MASK                    0x100UL                            /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IEN_MPAF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_MPAF_DEFAULT                  (_LEUART_IEN_MPAF_DEFAULT << 8)    /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_STARTF                        (0x1UL << 9)                       /**< Start Frame Interrupt Enable */
+#define _LEUART_IEN_STARTF_SHIFT                 9                                  /**< Shift value for LEUART_STARTF */
+#define _LEUART_IEN_STARTF_MASK                  0x200UL                            /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IEN_STARTF_DEFAULT               0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_STARTF_DEFAULT                (_LEUART_IEN_STARTF_DEFAULT << 9)  /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_SIGF                          (0x1UL << 10)                      /**< Signal Frame Interrupt Enable */
+#define _LEUART_IEN_SIGF_SHIFT                   10                                 /**< Shift value for LEUART_SIGF */
+#define _LEUART_IEN_SIGF_MASK                    0x400UL                            /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IEN_SIGF_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_SIGF_DEFAULT                  (_LEUART_IEN_SIGF_DEFAULT << 10)   /**< Shifted mode DEFAULT for LEUART_IEN */
+
+/* Bit fields for LEUART PULSECTRL */
+#define _LEUART_PULSECTRL_RESETVALUE             0x00000000UL                               /**< Default value for LEUART_PULSECTRL */
+#define _LEUART_PULSECTRL_MASK                   0x0000003FUL                               /**< Mask for LEUART_PULSECTRL */
+#define _LEUART_PULSECTRL_PULSEW_SHIFT           0                                          /**< Shift value for LEUART_PULSEW */
+#define _LEUART_PULSECTRL_PULSEW_MASK            0xFUL                                      /**< Bit mask for LEUART_PULSEW */
+#define _LEUART_PULSECTRL_PULSEW_DEFAULT         0x00000000UL                               /**< Mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEW_DEFAULT          (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0)    /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEEN                 (0x1UL << 4)                               /**< Pulse Generator/Extender Enable */
+#define _LEUART_PULSECTRL_PULSEEN_SHIFT          4                                          /**< Shift value for LEUART_PULSEEN */
+#define _LEUART_PULSECTRL_PULSEEN_MASK           0x10UL                                     /**< Bit mask for LEUART_PULSEEN */
+#define _LEUART_PULSECTRL_PULSEEN_DEFAULT        0x00000000UL                               /**< Mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEEN_DEFAULT         (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4)   /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEFILT               (0x1UL << 5)                               /**< Pulse Filter */
+#define _LEUART_PULSECTRL_PULSEFILT_SHIFT        5                                          /**< Shift value for LEUART_PULSEFILT */
+#define _LEUART_PULSECTRL_PULSEFILT_MASK         0x20UL                                     /**< Bit mask for LEUART_PULSEFILT */
+#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT      0x00000000UL                               /**< Mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEFILT_DEFAULT       (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
+
+/* Bit fields for LEUART FREEZE */
+#define _LEUART_FREEZE_RESETVALUE                0x00000000UL                            /**< Default value for LEUART_FREEZE */
+#define _LEUART_FREEZE_MASK                      0x00000001UL                            /**< Mask for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE                  (0x1UL << 0)                            /**< Register Update Freeze */
+#define _LEUART_FREEZE_REGFREEZE_SHIFT           0                                       /**< Shift value for LEUART_REGFREEZE */
+#define _LEUART_FREEZE_REGFREEZE_MASK            0x1UL                                   /**< Bit mask for LEUART_REGFREEZE */
+#define _LEUART_FREEZE_REGFREEZE_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for LEUART_FREEZE */
+#define _LEUART_FREEZE_REGFREEZE_UPDATE          0x00000000UL                            /**< Mode UPDATE for LEUART_FREEZE */
+#define _LEUART_FREEZE_REGFREEZE_FREEZE          0x00000001UL                            /**< Mode FREEZE for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE_DEFAULT          (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE_UPDATE           (_LEUART_FREEZE_REGFREEZE_UPDATE << 0)  /**< Shifted mode UPDATE for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE_FREEZE           (_LEUART_FREEZE_REGFREEZE_FREEZE << 0)  /**< Shifted mode FREEZE for LEUART_FREEZE */
+
+/* Bit fields for LEUART SYNCBUSY */
+#define _LEUART_SYNCBUSY_RESETVALUE              0x00000000UL                               /**< Default value for LEUART_SYNCBUSY */
+#define _LEUART_SYNCBUSY_MASK                    0x000000FFUL                               /**< Mask for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CTRL                     (0x1UL << 0)                               /**< CTRL Register Busy */
+#define _LEUART_SYNCBUSY_CTRL_SHIFT              0                                          /**< Shift value for LEUART_CTRL */
+#define _LEUART_SYNCBUSY_CTRL_MASK               0x1UL                                      /**< Bit mask for LEUART_CTRL */
+#define _LEUART_SYNCBUSY_CTRL_DEFAULT            0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CTRL_DEFAULT             (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0)       /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CMD                      (0x1UL << 1)                               /**< CMD Register Busy */
+#define _LEUART_SYNCBUSY_CMD_SHIFT               1                                          /**< Shift value for LEUART_CMD */
+#define _LEUART_SYNCBUSY_CMD_MASK                0x2UL                                      /**< Bit mask for LEUART_CMD */
+#define _LEUART_SYNCBUSY_CMD_DEFAULT             0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CMD_DEFAULT              (_LEUART_SYNCBUSY_CMD_DEFAULT << 1)        /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CLKDIV                   (0x1UL << 2)                               /**< CLKDIV Register Busy */
+#define _LEUART_SYNCBUSY_CLKDIV_SHIFT            2                                          /**< Shift value for LEUART_CLKDIV */
+#define _LEUART_SYNCBUSY_CLKDIV_MASK             0x4UL                                      /**< Bit mask for LEUART_CLKDIV */
+#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CLKDIV_DEFAULT           (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2)     /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_STARTFRAME               (0x1UL << 3)                               /**< STARTFRAME Register Busy */
+#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT        3                                          /**< Shift value for LEUART_STARTFRAME */
+#define _LEUART_SYNCBUSY_STARTFRAME_MASK         0x8UL                                      /**< Bit mask for LEUART_STARTFRAME */
+#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT      0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT       (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_SIGFRAME                 (0x1UL << 4)                               /**< SIGFRAME Register Busy */
+#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT          4                                          /**< Shift value for LEUART_SIGFRAME */
+#define _LEUART_SYNCBUSY_SIGFRAME_MASK           0x10UL                                     /**< Bit mask for LEUART_SIGFRAME */
+#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT        0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT         (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4)   /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATAX                  (0x1UL << 5)                               /**< TXDATAX Register Busy */
+#define _LEUART_SYNCBUSY_TXDATAX_SHIFT           5                                          /**< Shift value for LEUART_TXDATAX */
+#define _LEUART_SYNCBUSY_TXDATAX_MASK            0x20UL                                     /**< Bit mask for LEUART_TXDATAX */
+#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT         0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATAX_DEFAULT          (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5)    /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATA                   (0x1UL << 6)                               /**< TXDATA Register Busy */
+#define _LEUART_SYNCBUSY_TXDATA_SHIFT            6                                          /**< Shift value for LEUART_TXDATA */
+#define _LEUART_SYNCBUSY_TXDATA_MASK             0x40UL                                     /**< Bit mask for LEUART_TXDATA */
+#define _LEUART_SYNCBUSY_TXDATA_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATA_DEFAULT           (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6)     /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_PULSECTRL                (0x1UL << 7)                               /**< PULSECTRL Register Busy */
+#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT         7                                          /**< Shift value for LEUART_PULSECTRL */
+#define _LEUART_SYNCBUSY_PULSECTRL_MASK          0x80UL                                     /**< Bit mask for LEUART_PULSECTRL */
+#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT       0x00000000UL                               /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT        (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7)  /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+
+/* Bit fields for LEUART ROUTE */
+#define _LEUART_ROUTE_RESETVALUE                 0x00000000UL                          /**< Default value for LEUART_ROUTE */
+#define _LEUART_ROUTE_MASK                       0x00000703UL                          /**< Mask for LEUART_ROUTE */
+#define LEUART_ROUTE_RXPEN                       (0x1UL << 0)                          /**< RX Pin Enable */
+#define _LEUART_ROUTE_RXPEN_SHIFT                0                                     /**< Shift value for LEUART_RXPEN */
+#define _LEUART_ROUTE_RXPEN_MASK                 0x1UL                                 /**< Bit mask for LEUART_RXPEN */
+#define _LEUART_ROUTE_RXPEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for LEUART_ROUTE */
+#define LEUART_ROUTE_RXPEN_DEFAULT               (_LEUART_ROUTE_RXPEN_DEFAULT << 0)    /**< Shifted mode DEFAULT for LEUART_ROUTE */
+#define LEUART_ROUTE_TXPEN                       (0x1UL << 1)                          /**< TX Pin Enable */
+#define _LEUART_ROUTE_TXPEN_SHIFT                1                                     /**< Shift value for LEUART_TXPEN */
+#define _LEUART_ROUTE_TXPEN_MASK                 0x2UL                                 /**< Bit mask for LEUART_TXPEN */
+#define _LEUART_ROUTE_TXPEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for LEUART_ROUTE */
+#define LEUART_ROUTE_TXPEN_DEFAULT               (_LEUART_ROUTE_TXPEN_DEFAULT << 1)    /**< Shifted mode DEFAULT for LEUART_ROUTE */
+#define _LEUART_ROUTE_LOCATION_SHIFT             8                                     /**< Shift value for LEUART_LOCATION */
+#define _LEUART_ROUTE_LOCATION_MASK              0x700UL                               /**< Bit mask for LEUART_LOCATION */
+#define _LEUART_ROUTE_LOCATION_LOC0              0x00000000UL                          /**< Mode LOC0 for LEUART_ROUTE */
+#define _LEUART_ROUTE_LOCATION_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_ROUTE */
+#define _LEUART_ROUTE_LOCATION_LOC1              0x00000001UL                          /**< Mode LOC1 for LEUART_ROUTE */
+#define _LEUART_ROUTE_LOCATION_LOC2              0x00000002UL                          /**< Mode LOC2 for LEUART_ROUTE */
+#define _LEUART_ROUTE_LOCATION_LOC3              0x00000003UL                          /**< Mode LOC3 for LEUART_ROUTE */
+#define _LEUART_ROUTE_LOCATION_LOC4              0x00000004UL                          /**< Mode LOC4 for LEUART_ROUTE */
+#define _LEUART_ROUTE_LOCATION_LOC5              0x00000005UL                          /**< Mode LOC5 for LEUART_ROUTE */
+#define LEUART_ROUTE_LOCATION_LOC0               (_LEUART_ROUTE_LOCATION_LOC0 << 8)    /**< Shifted mode LOC0 for LEUART_ROUTE */
+#define LEUART_ROUTE_LOCATION_DEFAULT            (_LEUART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTE */
+#define LEUART_ROUTE_LOCATION_LOC1               (_LEUART_ROUTE_LOCATION_LOC1 << 8)    /**< Shifted mode LOC1 for LEUART_ROUTE */
+#define LEUART_ROUTE_LOCATION_LOC2               (_LEUART_ROUTE_LOCATION_LOC2 << 8)    /**< Shifted mode LOC2 for LEUART_ROUTE */
+#define LEUART_ROUTE_LOCATION_LOC3               (_LEUART_ROUTE_LOCATION_LOC3 << 8)    /**< Shifted mode LOC3 for LEUART_ROUTE */
+#define LEUART_ROUTE_LOCATION_LOC4               (_LEUART_ROUTE_LOCATION_LOC4 << 8)    /**< Shifted mode LOC4 for LEUART_ROUTE */
+#define LEUART_ROUTE_LOCATION_LOC5               (_LEUART_ROUTE_LOCATION_LOC5 << 8)    /**< Shifted mode LOC5 for LEUART_ROUTE */
+
+/* Bit fields for LEUART INPUT */
+#define _LEUART_INPUT_RESETVALUE                 0x00000000UL                          /**< Default value for LEUART_INPUT */
+#define _LEUART_INPUT_MASK                       0x00000017UL                          /**< Mask for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_SHIFT             0                                     /**< Shift value for LEUART_RXPRSSEL */
+#define _LEUART_INPUT_RXPRSSEL_MASK              0x7UL                                 /**< Bit mask for LEUART_RXPRSSEL */
+#define _LEUART_INPUT_RXPRSSEL_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH0            0x00000000UL                          /**< Mode PRSCH0 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH1            0x00000001UL                          /**< Mode PRSCH1 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH2            0x00000002UL                          /**< Mode PRSCH2 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH3            0x00000003UL                          /**< Mode PRSCH3 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH4            0x00000004UL                          /**< Mode PRSCH4 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH5            0x00000005UL                          /**< Mode PRSCH5 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_DEFAULT            (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH0             (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0)  /**< Shifted mode PRSCH0 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH1             (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0)  /**< Shifted mode PRSCH1 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH2             (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0)  /**< Shifted mode PRSCH2 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH3             (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0)  /**< Shifted mode PRSCH3 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH4             (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0)  /**< Shifted mode PRSCH4 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH5             (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0)  /**< Shifted mode PRSCH5 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRS                       (0x1UL << 4)                          /**< PRS RX Enable */
+#define _LEUART_INPUT_RXPRS_SHIFT                4                                     /**< Shift value for LEUART_RXPRS */
+#define _LEUART_INPUT_RXPRS_MASK                 0x10UL                                /**< Bit mask for LEUART_RXPRS */
+#define _LEUART_INPUT_RXPRS_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for LEUART_INPUT */
+#define LEUART_INPUT_RXPRS_DEFAULT               (_LEUART_INPUT_RXPRS_DEFAULT << 4)    /**< Shifted mode DEFAULT for LEUART_INPUT */
+
+/** @} End of group EFM32HG_LEUART */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_msc.h

@@ -0,0 +1,428 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_MSC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_MSC
+ * @{
+ * @brief EFM32HG_MSC Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;          /**< Memory System Control Register  */
+  __IOM uint32_t READCTRL;      /**< Read Control Register  */
+  __IOM uint32_t WRITECTRL;     /**< Write Control Register  */
+  __IOM uint32_t WRITECMD;      /**< Write Command Register  */
+  __IOM uint32_t ADDRB;         /**< Page Erase/Write Address Buffer  */
+
+  uint32_t       RESERVED0[1U]; /**< Reserved for future use **/
+  __IOM uint32_t WDATA;         /**< Write Data Register  */
+  __IM uint32_t  STATUS;        /**< Status Register  */
+
+  uint32_t       RESERVED1[3U]; /**< Reserved for future use **/
+  __IM uint32_t  IF;            /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;           /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;           /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;           /**< Interrupt Enable Register  */
+  __IOM uint32_t LOCK;          /**< Configuration Lock Register  */
+  __IOM uint32_t CMD;           /**< Command Register  */
+  __IM uint32_t  CACHEHITS;     /**< Cache Hits Performance Counter  */
+  __IM uint32_t  CACHEMISSES;   /**< Cache Misses Performance Counter  */
+  uint32_t       RESERVED2[1U]; /**< Reserved for future use **/
+  __IOM uint32_t TIMEBASE;      /**< Flash Write and Erase Timebase  */
+  __IOM uint32_t MASSLOCK;      /**< Mass Erase Lock Register  */
+  __IOM uint32_t IRQLATENCY;    /**< Irq Latency Register  */
+} MSC_TypeDef;                  /**< MSC Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_MSC_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for MSC CTRL */
+#define _MSC_CTRL_RESETVALUE                    0x00000001UL                       /**< Default value for MSC_CTRL */
+#define _MSC_CTRL_MASK                          0x00000001UL                       /**< Mask for MSC_CTRL */
+#define MSC_CTRL_BUSFAULT                       (0x1UL << 0)                       /**< Bus Fault Response Enable */
+#define _MSC_CTRL_BUSFAULT_SHIFT                0                                  /**< Shift value for MSC_BUSFAULT */
+#define _MSC_CTRL_BUSFAULT_MASK                 0x1UL                              /**< Bit mask for MSC_BUSFAULT */
+#define _MSC_CTRL_BUSFAULT_GENERATE             0x00000000UL                       /**< Mode GENERATE for MSC_CTRL */
+#define _MSC_CTRL_BUSFAULT_DEFAULT              0x00000001UL                       /**< Mode DEFAULT for MSC_CTRL */
+#define _MSC_CTRL_BUSFAULT_IGNORE               0x00000001UL                       /**< Mode IGNORE for MSC_CTRL */
+#define MSC_CTRL_BUSFAULT_GENERATE              (_MSC_CTRL_BUSFAULT_GENERATE << 0) /**< Shifted mode GENERATE for MSC_CTRL */
+#define MSC_CTRL_BUSFAULT_DEFAULT               (_MSC_CTRL_BUSFAULT_DEFAULT << 0)  /**< Shifted mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_BUSFAULT_IGNORE                (_MSC_CTRL_BUSFAULT_IGNORE << 0)   /**< Shifted mode IGNORE for MSC_CTRL */
+
+/* Bit fields for MSC READCTRL */
+#define _MSC_READCTRL_RESETVALUE                0x00000001UL                        /**< Default value for MSC_READCTRL */
+#define _MSC_READCTRL_MASK                      0x0000009FUL                        /**< Mask for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_SHIFT                0                                   /**< Shift value for MSC_MODE */
+#define _MSC_READCTRL_MODE_MASK                 0x7UL                               /**< Bit mask for MSC_MODE */
+#define _MSC_READCTRL_MODE_WS0                  0x00000000UL                        /**< Mode WS0 for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_DEFAULT              0x00000001UL                        /**< Mode DEFAULT for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_WS1                  0x00000001UL                        /**< Mode WS1 for MSC_READCTRL */
+#define MSC_READCTRL_MODE_WS0                   (_MSC_READCTRL_MODE_WS0 << 0)       /**< Shifted mode WS0 for MSC_READCTRL */
+#define MSC_READCTRL_MODE_DEFAULT               (_MSC_READCTRL_MODE_DEFAULT << 0)   /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_MODE_WS1                   (_MSC_READCTRL_MODE_WS1 << 0)       /**< Shifted mode WS1 for MSC_READCTRL */
+#define MSC_READCTRL_IFCDIS                     (0x1UL << 3)                        /**< Internal Flash Cache Disable */
+#define _MSC_READCTRL_IFCDIS_SHIFT              3                                   /**< Shift value for MSC_IFCDIS */
+#define _MSC_READCTRL_IFCDIS_MASK               0x8UL                               /**< Bit mask for MSC_IFCDIS */
+#define _MSC_READCTRL_IFCDIS_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_IFCDIS_DEFAULT             (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_AIDIS                      (0x1UL << 4)                        /**< Automatic Invalidate Disable */
+#define _MSC_READCTRL_AIDIS_SHIFT               4                                   /**< Shift value for MSC_AIDIS */
+#define _MSC_READCTRL_AIDIS_MASK                0x10UL                              /**< Bit mask for MSC_AIDIS */
+#define _MSC_READCTRL_AIDIS_DEFAULT             0x00000000UL                        /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_AIDIS_DEFAULT              (_MSC_READCTRL_AIDIS_DEFAULT << 4)  /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_RAMCEN                     (0x1UL << 7)                        /**< RAM Cache Enable */
+#define _MSC_READCTRL_RAMCEN_SHIFT              7                                   /**< Shift value for MSC_RAMCEN */
+#define _MSC_READCTRL_RAMCEN_MASK               0x80UL                              /**< Bit mask for MSC_RAMCEN */
+#define _MSC_READCTRL_RAMCEN_DEFAULT            0x00000000UL                        /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_RAMCEN_DEFAULT             (_MSC_READCTRL_RAMCEN_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_READCTRL */
+
+/* Bit fields for MSC WRITECTRL */
+#define _MSC_WRITECTRL_RESETVALUE               0x00000000UL                                /**< Default value for MSC_WRITECTRL */
+#define _MSC_WRITECTRL_MASK                     0x00000003UL                                /**< Mask for MSC_WRITECTRL */
+#define MSC_WRITECTRL_WREN                      (0x1UL << 0)                                /**< Enable Write/Erase Controller  */
+#define _MSC_WRITECTRL_WREN_SHIFT               0                                           /**< Shift value for MSC_WREN */
+#define _MSC_WRITECTRL_WREN_MASK                0x1UL                                       /**< Bit mask for MSC_WREN */
+#define _MSC_WRITECTRL_WREN_DEFAULT             0x00000000UL                                /**< Mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_WREN_DEFAULT              (_MSC_WRITECTRL_WREN_DEFAULT << 0)          /**< Shifted mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_IRQERASEABORT             (0x1UL << 1)                                /**< Abort Page Erase on Interrupt */
+#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT      1                                           /**< Shift value for MSC_IRQERASEABORT */
+#define _MSC_WRITECTRL_IRQERASEABORT_MASK       0x2UL                                       /**< Bit mask for MSC_IRQERASEABORT */
+#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT    0x00000000UL                                /**< Mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT     (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
+
+/* Bit fields for MSC WRITECMD */
+#define _MSC_WRITECMD_RESETVALUE                0x00000000UL                             /**< Default value for MSC_WRITECMD */
+#define _MSC_WRITECMD_MASK                      0x0000113FUL                             /**< Mask for MSC_WRITECMD */
+#define MSC_WRITECMD_LADDRIM                    (0x1UL << 0)                             /**< Load MSC_ADDRB into ADDR */
+#define _MSC_WRITECMD_LADDRIM_SHIFT             0                                        /**< Shift value for MSC_LADDRIM */
+#define _MSC_WRITECMD_LADDRIM_MASK              0x1UL                                    /**< Bit mask for MSC_LADDRIM */
+#define _MSC_WRITECMD_LADDRIM_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_LADDRIM_DEFAULT            (_MSC_WRITECMD_LADDRIM_DEFAULT << 0)     /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEPAGE                  (0x1UL << 1)                             /**< Erase Page */
+#define _MSC_WRITECMD_ERASEPAGE_SHIFT           1                                        /**< Shift value for MSC_ERASEPAGE */
+#define _MSC_WRITECMD_ERASEPAGE_MASK            0x2UL                                    /**< Bit mask for MSC_ERASEPAGE */
+#define _MSC_WRITECMD_ERASEPAGE_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEPAGE_DEFAULT          (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)   /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEEND                   (0x1UL << 2)                             /**< End Write Mode */
+#define _MSC_WRITECMD_WRITEEND_SHIFT            2                                        /**< Shift value for MSC_WRITEEND */
+#define _MSC_WRITECMD_WRITEEND_MASK             0x4UL                                    /**< Bit mask for MSC_WRITEEND */
+#define _MSC_WRITECMD_WRITEEND_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEEND_DEFAULT           (_MSC_WRITECMD_WRITEEND_DEFAULT << 2)    /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEONCE                  (0x1UL << 3)                             /**< Word Write-Once Trigger */
+#define _MSC_WRITECMD_WRITEONCE_SHIFT           3                                        /**< Shift value for MSC_WRITEONCE */
+#define _MSC_WRITECMD_WRITEONCE_MASK            0x8UL                                    /**< Bit mask for MSC_WRITEONCE */
+#define _MSC_WRITECMD_WRITEONCE_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEONCE_DEFAULT          (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3)   /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITETRIG                  (0x1UL << 4)                             /**< Word Write Sequence Trigger */
+#define _MSC_WRITECMD_WRITETRIG_SHIFT           4                                        /**< Shift value for MSC_WRITETRIG */
+#define _MSC_WRITECMD_WRITETRIG_MASK            0x10UL                                   /**< Bit mask for MSC_WRITETRIG */
+#define _MSC_WRITECMD_WRITETRIG_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITETRIG_DEFAULT          (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4)   /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEABORT                 (0x1UL << 5)                             /**< Abort erase sequence */
+#define _MSC_WRITECMD_ERASEABORT_SHIFT          5                                        /**< Shift value for MSC_ERASEABORT */
+#define _MSC_WRITECMD_ERASEABORT_MASK           0x20UL                                   /**< Bit mask for MSC_ERASEABORT */
+#define _MSC_WRITECMD_ERASEABORT_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEABORT_DEFAULT         (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5)  /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEMAIN0                 (0x1UL << 8)                             /**< Mass erase region 0 */
+#define _MSC_WRITECMD_ERASEMAIN0_SHIFT          8                                        /**< Shift value for MSC_ERASEMAIN0 */
+#define _MSC_WRITECMD_ERASEMAIN0_MASK           0x100UL                                  /**< Bit mask for MSC_ERASEMAIN0 */
+#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEMAIN0_DEFAULT         (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8)  /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_CLEARWDATA                 (0x1UL << 12)                            /**< Clear WDATA state */
+#define _MSC_WRITECMD_CLEARWDATA_SHIFT          12                                       /**< Shift value for MSC_CLEARWDATA */
+#define _MSC_WRITECMD_CLEARWDATA_MASK           0x1000UL                                 /**< Bit mask for MSC_CLEARWDATA */
+#define _MSC_WRITECMD_CLEARWDATA_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_CLEARWDATA_DEFAULT         (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+
+/* Bit fields for MSC ADDRB */
+#define _MSC_ADDRB_RESETVALUE                   0x00000000UL                    /**< Default value for MSC_ADDRB */
+#define _MSC_ADDRB_MASK                         0xFFFFFFFFUL                    /**< Mask for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_SHIFT                  0                               /**< Shift value for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_MASK                   0xFFFFFFFFUL                    /**< Bit mask for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for MSC_ADDRB */
+#define MSC_ADDRB_ADDRB_DEFAULT                 (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
+
+/* Bit fields for MSC WDATA */
+#define _MSC_WDATA_RESETVALUE                   0x00000000UL                    /**< Default value for MSC_WDATA */
+#define _MSC_WDATA_MASK                         0xFFFFFFFFUL                    /**< Mask for MSC_WDATA */
+#define _MSC_WDATA_WDATA_SHIFT                  0                               /**< Shift value for MSC_WDATA */
+#define _MSC_WDATA_WDATA_MASK                   0xFFFFFFFFUL                    /**< Bit mask for MSC_WDATA */
+#define _MSC_WDATA_WDATA_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for MSC_WDATA */
+#define MSC_WDATA_WDATA_DEFAULT                 (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
+
+/* Bit fields for MSC STATUS */
+#define _MSC_STATUS_RESETVALUE                  0x00000008UL                            /**< Default value for MSC_STATUS */
+#define _MSC_STATUS_MASK                        0x0000007FUL                            /**< Mask for MSC_STATUS */
+#define MSC_STATUS_BUSY                         (0x1UL << 0)                            /**< Erase/Write Busy */
+#define _MSC_STATUS_BUSY_SHIFT                  0                                       /**< Shift value for MSC_BUSY */
+#define _MSC_STATUS_BUSY_MASK                   0x1UL                                   /**< Bit mask for MSC_BUSY */
+#define _MSC_STATUS_BUSY_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_BUSY_DEFAULT                 (_MSC_STATUS_BUSY_DEFAULT << 0)         /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_LOCKED                       (0x1UL << 1)                            /**< Access Locked */
+#define _MSC_STATUS_LOCKED_SHIFT                1                                       /**< Shift value for MSC_LOCKED */
+#define _MSC_STATUS_LOCKED_MASK                 0x2UL                                   /**< Bit mask for MSC_LOCKED */
+#define _MSC_STATUS_LOCKED_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_LOCKED_DEFAULT               (_MSC_STATUS_LOCKED_DEFAULT << 1)       /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_INVADDR                      (0x1UL << 2)                            /**< Invalid Write Address or Erase Page */
+#define _MSC_STATUS_INVADDR_SHIFT               2                                       /**< Shift value for MSC_INVADDR */
+#define _MSC_STATUS_INVADDR_MASK                0x4UL                                   /**< Bit mask for MSC_INVADDR */
+#define _MSC_STATUS_INVADDR_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_INVADDR_DEFAULT              (_MSC_STATUS_INVADDR_DEFAULT << 2)      /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WDATAREADY                   (0x1UL << 3)                            /**< WDATA Write Ready */
+#define _MSC_STATUS_WDATAREADY_SHIFT            3                                       /**< Shift value for MSC_WDATAREADY */
+#define _MSC_STATUS_WDATAREADY_MASK             0x8UL                                   /**< Bit mask for MSC_WDATAREADY */
+#define _MSC_STATUS_WDATAREADY_DEFAULT          0x00000001UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WDATAREADY_DEFAULT           (_MSC_STATUS_WDATAREADY_DEFAULT << 3)   /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WORDTIMEOUT                  (0x1UL << 4)                            /**< Flash Write Word Timeout */
+#define _MSC_STATUS_WORDTIMEOUT_SHIFT           4                                       /**< Shift value for MSC_WORDTIMEOUT */
+#define _MSC_STATUS_WORDTIMEOUT_MASK            0x10UL                                  /**< Bit mask for MSC_WORDTIMEOUT */
+#define _MSC_STATUS_WORDTIMEOUT_DEFAULT         0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WORDTIMEOUT_DEFAULT          (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)  /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_ERASEABORTED                 (0x1UL << 5)                            /**< The Current Flash Erase Operation Aborted */
+#define _MSC_STATUS_ERASEABORTED_SHIFT          5                                       /**< Shift value for MSC_ERASEABORTED */
+#define _MSC_STATUS_ERASEABORTED_MASK           0x20UL                                  /**< Bit mask for MSC_ERASEABORTED */
+#define _MSC_STATUS_ERASEABORTED_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_ERASEABORTED_DEFAULT         (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_PCRUNNING                    (0x1UL << 6)                            /**< Performance Counters Running */
+#define _MSC_STATUS_PCRUNNING_SHIFT             6                                       /**< Shift value for MSC_PCRUNNING */
+#define _MSC_STATUS_PCRUNNING_MASK              0x40UL                                  /**< Bit mask for MSC_PCRUNNING */
+#define _MSC_STATUS_PCRUNNING_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_PCRUNNING_DEFAULT            (_MSC_STATUS_PCRUNNING_DEFAULT << 6)    /**< Shifted mode DEFAULT for MSC_STATUS */
+
+/* Bit fields for MSC IF */
+#define _MSC_IF_RESETVALUE                      0x00000000UL                 /**< Default value for MSC_IF */
+#define _MSC_IF_MASK                            0x0000000FUL                 /**< Mask for MSC_IF */
+#define MSC_IF_ERASE                            (0x1UL << 0)                 /**< Erase Done Interrupt Read Flag */
+#define _MSC_IF_ERASE_SHIFT                     0                            /**< Shift value for MSC_ERASE */
+#define _MSC_IF_ERASE_MASK                      0x1UL                        /**< Bit mask for MSC_ERASE */
+#define _MSC_IF_ERASE_DEFAULT                   0x00000000UL                 /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_ERASE_DEFAULT                    (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_WRITE                            (0x1UL << 1)                 /**< Write Done Interrupt Read Flag */
+#define _MSC_IF_WRITE_SHIFT                     1                            /**< Shift value for MSC_WRITE */
+#define _MSC_IF_WRITE_MASK                      0x2UL                        /**< Bit mask for MSC_WRITE */
+#define _MSC_IF_WRITE_DEFAULT                   0x00000000UL                 /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_WRITE_DEFAULT                    (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_CHOF                             (0x1UL << 2)                 /**< Cache Hits Overflow Interrupt Flag */
+#define _MSC_IF_CHOF_SHIFT                      2                            /**< Shift value for MSC_CHOF */
+#define _MSC_IF_CHOF_MASK                       0x4UL                        /**< Bit mask for MSC_CHOF */
+#define _MSC_IF_CHOF_DEFAULT                    0x00000000UL                 /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_CHOF_DEFAULT                     (_MSC_IF_CHOF_DEFAULT << 2)  /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_CMOF                             (0x1UL << 3)                 /**< Cache Misses Overflow Interrupt Flag */
+#define _MSC_IF_CMOF_SHIFT                      3                            /**< Shift value for MSC_CMOF */
+#define _MSC_IF_CMOF_MASK                       0x8UL                        /**< Bit mask for MSC_CMOF */
+#define _MSC_IF_CMOF_DEFAULT                    0x00000000UL                 /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_CMOF_DEFAULT                     (_MSC_IF_CMOF_DEFAULT << 3)  /**< Shifted mode DEFAULT for MSC_IF */
+
+/* Bit fields for MSC IFS */
+#define _MSC_IFS_RESETVALUE                     0x00000000UL                  /**< Default value for MSC_IFS */
+#define _MSC_IFS_MASK                           0x0000000FUL                  /**< Mask for MSC_IFS */
+#define MSC_IFS_ERASE                           (0x1UL << 0)                  /**< Erase Done Interrupt Set */
+#define _MSC_IFS_ERASE_SHIFT                    0                             /**< Shift value for MSC_ERASE */
+#define _MSC_IFS_ERASE_MASK                     0x1UL                         /**< Bit mask for MSC_ERASE */
+#define _MSC_IFS_ERASE_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_ERASE_DEFAULT                   (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_WRITE                           (0x1UL << 1)                  /**< Write Done Interrupt Set */
+#define _MSC_IFS_WRITE_SHIFT                    1                             /**< Shift value for MSC_WRITE */
+#define _MSC_IFS_WRITE_MASK                     0x2UL                         /**< Bit mask for MSC_WRITE */
+#define _MSC_IFS_WRITE_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_WRITE_DEFAULT                   (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CHOF                            (0x1UL << 2)                  /**< Cache Hits Overflow Interrupt Set */
+#define _MSC_IFS_CHOF_SHIFT                     2                             /**< Shift value for MSC_CHOF */
+#define _MSC_IFS_CHOF_MASK                      0x4UL                         /**< Bit mask for MSC_CHOF */
+#define _MSC_IFS_CHOF_DEFAULT                   0x00000000UL                  /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CHOF_DEFAULT                    (_MSC_IFS_CHOF_DEFAULT << 2)  /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CMOF                            (0x1UL << 3)                  /**< Cache Misses Overflow Interrupt Set */
+#define _MSC_IFS_CMOF_SHIFT                     3                             /**< Shift value for MSC_CMOF */
+#define _MSC_IFS_CMOF_MASK                      0x8UL                         /**< Bit mask for MSC_CMOF */
+#define _MSC_IFS_CMOF_DEFAULT                   0x00000000UL                  /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CMOF_DEFAULT                    (_MSC_IFS_CMOF_DEFAULT << 3)  /**< Shifted mode DEFAULT for MSC_IFS */
+
+/* Bit fields for MSC IFC */
+#define _MSC_IFC_RESETVALUE                     0x00000000UL                  /**< Default value for MSC_IFC */
+#define _MSC_IFC_MASK                           0x0000000FUL                  /**< Mask for MSC_IFC */
+#define MSC_IFC_ERASE                           (0x1UL << 0)                  /**< Erase Done Interrupt Clear */
+#define _MSC_IFC_ERASE_SHIFT                    0                             /**< Shift value for MSC_ERASE */
+#define _MSC_IFC_ERASE_MASK                     0x1UL                         /**< Bit mask for MSC_ERASE */
+#define _MSC_IFC_ERASE_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_ERASE_DEFAULT                   (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_WRITE                           (0x1UL << 1)                  /**< Write Done Interrupt Clear */
+#define _MSC_IFC_WRITE_SHIFT                    1                             /**< Shift value for MSC_WRITE */
+#define _MSC_IFC_WRITE_MASK                     0x2UL                         /**< Bit mask for MSC_WRITE */
+#define _MSC_IFC_WRITE_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_WRITE_DEFAULT                   (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CHOF                            (0x1UL << 2)                  /**< Cache Hits Overflow Interrupt Clear */
+#define _MSC_IFC_CHOF_SHIFT                     2                             /**< Shift value for MSC_CHOF */
+#define _MSC_IFC_CHOF_MASK                      0x4UL                         /**< Bit mask for MSC_CHOF */
+#define _MSC_IFC_CHOF_DEFAULT                   0x00000000UL                  /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CHOF_DEFAULT                    (_MSC_IFC_CHOF_DEFAULT << 2)  /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CMOF                            (0x1UL << 3)                  /**< Cache Misses Overflow Interrupt Clear */
+#define _MSC_IFC_CMOF_SHIFT                     3                             /**< Shift value for MSC_CMOF */
+#define _MSC_IFC_CMOF_MASK                      0x8UL                         /**< Bit mask for MSC_CMOF */
+#define _MSC_IFC_CMOF_DEFAULT                   0x00000000UL                  /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CMOF_DEFAULT                    (_MSC_IFC_CMOF_DEFAULT << 3)  /**< Shifted mode DEFAULT for MSC_IFC */
+
+/* Bit fields for MSC IEN */
+#define _MSC_IEN_RESETVALUE                     0x00000000UL                  /**< Default value for MSC_IEN */
+#define _MSC_IEN_MASK                           0x0000000FUL                  /**< Mask for MSC_IEN */
+#define MSC_IEN_ERASE                           (0x1UL << 0)                  /**< Erase Done Interrupt Enable */
+#define _MSC_IEN_ERASE_SHIFT                    0                             /**< Shift value for MSC_ERASE */
+#define _MSC_IEN_ERASE_MASK                     0x1UL                         /**< Bit mask for MSC_ERASE */
+#define _MSC_IEN_ERASE_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_ERASE_DEFAULT                   (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_WRITE                           (0x1UL << 1)                  /**< Write Done Interrupt Enable */
+#define _MSC_IEN_WRITE_SHIFT                    1                             /**< Shift value for MSC_WRITE */
+#define _MSC_IEN_WRITE_MASK                     0x2UL                         /**< Bit mask for MSC_WRITE */
+#define _MSC_IEN_WRITE_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_WRITE_DEFAULT                   (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CHOF                            (0x1UL << 2)                  /**< Cache Hits Overflow Interrupt Enable */
+#define _MSC_IEN_CHOF_SHIFT                     2                             /**< Shift value for MSC_CHOF */
+#define _MSC_IEN_CHOF_MASK                      0x4UL                         /**< Bit mask for MSC_CHOF */
+#define _MSC_IEN_CHOF_DEFAULT                   0x00000000UL                  /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CHOF_DEFAULT                    (_MSC_IEN_CHOF_DEFAULT << 2)  /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CMOF                            (0x1UL << 3)                  /**< Cache Misses Overflow Interrupt Enable */
+#define _MSC_IEN_CMOF_SHIFT                     3                             /**< Shift value for MSC_CMOF */
+#define _MSC_IEN_CMOF_MASK                      0x8UL                         /**< Bit mask for MSC_CMOF */
+#define _MSC_IEN_CMOF_DEFAULT                   0x00000000UL                  /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CMOF_DEFAULT                    (_MSC_IEN_CMOF_DEFAULT << 3)  /**< Shifted mode DEFAULT for MSC_IEN */
+
+/* Bit fields for MSC LOCK */
+#define _MSC_LOCK_RESETVALUE                    0x00000000UL                      /**< Default value for MSC_LOCK */
+#define _MSC_LOCK_MASK                          0x0000FFFFUL                      /**< Mask for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_SHIFT                 0                                 /**< Shift value for MSC_LOCKKEY */
+#define _MSC_LOCK_LOCKKEY_MASK                  0xFFFFUL                          /**< Bit mask for MSC_LOCKKEY */
+#define _MSC_LOCK_LOCKKEY_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_UNLOCKED              0x00000000UL                      /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK                  0x00000000UL                      /**< Mode LOCK for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCKED                0x00000001UL                      /**< Mode LOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_UNLOCK                0x00001B71UL                      /**< Mode UNLOCK for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_DEFAULT                (_MSC_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_UNLOCKED               (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK                   (_MSC_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCKED                 (_MSC_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_UNLOCK                 (_MSC_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for MSC_LOCK */
+
+/* Bit fields for MSC CMD */
+#define _MSC_CMD_RESETVALUE                     0x00000000UL                     /**< Default value for MSC_CMD */
+#define _MSC_CMD_MASK                           0x00000007UL                     /**< Mask for MSC_CMD */
+#define MSC_CMD_INVCACHE                        (0x1UL << 0)                     /**< Invalidate Instruction Cache */
+#define _MSC_CMD_INVCACHE_SHIFT                 0                                /**< Shift value for MSC_INVCACHE */
+#define _MSC_CMD_INVCACHE_MASK                  0x1UL                            /**< Bit mask for MSC_INVCACHE */
+#define _MSC_CMD_INVCACHE_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for MSC_CMD */
+#define MSC_CMD_INVCACHE_DEFAULT                (_MSC_CMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
+#define MSC_CMD_STARTPC                         (0x1UL << 1)                     /**< Start Performance Counters */
+#define _MSC_CMD_STARTPC_SHIFT                  1                                /**< Shift value for MSC_STARTPC */
+#define _MSC_CMD_STARTPC_MASK                   0x2UL                            /**< Bit mask for MSC_STARTPC */
+#define _MSC_CMD_STARTPC_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for MSC_CMD */
+#define MSC_CMD_STARTPC_DEFAULT                 (_MSC_CMD_STARTPC_DEFAULT << 1)  /**< Shifted mode DEFAULT for MSC_CMD */
+#define MSC_CMD_STOPPC                          (0x1UL << 2)                     /**< Stop Performance Counters */
+#define _MSC_CMD_STOPPC_SHIFT                   2                                /**< Shift value for MSC_STOPPC */
+#define _MSC_CMD_STOPPC_MASK                    0x4UL                            /**< Bit mask for MSC_STOPPC */
+#define _MSC_CMD_STOPPC_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for MSC_CMD */
+#define MSC_CMD_STOPPC_DEFAULT                  (_MSC_CMD_STOPPC_DEFAULT << 2)   /**< Shifted mode DEFAULT for MSC_CMD */
+
+/* Bit fields for MSC CACHEHITS */
+#define _MSC_CACHEHITS_RESETVALUE               0x00000000UL                            /**< Default value for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_MASK                     0x000FFFFFUL                            /**< Mask for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_CACHEHITS_SHIFT          0                                       /**< Shift value for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_CACHEHITS_MASK           0xFFFFFUL                               /**< Bit mask for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_CACHEHITS_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for MSC_CACHEHITS */
+#define MSC_CACHEHITS_CACHEHITS_DEFAULT         (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
+
+/* Bit fields for MSC CACHEMISSES */
+#define _MSC_CACHEMISSES_RESETVALUE             0x00000000UL                                /**< Default value for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_MASK                   0x000FFFFFUL                                /**< Mask for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT      0                                           /**< Shift value for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_CACHEMISSES_MASK       0xFFFFFUL                                   /**< Bit mask for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT    0x00000000UL                                /**< Mode DEFAULT for MSC_CACHEMISSES */
+#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT     (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
+
+/* Bit fields for MSC TIMEBASE */
+#define _MSC_TIMEBASE_RESETVALUE                0x00000010UL                         /**< Default value for MSC_TIMEBASE */
+#define _MSC_TIMEBASE_MASK                      0x0001003FUL                         /**< Mask for MSC_TIMEBASE */
+#define _MSC_TIMEBASE_BASE_SHIFT                0                                    /**< Shift value for MSC_BASE */
+#define _MSC_TIMEBASE_BASE_MASK                 0x3FUL                               /**< Bit mask for MSC_BASE */
+#define _MSC_TIMEBASE_BASE_DEFAULT              0x00000010UL                         /**< Mode DEFAULT for MSC_TIMEBASE */
+#define MSC_TIMEBASE_BASE_DEFAULT               (_MSC_TIMEBASE_BASE_DEFAULT << 0)    /**< Shifted mode DEFAULT for MSC_TIMEBASE */
+#define MSC_TIMEBASE_PERIOD                     (0x1UL << 16)                        /**< Sets the timebase period */
+#define _MSC_TIMEBASE_PERIOD_SHIFT              16                                   /**< Shift value for MSC_PERIOD */
+#define _MSC_TIMEBASE_PERIOD_MASK               0x10000UL                            /**< Bit mask for MSC_PERIOD */
+#define _MSC_TIMEBASE_PERIOD_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for MSC_TIMEBASE */
+#define _MSC_TIMEBASE_PERIOD_1US                0x00000000UL                         /**< Mode 1US for MSC_TIMEBASE */
+#define _MSC_TIMEBASE_PERIOD_5US                0x00000001UL                         /**< Mode 5US for MSC_TIMEBASE */
+#define MSC_TIMEBASE_PERIOD_DEFAULT             (_MSC_TIMEBASE_PERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
+#define MSC_TIMEBASE_PERIOD_1US                 (_MSC_TIMEBASE_PERIOD_1US << 16)     /**< Shifted mode 1US for MSC_TIMEBASE */
+#define MSC_TIMEBASE_PERIOD_5US                 (_MSC_TIMEBASE_PERIOD_5US << 16)     /**< Shifted mode 5US for MSC_TIMEBASE */
+
+/* Bit fields for MSC MASSLOCK */
+#define _MSC_MASSLOCK_RESETVALUE                0x00000001UL                          /**< Default value for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_MASK                      0x0000FFFFUL                          /**< Mask for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_SHIFT             0                                     /**< Shift value for MSC_LOCKKEY */
+#define _MSC_MASSLOCK_LOCKKEY_MASK              0xFFFFUL                              /**< Bit mask for MSC_LOCKKEY */
+#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED          0x00000000UL                          /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK              0x00000000UL                          /**< Mode LOCK for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_DEFAULT           0x00000001UL                          /**< Mode DEFAULT for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCKED            0x00000001UL                          /**< Mode LOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_UNLOCK            0x0000631AUL                          /**< Mode UNLOCK for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_UNLOCKED           (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK               (_MSC_MASSLOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_DEFAULT            (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCKED             (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_UNLOCK             (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for MSC_MASSLOCK */
+
+/* Bit fields for MSC IRQLATENCY */
+#define _MSC_IRQLATENCY_RESETVALUE              0x00000000UL                              /**< Default value for MSC_IRQLATENCY */
+#define _MSC_IRQLATENCY_MASK                    0x000000FFUL                              /**< Mask for MSC_IRQLATENCY */
+#define _MSC_IRQLATENCY_IRQLATENCY_SHIFT        0                                         /**< Shift value for MSC_IRQLATENCY */
+#define _MSC_IRQLATENCY_IRQLATENCY_MASK         0xFFUL                                    /**< Bit mask for MSC_IRQLATENCY */
+#define _MSC_IRQLATENCY_IRQLATENCY_DEFAULT      0x00000000UL                              /**< Mode DEFAULT for MSC_IRQLATENCY */
+#define MSC_IRQLATENCY_IRQLATENCY_DEFAULT       (_MSC_IRQLATENCY_IRQLATENCY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IRQLATENCY */
+
+/** @} End of group EFM32HG_MSC */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_mtb.h

@@ -0,0 +1,135 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_MTB register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_MTB
+ * @{
+ * @brief EFM32HG_MTB Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t POSITION; /**< MTB Trace Position Register.  */
+  __IOM uint32_t MASTER;   /**< MTB Trace Control Register  */
+  __IOM uint32_t FLOW;     /**< MTB Trace Flow Register  */
+  __IOM uint32_t BASE;     /**< MTB Trace Base Register  */
+} MTB_TypeDef;             /**< MTB Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_MTB_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for MTB POSITION */
+#define _MTB_POSITION_RESETVALUE         0x00000000UL                         /**< Default value for MTB_POSITION */
+#define _MTB_POSITION_MASK               0xFFFFFFFCUL                         /**< Mask for MTB_POSITION */
+#define MTB_POSITION_WRAP                (0x1UL << 2)                         /**< Trace wrap bit. */
+#define _MTB_POSITION_WRAP_SHIFT         2                                    /**< Shift value for MTB_WRAP */
+#define _MTB_POSITION_WRAP_MASK          0x4UL                                /**< Bit mask for MTB_WRAP */
+#define _MTB_POSITION_WRAP_DEFAULT       0x00000000UL                         /**< Mode DEFAULT for MTB_POSITION */
+#define MTB_POSITION_WRAP_DEFAULT        (_MTB_POSITION_WRAP_DEFAULT << 2)    /**< Shifted mode DEFAULT for MTB_POSITION */
+#define _MTB_POSITION_POINTER_SHIFT      3                                    /**< Shift value for MTB_POINTER */
+#define _MTB_POSITION_POINTER_MASK       0xFFFFFFF8UL                         /**< Bit mask for MTB_POINTER */
+#define _MTB_POSITION_POINTER_DEFAULT    0x00000000UL                         /**< Mode DEFAULT for MTB_POSITION */
+#define MTB_POSITION_POINTER_DEFAULT     (_MTB_POSITION_POINTER_DEFAULT << 3) /**< Shifted mode DEFAULT for MTB_POSITION */
+
+/* Bit fields for MTB MASTER */
+#define _MTB_MASTER_RESETVALUE           0x00000000UL                        /**< Default value for MTB_MASTER */
+#define _MTB_MASTER_MASK                 0x8000027FUL                        /**< Mask for MTB_MASTER */
+#define _MTB_MASTER_MASK_SHIFT           0                                   /**< Shift value for MTB_MASK */
+#define _MTB_MASTER_MASK_MASK            0x1FUL                              /**< Bit mask for MTB_MASK */
+#define _MTB_MASTER_MASK_DEFAULT         0x00000000UL                        /**< Mode DEFAULT for MTB_MASTER */
+#define MTB_MASTER_MASK_DEFAULT          (_MTB_MASTER_MASK_DEFAULT << 0)     /**< Shifted mode DEFAULT for MTB_MASTER */
+#define MTB_MASTER_TSTARTEN              (0x1UL << 5)                        /**< Trace start input enable. */
+#define _MTB_MASTER_TSTARTEN_SHIFT       5                                   /**< Shift value for MTB_TSTARTEN */
+#define _MTB_MASTER_TSTARTEN_MASK        0x20UL                              /**< Bit mask for MTB_TSTARTEN */
+#define _MTB_MASTER_TSTARTEN_DEFAULT     0x00000000UL                        /**< Mode DEFAULT for MTB_MASTER */
+#define MTB_MASTER_TSTARTEN_DEFAULT      (_MTB_MASTER_TSTARTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MTB_MASTER */
+#define MTB_MASTER_TSTOPEN               (0x1UL << 6)                        /**< Trace stop input enable. */
+#define _MTB_MASTER_TSTOPEN_SHIFT        6                                   /**< Shift value for MTB_TSTOPEN */
+#define _MTB_MASTER_TSTOPEN_MASK         0x40UL                              /**< Bit mask for MTB_TSTOPEN */
+#define _MTB_MASTER_TSTOPEN_DEFAULT      0x00000000UL                        /**< Mode DEFAULT for MTB_MASTER */
+#define MTB_MASTER_TSTOPEN_DEFAULT       (_MTB_MASTER_TSTOPEN_DEFAULT << 6)  /**< Shifted mode DEFAULT for MTB_MASTER */
+#define MTB_MASTER_HALTREQ               (0x1UL << 9)                        /**< Halt request bit. */
+#define _MTB_MASTER_HALTREQ_SHIFT        9                                   /**< Shift value for MTB_HALTREQ */
+#define _MTB_MASTER_HALTREQ_MASK         0x200UL                             /**< Bit mask for MTB_HALTREQ */
+#define _MTB_MASTER_HALTREQ_DEFAULT      0x00000000UL                        /**< Mode DEFAULT for MTB_MASTER */
+#define MTB_MASTER_HALTREQ_DEFAULT       (_MTB_MASTER_HALTREQ_DEFAULT << 9)  /**< Shifted mode DEFAULT for MTB_MASTER */
+#define MTB_MASTER_EN                    (0x1UL << 31)                       /**< Main trace enable bit. */
+#define _MTB_MASTER_EN_SHIFT             31                                  /**< Shift value for MTB_EN */
+#define _MTB_MASTER_EN_MASK              0x80000000UL                        /**< Bit mask for MTB_EN */
+#define _MTB_MASTER_EN_DEFAULT           0x00000000UL                        /**< Mode DEFAULT for MTB_MASTER */
+#define MTB_MASTER_EN_DEFAULT            (_MTB_MASTER_EN_DEFAULT << 31)      /**< Shifted mode DEFAULT for MTB_MASTER */
+
+/* Bit fields for MTB FLOW */
+#define _MTB_FLOW_RESETVALUE             0x00000000UL                       /**< Default value for MTB_FLOW */
+#define _MTB_FLOW_MASK                   0xFFFFFFFBUL                       /**< Mask for MTB_FLOW */
+#define MTB_FLOW_AUTOSTOP                (0x1UL << 0)                       /**< AUTOSTOP enable. */
+#define _MTB_FLOW_AUTOSTOP_SHIFT         0                                  /**< Shift value for MTB_AUTOSTOP */
+#define _MTB_FLOW_AUTOSTOP_MASK          0x1UL                              /**< Bit mask for MTB_AUTOSTOP */
+#define _MTB_FLOW_AUTOSTOP_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for MTB_FLOW */
+#define MTB_FLOW_AUTOSTOP_DEFAULT        (_MTB_FLOW_AUTOSTOP_DEFAULT << 0)  /**< Shifted mode DEFAULT for MTB_FLOW */
+#define MTB_FLOW_AUTOHALT                (0x1UL << 1)                       /**< AUTOHALT enable. */
+#define _MTB_FLOW_AUTOHALT_SHIFT         1                                  /**< Shift value for MTB_AUTOHALT */
+#define _MTB_FLOW_AUTOHALT_MASK          0x2UL                              /**< Bit mask for MTB_AUTOHALT */
+#define _MTB_FLOW_AUTOHALT_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for MTB_FLOW */
+#define MTB_FLOW_AUTOHALT_DEFAULT        (_MTB_FLOW_AUTOHALT_DEFAULT << 1)  /**< Shifted mode DEFAULT for MTB_FLOW */
+#define _MTB_FLOW_WATERMARK_SHIFT        3                                  /**< Shift value for MTB_WATERMARK */
+#define _MTB_FLOW_WATERMARK_MASK         0xFFFFFFF8UL                       /**< Bit mask for MTB_WATERMARK */
+#define _MTB_FLOW_WATERMARK_DEFAULT      0x00000000UL                       /**< Mode DEFAULT for MTB_FLOW */
+#define MTB_FLOW_WATERMARK_DEFAULT       (_MTB_FLOW_WATERMARK_DEFAULT << 3) /**< Shifted mode DEFAULT for MTB_FLOW */
+
+/* Bit fields for MTB BASE */
+#define _MTB_BASE_RESETVALUE             0x20000000UL                  /**< Default value for MTB_BASE */
+#define _MTB_BASE_MASK                   0xFFFFFFFFUL                  /**< Mask for MTB_BASE */
+#define _MTB_BASE_BASE_SHIFT             0                             /**< Shift value for MTB_BASE */
+#define _MTB_BASE_BASE_MASK              0xFFFFFFFFUL                  /**< Bit mask for MTB_BASE */
+#define _MTB_BASE_BASE_DEFAULT           0x20000000UL                  /**< Mode DEFAULT for MTB_BASE */
+#define MTB_BASE_BASE_DEFAULT            (_MTB_BASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MTB_BASE */
+
+/** @} End of group EFM32HG_MTB */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_pcnt.h

@@ -0,0 +1,498 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_PCNT register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_PCNT
+ * @{
+ * @brief EFM32HG_PCNT Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;          /**< Control Register  */
+  __IOM uint32_t CMD;           /**< Command Register  */
+  __IM uint32_t  STATUS;        /**< Status Register  */
+  __IM uint32_t  CNT;           /**< Counter Value Register  */
+  __IM uint32_t  TOP;           /**< Top Value Register  */
+  __IOM uint32_t TOPB;          /**< Top Value Buffer Register  */
+  __IM uint32_t  IF;            /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;           /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;           /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;           /**< Interrupt Enable Register  */
+  __IOM uint32_t ROUTE;         /**< I/O Routing Register  */
+
+  __IOM uint32_t FREEZE;        /**< Freeze Register  */
+  __IM uint32_t  SYNCBUSY;      /**< Synchronization Busy Register  */
+
+  uint32_t       RESERVED0[1U]; /**< Reserved for future use **/
+  __IOM uint32_t AUXCNT;        /**< Auxiliary Counter Value Register  */
+  __IOM uint32_t INPUT;         /**< PCNT Input Register  */
+} PCNT_TypeDef;                 /**< PCNT Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_PCNT_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for PCNT CTRL */
+#define _PCNT_CTRL_RESETVALUE             0x00000000UL                          /**< Default value for PCNT_CTRL */
+#define _PCNT_CTRL_MASK                   0xFECCCF7FUL                          /**< Mask for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_SHIFT             0                                     /**< Shift value for PCNT_MODE */
+#define _PCNT_CTRL_MODE_MASK              0x3UL                                 /**< Bit mask for PCNT_MODE */
+#define _PCNT_CTRL_MODE_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_DISABLE           0x00000000UL                          /**< Mode DISABLE for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_OVSSINGLE         0x00000001UL                          /**< Mode OVSSINGLE for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_EXTCLKSINGLE      0x00000002UL                          /**< Mode EXTCLKSINGLE for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_EXTCLKQUAD        0x00000003UL                          /**< Mode EXTCLKQUAD for PCNT_CTRL */
+#define PCNT_CTRL_MODE_DEFAULT            (_PCNT_CTRL_MODE_DEFAULT << 0)        /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_MODE_DISABLE            (_PCNT_CTRL_MODE_DISABLE << 0)        /**< Shifted mode DISABLE for PCNT_CTRL */
+#define PCNT_CTRL_MODE_OVSSINGLE          (_PCNT_CTRL_MODE_OVSSINGLE << 0)      /**< Shifted mode OVSSINGLE for PCNT_CTRL */
+#define PCNT_CTRL_MODE_EXTCLKSINGLE       (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0)   /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */
+#define PCNT_CTRL_MODE_EXTCLKQUAD         (_PCNT_CTRL_MODE_EXTCLKQUAD << 0)     /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR                  (0x1UL << 2)                          /**< Non-Quadrature Mode Counter Direction Control */
+#define _PCNT_CTRL_CNTDIR_SHIFT           2                                     /**< Shift value for PCNT_CNTDIR */
+#define _PCNT_CTRL_CNTDIR_MASK            0x4UL                                 /**< Bit mask for PCNT_CNTDIR */
+#define _PCNT_CTRL_CNTDIR_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTDIR_UP              0x00000000UL                          /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_CNTDIR_DOWN            0x00000001UL                          /**< Mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_DEFAULT          (_PCNT_CTRL_CNTDIR_DEFAULT << 2)      /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_UP               (_PCNT_CTRL_CNTDIR_UP << 2)           /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_DOWN             (_PCNT_CTRL_CNTDIR_DOWN << 2)         /**< Shifted mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_EDGE                    (0x1UL << 3)                          /**< Edge Select */
+#define _PCNT_CTRL_EDGE_SHIFT             3                                     /**< Shift value for PCNT_EDGE */
+#define _PCNT_CTRL_EDGE_MASK              0x8UL                                 /**< Bit mask for PCNT_EDGE */
+#define _PCNT_CTRL_EDGE_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_EDGE_POS               0x00000000UL                          /**< Mode POS for PCNT_CTRL */
+#define _PCNT_CTRL_EDGE_NEG               0x00000001UL                          /**< Mode NEG for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_DEFAULT            (_PCNT_CTRL_EDGE_DEFAULT << 3)        /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_POS                (_PCNT_CTRL_EDGE_POS << 3)            /**< Shifted mode POS for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_NEG                (_PCNT_CTRL_EDGE_NEG << 3)            /**< Shifted mode NEG for PCNT_CTRL */
+#define PCNT_CTRL_FILT                    (0x1UL << 4)                          /**< Enable Digital Pulse Width Filter */
+#define _PCNT_CTRL_FILT_SHIFT             4                                     /**< Shift value for PCNT_FILT */
+#define _PCNT_CTRL_FILT_MASK              0x10UL                                /**< Bit mask for PCNT_FILT */
+#define _PCNT_CTRL_FILT_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_FILT_DEFAULT            (_PCNT_CTRL_FILT_DEFAULT << 4)        /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_RSTEN                   (0x1UL << 5)                          /**< Enable PCNT Clock Domain Reset */
+#define _PCNT_CTRL_RSTEN_SHIFT            5                                     /**< Shift value for PCNT_RSTEN */
+#define _PCNT_CTRL_RSTEN_MASK             0x20UL                                /**< Bit mask for PCNT_RSTEN */
+#define _PCNT_CTRL_RSTEN_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_RSTEN_DEFAULT           (_PCNT_CTRL_RSTEN_DEFAULT << 5)       /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTRSTEN             (0x1UL << 6)                          /**< Enable AUXCNT Reset */
+#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT      6                                     /**< Shift value for PCNT_AUXCNTRSTEN */
+#define _PCNT_CTRL_AUXCNTRSTEN_MASK       0x40UL                                /**< Bit mask for PCNT_AUXCNTRSTEN */
+#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT    0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT     (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_HYST                    (0x1UL << 8)                          /**< Enable Hysteresis */
+#define _PCNT_CTRL_HYST_SHIFT             8                                     /**< Shift value for PCNT_HYST */
+#define _PCNT_CTRL_HYST_MASK              0x100UL                               /**< Bit mask for PCNT_HYST */
+#define _PCNT_CTRL_HYST_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_HYST_DEFAULT            (_PCNT_CTRL_HYST_DEFAULT << 8)        /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_S1CDIR                  (0x1UL << 9)                          /**< Count direction determined by S1 */
+#define _PCNT_CTRL_S1CDIR_SHIFT           9                                     /**< Shift value for PCNT_S1CDIR */
+#define _PCNT_CTRL_S1CDIR_MASK            0x200UL                               /**< Bit mask for PCNT_S1CDIR */
+#define _PCNT_CTRL_S1CDIR_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_S1CDIR_DEFAULT          (_PCNT_CTRL_S1CDIR_DEFAULT << 9)      /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_SHIFT            10                                    /**< Shift value for PCNT_CNTEV */
+#define _PCNT_CTRL_CNTEV_MASK             0xC00UL                               /**< Bit mask for PCNT_CNTEV */
+#define _PCNT_CTRL_CNTEV_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_BOTH             0x00000000UL                          /**< Mode BOTH for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_UP               0x00000001UL                          /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_DOWN             0x00000002UL                          /**< Mode DOWN for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_NONE             0x00000003UL                          /**< Mode NONE for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_DEFAULT           (_PCNT_CTRL_CNTEV_DEFAULT << 10)      /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_BOTH              (_PCNT_CTRL_CNTEV_BOTH << 10)         /**< Shifted mode BOTH for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_UP                (_PCNT_CTRL_CNTEV_UP << 10)           /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_DOWN              (_PCNT_CTRL_CNTEV_DOWN << 10)         /**< Shifted mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_NONE              (_PCNT_CTRL_CNTEV_NONE << 10)         /**< Shifted mode NONE for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_SHIFT         14                                    /**< Shift value for PCNT_AUXCNTEV */
+#define _PCNT_CTRL_AUXCNTEV_MASK          0xC000UL                              /**< Bit mask for PCNT_AUXCNTEV */
+#define _PCNT_CTRL_AUXCNTEV_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_NONE          0x00000000UL                          /**< Mode NONE for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_UP            0x00000001UL                          /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_DOWN          0x00000002UL                          /**< Mode DOWN for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_BOTH          0x00000003UL                          /**< Mode BOTH for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_DEFAULT        (_PCNT_CTRL_AUXCNTEV_DEFAULT << 14)   /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_NONE           (_PCNT_CTRL_AUXCNTEV_NONE << 14)      /**< Shifted mode NONE for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_UP             (_PCNT_CTRL_AUXCNTEV_UP << 14)        /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_DOWN           (_PCNT_CTRL_AUXCNTEV_DOWN << 14)      /**< Shifted mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_BOTH           (_PCNT_CTRL_AUXCNTEV_BOTH << 14)      /**< Shifted mode BOTH for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_SHIFT          18                                    /**< Shift value for PCNT_TCCMODE */
+#define _PCNT_CTRL_TCCMODE_MASK           0xC0000UL                             /**< Bit mask for PCNT_TCCMODE */
+#define _PCNT_CTRL_TCCMODE_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_DISABLED       0x00000000UL                          /**< Mode DISABLED for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_LFA            0x00000001UL                          /**< Mode LFA for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_PRS            0x00000002UL                          /**< Mode PRS for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_DEFAULT         (_PCNT_CTRL_TCCMODE_DEFAULT << 18)    /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_DISABLED        (_PCNT_CTRL_TCCMODE_DISABLED << 18)   /**< Shifted mode DISABLED for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_LFA             (_PCNT_CTRL_TCCMODE_LFA << 18)        /**< Shifted mode LFA for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_PRS             (_PCNT_CTRL_TCCMODE_PRS << 18)        /**< Shifted mode PRS for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_SHIFT         22                                    /**< Shift value for PCNT_TCCPRESC */
+#define _PCNT_CTRL_TCCPRESC_MASK          0xC00000UL                            /**< Bit mask for PCNT_TCCPRESC */
+#define _PCNT_CTRL_TCCPRESC_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV1          0x00000000UL                          /**< Mode DIV1 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV2          0x00000001UL                          /**< Mode DIV2 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV4          0x00000002UL                          /**< Mode DIV4 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV8          0x00000003UL                          /**< Mode DIV8 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DEFAULT        (_PCNT_CTRL_TCCPRESC_DEFAULT << 22)   /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV1           (_PCNT_CTRL_TCCPRESC_DIV1 << 22)      /**< Shifted mode DIV1 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV2           (_PCNT_CTRL_TCCPRESC_DIV2 << 22)      /**< Shifted mode DIV2 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV4           (_PCNT_CTRL_TCCPRESC_DIV4 << 22)      /**< Shifted mode DIV4 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV8           (_PCNT_CTRL_TCCPRESC_DIV8 << 22)      /**< Shifted mode DIV8 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_SHIFT          25                                    /**< Shift value for PCNT_TCCCOMP */
+#define _PCNT_CTRL_TCCCOMP_MASK           0x6000000UL                           /**< Bit mask for PCNT_TCCCOMP */
+#define _PCNT_CTRL_TCCCOMP_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_LTOE           0x00000000UL                          /**< Mode LTOE for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_GTOE           0x00000001UL                          /**< Mode GTOE for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_RANGE          0x00000002UL                          /**< Mode RANGE for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_DEFAULT         (_PCNT_CTRL_TCCCOMP_DEFAULT << 25)    /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_LTOE            (_PCNT_CTRL_TCCCOMP_LTOE << 25)       /**< Shifted mode LTOE for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_GTOE            (_PCNT_CTRL_TCCCOMP_GTOE << 25)       /**< Shifted mode GTOE for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_RANGE           (_PCNT_CTRL_TCCCOMP_RANGE << 25)      /**< Shifted mode RANGE for PCNT_CTRL */
+#define PCNT_CTRL_PRSGATEEN               (0x1UL << 27)                         /**< PRS gate enable */
+#define _PCNT_CTRL_PRSGATEEN_SHIFT        27                                    /**< Shift value for PCNT_PRSGATEEN */
+#define _PCNT_CTRL_PRSGATEEN_MASK         0x8000000UL                           /**< Bit mask for PCNT_PRSGATEEN */
+#define _PCNT_CTRL_PRSGATEEN_DEFAULT      0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_PRSGATEEN_DEFAULT       (_PCNT_CTRL_PRSGATEEN_DEFAULT << 27)  /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL               (0x1UL << 28)                         /**< TCC PRS polarity select */
+#define _PCNT_CTRL_TCCPRSPOL_SHIFT        28                                    /**< Shift value for PCNT_TCCPRSPOL */
+#define _PCNT_CTRL_TCCPRSPOL_MASK         0x10000000UL                          /**< Bit mask for PCNT_TCCPRSPOL */
+#define _PCNT_CTRL_TCCPRSPOL_DEFAULT      0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSPOL_RISING       0x00000000UL                          /**< Mode RISING for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSPOL_FALLING      0x00000001UL                          /**< Mode FALLING for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL_DEFAULT       (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 28)  /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL_RISING        (_PCNT_CTRL_TCCPRSPOL_RISING << 28)   /**< Shifted mode RISING for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL_FALLING       (_PCNT_CTRL_TCCPRSPOL_FALLING << 28)  /**< Shifted mode FALLING for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_SHIFT        29                                    /**< Shift value for PCNT_TCCPRSSEL */
+#define _PCNT_CTRL_TCCPRSSEL_MASK         0xE0000000UL                          /**< Bit mask for PCNT_TCCPRSSEL */
+#define _PCNT_CTRL_TCCPRSSEL_DEFAULT      0x00000000UL                          /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH0       0x00000000UL                          /**< Mode PRSCH0 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH1       0x00000001UL                          /**< Mode PRSCH1 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH2       0x00000002UL                          /**< Mode PRSCH2 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH3       0x00000003UL                          /**< Mode PRSCH3 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH4       0x00000004UL                          /**< Mode PRSCH4 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH5       0x00000005UL                          /**< Mode PRSCH5 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_DEFAULT       (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 29)  /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH0        (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 29)   /**< Shifted mode PRSCH0 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH1        (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 29)   /**< Shifted mode PRSCH1 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH2        (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 29)   /**< Shifted mode PRSCH2 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH3        (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 29)   /**< Shifted mode PRSCH3 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH4        (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 29)   /**< Shifted mode PRSCH4 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH5        (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 29)   /**< Shifted mode PRSCH5 for PCNT_CTRL */
+
+/* Bit fields for PCNT CMD */
+#define _PCNT_CMD_RESETVALUE              0x00000000UL                     /**< Default value for PCNT_CMD */
+#define _PCNT_CMD_MASK                    0x00000003UL                     /**< Mask for PCNT_CMD */
+#define PCNT_CMD_LCNTIM                   (0x1UL << 0)                     /**< Load CNT Immediately */
+#define _PCNT_CMD_LCNTIM_SHIFT            0                                /**< Shift value for PCNT_LCNTIM */
+#define _PCNT_CMD_LCNTIM_MASK             0x1UL                            /**< Bit mask for PCNT_LCNTIM */
+#define _PCNT_CMD_LCNTIM_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LCNTIM_DEFAULT           (_PCNT_CMD_LCNTIM_DEFAULT << 0)  /**< Shifted mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LTOPBIM                  (0x1UL << 1)                     /**< Load TOPB Immediately */
+#define _PCNT_CMD_LTOPBIM_SHIFT           1                                /**< Shift value for PCNT_LTOPBIM */
+#define _PCNT_CMD_LTOPBIM_MASK            0x2UL                            /**< Bit mask for PCNT_LTOPBIM */
+#define _PCNT_CMD_LTOPBIM_DEFAULT         0x00000000UL                     /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LTOPBIM_DEFAULT          (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */
+
+/* Bit fields for PCNT STATUS */
+#define _PCNT_STATUS_RESETVALUE           0x00000000UL                    /**< Default value for PCNT_STATUS */
+#define _PCNT_STATUS_MASK                 0x00000001UL                    /**< Mask for PCNT_STATUS */
+#define PCNT_STATUS_DIR                   (0x1UL << 0)                    /**< Current Counter Direction */
+#define _PCNT_STATUS_DIR_SHIFT            0                               /**< Shift value for PCNT_DIR */
+#define _PCNT_STATUS_DIR_MASK             0x1UL                           /**< Bit mask for PCNT_DIR */
+#define _PCNT_STATUS_DIR_DEFAULT          0x00000000UL                    /**< Mode DEFAULT for PCNT_STATUS */
+#define _PCNT_STATUS_DIR_UP               0x00000000UL                    /**< Mode UP for PCNT_STATUS */
+#define _PCNT_STATUS_DIR_DOWN             0x00000001UL                    /**< Mode DOWN for PCNT_STATUS */
+#define PCNT_STATUS_DIR_DEFAULT           (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */
+#define PCNT_STATUS_DIR_UP                (_PCNT_STATUS_DIR_UP << 0)      /**< Shifted mode UP for PCNT_STATUS */
+#define PCNT_STATUS_DIR_DOWN              (_PCNT_STATUS_DIR_DOWN << 0)    /**< Shifted mode DOWN for PCNT_STATUS */
+
+/* Bit fields for PCNT CNT */
+#define _PCNT_CNT_RESETVALUE              0x00000000UL                 /**< Default value for PCNT_CNT */
+#define _PCNT_CNT_MASK                    0x0000FFFFUL                 /**< Mask for PCNT_CNT */
+#define _PCNT_CNT_CNT_SHIFT               0                            /**< Shift value for PCNT_CNT */
+#define _PCNT_CNT_CNT_MASK                0xFFFFUL                     /**< Bit mask for PCNT_CNT */
+#define _PCNT_CNT_CNT_DEFAULT             0x00000000UL                 /**< Mode DEFAULT for PCNT_CNT */
+#define PCNT_CNT_CNT_DEFAULT              (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */
+
+/* Bit fields for PCNT TOP */
+#define _PCNT_TOP_RESETVALUE              0x000000FFUL                 /**< Default value for PCNT_TOP */
+#define _PCNT_TOP_MASK                    0x0000FFFFUL                 /**< Mask for PCNT_TOP */
+#define _PCNT_TOP_TOP_SHIFT               0                            /**< Shift value for PCNT_TOP */
+#define _PCNT_TOP_TOP_MASK                0xFFFFUL                     /**< Bit mask for PCNT_TOP */
+#define _PCNT_TOP_TOP_DEFAULT             0x000000FFUL                 /**< Mode DEFAULT for PCNT_TOP */
+#define PCNT_TOP_TOP_DEFAULT              (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */
+
+/* Bit fields for PCNT TOPB */
+#define _PCNT_TOPB_RESETVALUE             0x000000FFUL                   /**< Default value for PCNT_TOPB */
+#define _PCNT_TOPB_MASK                   0x0000FFFFUL                   /**< Mask for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_SHIFT             0                              /**< Shift value for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_MASK              0xFFFFUL                       /**< Bit mask for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_DEFAULT           0x000000FFUL                   /**< Mode DEFAULT for PCNT_TOPB */
+#define PCNT_TOPB_TOPB_DEFAULT            (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */
+
+/* Bit fields for PCNT IF */
+#define _PCNT_IF_RESETVALUE               0x00000000UL                   /**< Default value for PCNT_IF */
+#define _PCNT_IF_MASK                     0x0000001FUL                   /**< Mask for PCNT_IF */
+#define PCNT_IF_UF                        (0x1UL << 0)                   /**< Underflow Interrupt Read Flag */
+#define _PCNT_IF_UF_SHIFT                 0                              /**< Shift value for PCNT_UF */
+#define _PCNT_IF_UF_MASK                  0x1UL                          /**< Bit mask for PCNT_UF */
+#define _PCNT_IF_UF_DEFAULT               0x00000000UL                   /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_UF_DEFAULT                (_PCNT_IF_UF_DEFAULT << 0)     /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OF                        (0x1UL << 1)                   /**< Overflow Interrupt Read Flag */
+#define _PCNT_IF_OF_SHIFT                 1                              /**< Shift value for PCNT_OF */
+#define _PCNT_IF_OF_MASK                  0x2UL                          /**< Bit mask for PCNT_OF */
+#define _PCNT_IF_OF_DEFAULT               0x00000000UL                   /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OF_DEFAULT                (_PCNT_IF_OF_DEFAULT << 1)     /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_DIRCNG                    (0x1UL << 2)                   /**< Direction Change Detect Interrupt Flag */
+#define _PCNT_IF_DIRCNG_SHIFT             2                              /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IF_DIRCNG_MASK              0x4UL                          /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IF_DIRCNG_DEFAULT           0x00000000UL                   /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_DIRCNG_DEFAULT            (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_AUXOF                     (0x1UL << 3)                   /**< Overflow Interrupt Read Flag */
+#define _PCNT_IF_AUXOF_SHIFT              3                              /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IF_AUXOF_MASK               0x8UL                          /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IF_AUXOF_DEFAULT            0x00000000UL                   /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_AUXOF_DEFAULT             (_PCNT_IF_AUXOF_DEFAULT << 3)  /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_TCC                       (0x1UL << 4)                   /**< Triggered compare Interrupt Read Flag */
+#define _PCNT_IF_TCC_SHIFT                4                              /**< Shift value for PCNT_TCC */
+#define _PCNT_IF_TCC_MASK                 0x10UL                         /**< Bit mask for PCNT_TCC */
+#define _PCNT_IF_TCC_DEFAULT              0x00000000UL                   /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_TCC_DEFAULT               (_PCNT_IF_TCC_DEFAULT << 4)    /**< Shifted mode DEFAULT for PCNT_IF */
+
+/* Bit fields for PCNT IFS */
+#define _PCNT_IFS_RESETVALUE              0x00000000UL                    /**< Default value for PCNT_IFS */
+#define _PCNT_IFS_MASK                    0x0000001FUL                    /**< Mask for PCNT_IFS */
+#define PCNT_IFS_UF                       (0x1UL << 0)                    /**< Underflow interrupt set */
+#define _PCNT_IFS_UF_SHIFT                0                               /**< Shift value for PCNT_UF */
+#define _PCNT_IFS_UF_MASK                 0x1UL                           /**< Bit mask for PCNT_UF */
+#define _PCNT_IFS_UF_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_UF_DEFAULT               (_PCNT_IFS_UF_DEFAULT << 0)     /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_OF                       (0x1UL << 1)                    /**< Overflow Interrupt Set */
+#define _PCNT_IFS_OF_SHIFT                1                               /**< Shift value for PCNT_OF */
+#define _PCNT_IFS_OF_MASK                 0x2UL                           /**< Bit mask for PCNT_OF */
+#define _PCNT_IFS_OF_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_OF_DEFAULT               (_PCNT_IFS_OF_DEFAULT << 1)     /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_DIRCNG                   (0x1UL << 2)                    /**< Direction Change Detect Interrupt Set */
+#define _PCNT_IFS_DIRCNG_SHIFT            2                               /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IFS_DIRCNG_MASK             0x4UL                           /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IFS_DIRCNG_DEFAULT          0x00000000UL                    /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_DIRCNG_DEFAULT           (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_AUXOF                    (0x1UL << 3)                    /**< Auxiliary Overflow Interrupt Set */
+#define _PCNT_IFS_AUXOF_SHIFT             3                               /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IFS_AUXOF_MASK              0x8UL                           /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IFS_AUXOF_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_AUXOF_DEFAULT            (_PCNT_IFS_AUXOF_DEFAULT << 3)  /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_TCC                      (0x1UL << 4)                    /**< Triggered compare Interrupt Set */
+#define _PCNT_IFS_TCC_SHIFT               4                               /**< Shift value for PCNT_TCC */
+#define _PCNT_IFS_TCC_MASK                0x10UL                          /**< Bit mask for PCNT_TCC */
+#define _PCNT_IFS_TCC_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_TCC_DEFAULT              (_PCNT_IFS_TCC_DEFAULT << 4)    /**< Shifted mode DEFAULT for PCNT_IFS */
+
+/* Bit fields for PCNT IFC */
+#define _PCNT_IFC_RESETVALUE              0x00000000UL                    /**< Default value for PCNT_IFC */
+#define _PCNT_IFC_MASK                    0x0000001FUL                    /**< Mask for PCNT_IFC */
+#define PCNT_IFC_UF                       (0x1UL << 0)                    /**< Underflow Interrupt Clear */
+#define _PCNT_IFC_UF_SHIFT                0                               /**< Shift value for PCNT_UF */
+#define _PCNT_IFC_UF_MASK                 0x1UL                           /**< Bit mask for PCNT_UF */
+#define _PCNT_IFC_UF_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_UF_DEFAULT               (_PCNT_IFC_UF_DEFAULT << 0)     /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_OF                       (0x1UL << 1)                    /**< Overflow Interrupt Clear */
+#define _PCNT_IFC_OF_SHIFT                1                               /**< Shift value for PCNT_OF */
+#define _PCNT_IFC_OF_MASK                 0x2UL                           /**< Bit mask for PCNT_OF */
+#define _PCNT_IFC_OF_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_OF_DEFAULT               (_PCNT_IFC_OF_DEFAULT << 1)     /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_DIRCNG                   (0x1UL << 2)                    /**< Direction Change Detect Interrupt Clear */
+#define _PCNT_IFC_DIRCNG_SHIFT            2                               /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IFC_DIRCNG_MASK             0x4UL                           /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IFC_DIRCNG_DEFAULT          0x00000000UL                    /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_DIRCNG_DEFAULT           (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_AUXOF                    (0x1UL << 3)                    /**< Auxiliary Overflow Interrupt Clear */
+#define _PCNT_IFC_AUXOF_SHIFT             3                               /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IFC_AUXOF_MASK              0x8UL                           /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IFC_AUXOF_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_AUXOF_DEFAULT            (_PCNT_IFC_AUXOF_DEFAULT << 3)  /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_TCC                      (0x1UL << 4)                    /**< Triggered compare Interrupt Clear */
+#define _PCNT_IFC_TCC_SHIFT               4                               /**< Shift value for PCNT_TCC */
+#define _PCNT_IFC_TCC_MASK                0x10UL                          /**< Bit mask for PCNT_TCC */
+#define _PCNT_IFC_TCC_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_TCC_DEFAULT              (_PCNT_IFC_TCC_DEFAULT << 4)    /**< Shifted mode DEFAULT for PCNT_IFC */
+
+/* Bit fields for PCNT IEN */
+#define _PCNT_IEN_RESETVALUE              0x00000000UL                    /**< Default value for PCNT_IEN */
+#define _PCNT_IEN_MASK                    0x0000001FUL                    /**< Mask for PCNT_IEN */
+#define PCNT_IEN_UF                       (0x1UL << 0)                    /**< Underflow Interrupt Enable */
+#define _PCNT_IEN_UF_SHIFT                0                               /**< Shift value for PCNT_UF */
+#define _PCNT_IEN_UF_MASK                 0x1UL                           /**< Bit mask for PCNT_UF */
+#define _PCNT_IEN_UF_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_UF_DEFAULT               (_PCNT_IEN_UF_DEFAULT << 0)     /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OF                       (0x1UL << 1)                    /**< Overflow Interrupt Enable */
+#define _PCNT_IEN_OF_SHIFT                1                               /**< Shift value for PCNT_OF */
+#define _PCNT_IEN_OF_MASK                 0x2UL                           /**< Bit mask for PCNT_OF */
+#define _PCNT_IEN_OF_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OF_DEFAULT               (_PCNT_IEN_OF_DEFAULT << 1)     /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_DIRCNG                   (0x1UL << 2)                    /**< Direction Change Detect Interrupt Enable */
+#define _PCNT_IEN_DIRCNG_SHIFT            2                               /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IEN_DIRCNG_MASK             0x4UL                           /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IEN_DIRCNG_DEFAULT          0x00000000UL                    /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_DIRCNG_DEFAULT           (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_AUXOF                    (0x1UL << 3)                    /**< Auxiliary Overflow Interrupt Enable */
+#define _PCNT_IEN_AUXOF_SHIFT             3                               /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IEN_AUXOF_MASK              0x8UL                           /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IEN_AUXOF_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_AUXOF_DEFAULT            (_PCNT_IEN_AUXOF_DEFAULT << 3)  /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_TCC                      (0x1UL << 4)                    /**< Triggered compare Interrupt Enable */
+#define _PCNT_IEN_TCC_SHIFT               4                               /**< Shift value for PCNT_TCC */
+#define _PCNT_IEN_TCC_MASK                0x10UL                          /**< Bit mask for PCNT_TCC */
+#define _PCNT_IEN_TCC_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_TCC_DEFAULT              (_PCNT_IEN_TCC_DEFAULT << 4)    /**< Shifted mode DEFAULT for PCNT_IEN */
+
+/* Bit fields for PCNT ROUTE */
+#define _PCNT_ROUTE_RESETVALUE            0x00000000UL                        /**< Default value for PCNT_ROUTE */
+#define _PCNT_ROUTE_MASK                  0x00000700UL                        /**< Mask for PCNT_ROUTE */
+#define _PCNT_ROUTE_LOCATION_SHIFT        8                                   /**< Shift value for PCNT_LOCATION */
+#define _PCNT_ROUTE_LOCATION_MASK         0x700UL                             /**< Bit mask for PCNT_LOCATION */
+#define _PCNT_ROUTE_LOCATION_LOC0         0x00000000UL                        /**< Mode LOC0 for PCNT_ROUTE */
+#define _PCNT_ROUTE_LOCATION_DEFAULT      0x00000000UL                        /**< Mode DEFAULT for PCNT_ROUTE */
+#define _PCNT_ROUTE_LOCATION_LOC1         0x00000001UL                        /**< Mode LOC1 for PCNT_ROUTE */
+#define _PCNT_ROUTE_LOCATION_LOC2         0x00000002UL                        /**< Mode LOC2 for PCNT_ROUTE */
+#define _PCNT_ROUTE_LOCATION_LOC3         0x00000003UL                        /**< Mode LOC3 for PCNT_ROUTE */
+#define _PCNT_ROUTE_LOCATION_LOC4         0x00000004UL                        /**< Mode LOC4 for PCNT_ROUTE */
+#define PCNT_ROUTE_LOCATION_LOC0          (_PCNT_ROUTE_LOCATION_LOC0 << 8)    /**< Shifted mode LOC0 for PCNT_ROUTE */
+#define PCNT_ROUTE_LOCATION_DEFAULT       (_PCNT_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTE */
+#define PCNT_ROUTE_LOCATION_LOC1          (_PCNT_ROUTE_LOCATION_LOC1 << 8)    /**< Shifted mode LOC1 for PCNT_ROUTE */
+#define PCNT_ROUTE_LOCATION_LOC2          (_PCNT_ROUTE_LOCATION_LOC2 << 8)    /**< Shifted mode LOC2 for PCNT_ROUTE */
+#define PCNT_ROUTE_LOCATION_LOC3          (_PCNT_ROUTE_LOCATION_LOC3 << 8)    /**< Shifted mode LOC3 for PCNT_ROUTE */
+#define PCNT_ROUTE_LOCATION_LOC4          (_PCNT_ROUTE_LOCATION_LOC4 << 8)    /**< Shifted mode LOC4 for PCNT_ROUTE */
+
+/* Bit fields for PCNT FREEZE */
+#define _PCNT_FREEZE_RESETVALUE           0x00000000UL                          /**< Default value for PCNT_FREEZE */
+#define _PCNT_FREEZE_MASK                 0x00000001UL                          /**< Mask for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE             (0x1UL << 0)                          /**< Register Update Freeze */
+#define _PCNT_FREEZE_REGFREEZE_SHIFT      0                                     /**< Shift value for PCNT_REGFREEZE */
+#define _PCNT_FREEZE_REGFREEZE_MASK       0x1UL                                 /**< Bit mask for PCNT_REGFREEZE */
+#define _PCNT_FREEZE_REGFREEZE_DEFAULT    0x00000000UL                          /**< Mode DEFAULT for PCNT_FREEZE */
+#define _PCNT_FREEZE_REGFREEZE_UPDATE     0x00000000UL                          /**< Mode UPDATE for PCNT_FREEZE */
+#define _PCNT_FREEZE_REGFREEZE_FREEZE     0x00000001UL                          /**< Mode FREEZE for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE_DEFAULT     (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE_UPDATE      (_PCNT_FREEZE_REGFREEZE_UPDATE << 0)  /**< Shifted mode UPDATE for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE_FREEZE      (_PCNT_FREEZE_REGFREEZE_FREEZE << 0)  /**< Shifted mode FREEZE for PCNT_FREEZE */
+
+/* Bit fields for PCNT SYNCBUSY */
+#define _PCNT_SYNCBUSY_RESETVALUE         0x00000000UL                       /**< Default value for PCNT_SYNCBUSY */
+#define _PCNT_SYNCBUSY_MASK               0x00000007UL                       /**< Mask for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CTRL                (0x1UL << 0)                       /**< CTRL Register Busy */
+#define _PCNT_SYNCBUSY_CTRL_SHIFT         0                                  /**< Shift value for PCNT_CTRL */
+#define _PCNT_SYNCBUSY_CTRL_MASK          0x1UL                              /**< Bit mask for PCNT_CTRL */
+#define _PCNT_SYNCBUSY_CTRL_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CTRL_DEFAULT        (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CMD                 (0x1UL << 1)                       /**< CMD Register Busy */
+#define _PCNT_SYNCBUSY_CMD_SHIFT          1                                  /**< Shift value for PCNT_CMD */
+#define _PCNT_SYNCBUSY_CMD_MASK           0x2UL                              /**< Bit mask for PCNT_CMD */
+#define _PCNT_SYNCBUSY_CMD_DEFAULT        0x00000000UL                       /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CMD_DEFAULT         (_PCNT_SYNCBUSY_CMD_DEFAULT << 1)  /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_TOPB                (0x1UL << 2)                       /**< TOPB Register Busy */
+#define _PCNT_SYNCBUSY_TOPB_SHIFT         2                                  /**< Shift value for PCNT_TOPB */
+#define _PCNT_SYNCBUSY_TOPB_MASK          0x4UL                              /**< Bit mask for PCNT_TOPB */
+#define _PCNT_SYNCBUSY_TOPB_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_TOPB_DEFAULT        (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+
+/* Bit fields for PCNT AUXCNT */
+#define _PCNT_AUXCNT_RESETVALUE           0x00000000UL                       /**< Default value for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_MASK                 0x0000FFFFUL                       /**< Mask for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_SHIFT         0                                  /**< Shift value for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_MASK          0xFFFFUL                           /**< Bit mask for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for PCNT_AUXCNT */
+#define PCNT_AUXCNT_AUXCNT_DEFAULT        (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */
+
+/* Bit fields for PCNT INPUT */
+#define _PCNT_INPUT_RESETVALUE            0x00000000UL                        /**< Default value for PCNT_INPUT */
+#define _PCNT_INPUT_MASK                  0x000005D7UL                        /**< Mask for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_SHIFT        0                                   /**< Shift value for PCNT_S0PRSSEL */
+#define _PCNT_INPUT_S0PRSSEL_MASK         0x7UL                               /**< Bit mask for PCNT_S0PRSSEL */
+#define _PCNT_INPUT_S0PRSSEL_DEFAULT      0x00000000UL                        /**< Mode DEFAULT for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH0       0x00000000UL                        /**< Mode PRSCH0 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH1       0x00000001UL                        /**< Mode PRSCH1 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH2       0x00000002UL                        /**< Mode PRSCH2 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH3       0x00000003UL                        /**< Mode PRSCH3 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH4       0x00000004UL                        /**< Mode PRSCH4 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH5       0x00000005UL                        /**< Mode PRSCH5 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_DEFAULT       (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH0        (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0)  /**< Shifted mode PRSCH0 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH1        (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0)  /**< Shifted mode PRSCH1 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH2        (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0)  /**< Shifted mode PRSCH2 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH3        (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0)  /**< Shifted mode PRSCH3 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH4        (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0)  /**< Shifted mode PRSCH4 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH5        (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0)  /**< Shifted mode PRSCH5 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSEN                (0x1UL << 4)                        /**< S0IN PRS Enable */
+#define _PCNT_INPUT_S0PRSEN_SHIFT         4                                   /**< Shift value for PCNT_S0PRSEN */
+#define _PCNT_INPUT_S0PRSEN_MASK          0x10UL                              /**< Bit mask for PCNT_S0PRSEN */
+#define _PCNT_INPUT_S0PRSEN_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSEN_DEFAULT        (_PCNT_INPUT_S0PRSEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_SHIFT        6                                   /**< Shift value for PCNT_S1PRSSEL */
+#define _PCNT_INPUT_S1PRSSEL_MASK         0x1C0UL                             /**< Bit mask for PCNT_S1PRSSEL */
+#define _PCNT_INPUT_S1PRSSEL_DEFAULT      0x00000000UL                        /**< Mode DEFAULT for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH0       0x00000000UL                        /**< Mode PRSCH0 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH1       0x00000001UL                        /**< Mode PRSCH1 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH2       0x00000002UL                        /**< Mode PRSCH2 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH3       0x00000003UL                        /**< Mode PRSCH3 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH4       0x00000004UL                        /**< Mode PRSCH4 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH5       0x00000005UL                        /**< Mode PRSCH5 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_DEFAULT       (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH0        (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6)  /**< Shifted mode PRSCH0 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH1        (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6)  /**< Shifted mode PRSCH1 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH2        (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6)  /**< Shifted mode PRSCH2 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH3        (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6)  /**< Shifted mode PRSCH3 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH4        (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6)  /**< Shifted mode PRSCH4 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH5        (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6)  /**< Shifted mode PRSCH5 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSEN                (0x1UL << 10)                       /**< S1IN PRS Enable */
+#define _PCNT_INPUT_S1PRSEN_SHIFT         10                                  /**< Shift value for PCNT_S1PRSEN */
+#define _PCNT_INPUT_S1PRSEN_MASK          0x400UL                             /**< Bit mask for PCNT_S1PRSEN */
+#define _PCNT_INPUT_S1PRSEN_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSEN_DEFAULT        (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */
+
+/** @} End of group EFM32HG_PCNT */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_prs.h

@@ -0,0 +1,370 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_PRS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_PRS
+ * @{
+ * @brief EFM32HG_PRS Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t SWPULSE;       /**< Software Pulse Register  */
+  __IOM uint32_t SWLEVEL;       /**< Software Level Register  */
+  __IOM uint32_t ROUTE;         /**< I/O Routing Register  */
+
+  uint32_t       RESERVED0[1U]; /**< Reserved registers */
+  PRS_CH_TypeDef CH[6U];        /**< Channel registers */
+
+  uint32_t       RESERVED1[6U]; /**< Reserved for future use **/
+  __IOM uint32_t TRACECTRL;     /**< MTB Trace Control Register  */
+} PRS_TypeDef;                  /**< PRS Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_PRS_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for PRS SWPULSE */
+#define _PRS_SWPULSE_RESETVALUE              0x00000000UL                         /**< Default value for PRS_SWPULSE */
+#define _PRS_SWPULSE_MASK                    0x0000003FUL                         /**< Mask for PRS_SWPULSE */
+#define PRS_SWPULSE_CH0PULSE                 (0x1UL << 0)                         /**< Channel 0 Pulse Generation */
+#define _PRS_SWPULSE_CH0PULSE_SHIFT          0                                    /**< Shift value for PRS_CH0PULSE */
+#define _PRS_SWPULSE_CH0PULSE_MASK           0x1UL                                /**< Bit mask for PRS_CH0PULSE */
+#define _PRS_SWPULSE_CH0PULSE_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH0PULSE_DEFAULT         (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH1PULSE                 (0x1UL << 1)                         /**< Channel 1 Pulse Generation */
+#define _PRS_SWPULSE_CH1PULSE_SHIFT          1                                    /**< Shift value for PRS_CH1PULSE */
+#define _PRS_SWPULSE_CH1PULSE_MASK           0x2UL                                /**< Bit mask for PRS_CH1PULSE */
+#define _PRS_SWPULSE_CH1PULSE_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH1PULSE_DEFAULT         (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH2PULSE                 (0x1UL << 2)                         /**< Channel 2 Pulse Generation */
+#define _PRS_SWPULSE_CH2PULSE_SHIFT          2                                    /**< Shift value for PRS_CH2PULSE */
+#define _PRS_SWPULSE_CH2PULSE_MASK           0x4UL                                /**< Bit mask for PRS_CH2PULSE */
+#define _PRS_SWPULSE_CH2PULSE_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH2PULSE_DEFAULT         (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH3PULSE                 (0x1UL << 3)                         /**< Channel 3 Pulse Generation */
+#define _PRS_SWPULSE_CH3PULSE_SHIFT          3                                    /**< Shift value for PRS_CH3PULSE */
+#define _PRS_SWPULSE_CH3PULSE_MASK           0x8UL                                /**< Bit mask for PRS_CH3PULSE */
+#define _PRS_SWPULSE_CH3PULSE_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH3PULSE_DEFAULT         (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH4PULSE                 (0x1UL << 4)                         /**< Channel 4 Pulse Generation */
+#define _PRS_SWPULSE_CH4PULSE_SHIFT          4                                    /**< Shift value for PRS_CH4PULSE */
+#define _PRS_SWPULSE_CH4PULSE_MASK           0x10UL                               /**< Bit mask for PRS_CH4PULSE */
+#define _PRS_SWPULSE_CH4PULSE_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH4PULSE_DEFAULT         (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH5PULSE                 (0x1UL << 5)                         /**< Channel 5 Pulse Generation */
+#define _PRS_SWPULSE_CH5PULSE_SHIFT          5                                    /**< Shift value for PRS_CH5PULSE */
+#define _PRS_SWPULSE_CH5PULSE_MASK           0x20UL                               /**< Bit mask for PRS_CH5PULSE */
+#define _PRS_SWPULSE_CH5PULSE_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH5PULSE_DEFAULT         (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+
+/* Bit fields for PRS SWLEVEL */
+#define _PRS_SWLEVEL_RESETVALUE              0x00000000UL                         /**< Default value for PRS_SWLEVEL */
+#define _PRS_SWLEVEL_MASK                    0x0000003FUL                         /**< Mask for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH0LEVEL                 (0x1UL << 0)                         /**< Channel 0 Software Level */
+#define _PRS_SWLEVEL_CH0LEVEL_SHIFT          0                                    /**< Shift value for PRS_CH0LEVEL */
+#define _PRS_SWLEVEL_CH0LEVEL_MASK           0x1UL                                /**< Bit mask for PRS_CH0LEVEL */
+#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH0LEVEL_DEFAULT         (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH1LEVEL                 (0x1UL << 1)                         /**< Channel 1 Software Level */
+#define _PRS_SWLEVEL_CH1LEVEL_SHIFT          1                                    /**< Shift value for PRS_CH1LEVEL */
+#define _PRS_SWLEVEL_CH1LEVEL_MASK           0x2UL                                /**< Bit mask for PRS_CH1LEVEL */
+#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH1LEVEL_DEFAULT         (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH2LEVEL                 (0x1UL << 2)                         /**< Channel 2 Software Level */
+#define _PRS_SWLEVEL_CH2LEVEL_SHIFT          2                                    /**< Shift value for PRS_CH2LEVEL */
+#define _PRS_SWLEVEL_CH2LEVEL_MASK           0x4UL                                /**< Bit mask for PRS_CH2LEVEL */
+#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH2LEVEL_DEFAULT         (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH3LEVEL                 (0x1UL << 3)                         /**< Channel 3 Software Level */
+#define _PRS_SWLEVEL_CH3LEVEL_SHIFT          3                                    /**< Shift value for PRS_CH3LEVEL */
+#define _PRS_SWLEVEL_CH3LEVEL_MASK           0x8UL                                /**< Bit mask for PRS_CH3LEVEL */
+#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH3LEVEL_DEFAULT         (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH4LEVEL                 (0x1UL << 4)                         /**< Channel 4 Software Level */
+#define _PRS_SWLEVEL_CH4LEVEL_SHIFT          4                                    /**< Shift value for PRS_CH4LEVEL */
+#define _PRS_SWLEVEL_CH4LEVEL_MASK           0x10UL                               /**< Bit mask for PRS_CH4LEVEL */
+#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH4LEVEL_DEFAULT         (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH5LEVEL                 (0x1UL << 5)                         /**< Channel 5 Software Level */
+#define _PRS_SWLEVEL_CH5LEVEL_SHIFT          5                                    /**< Shift value for PRS_CH5LEVEL */
+#define _PRS_SWLEVEL_CH5LEVEL_MASK           0x20UL                               /**< Bit mask for PRS_CH5LEVEL */
+#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH5LEVEL_DEFAULT         (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+
+/* Bit fields for PRS ROUTE */
+#define _PRS_ROUTE_RESETVALUE                0x00000000UL                       /**< Default value for PRS_ROUTE */
+#define _PRS_ROUTE_MASK                      0x0000070FUL                       /**< Mask for PRS_ROUTE */
+#define PRS_ROUTE_CH0PEN                     (0x1UL << 0)                       /**< CH0 Pin Enable */
+#define _PRS_ROUTE_CH0PEN_SHIFT              0                                  /**< Shift value for PRS_CH0PEN */
+#define _PRS_ROUTE_CH0PEN_MASK               0x1UL                              /**< Bit mask for PRS_CH0PEN */
+#define _PRS_ROUTE_CH0PEN_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for PRS_ROUTE */
+#define PRS_ROUTE_CH0PEN_DEFAULT             (_PRS_ROUTE_CH0PEN_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_ROUTE */
+#define PRS_ROUTE_CH1PEN                     (0x1UL << 1)                       /**< CH1 Pin Enable */
+#define _PRS_ROUTE_CH1PEN_SHIFT              1                                  /**< Shift value for PRS_CH1PEN */
+#define _PRS_ROUTE_CH1PEN_MASK               0x2UL                              /**< Bit mask for PRS_CH1PEN */
+#define _PRS_ROUTE_CH1PEN_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for PRS_ROUTE */
+#define PRS_ROUTE_CH1PEN_DEFAULT             (_PRS_ROUTE_CH1PEN_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_ROUTE */
+#define PRS_ROUTE_CH2PEN                     (0x1UL << 2)                       /**< CH2 Pin Enable */
+#define _PRS_ROUTE_CH2PEN_SHIFT              2                                  /**< Shift value for PRS_CH2PEN */
+#define _PRS_ROUTE_CH2PEN_MASK               0x4UL                              /**< Bit mask for PRS_CH2PEN */
+#define _PRS_ROUTE_CH2PEN_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for PRS_ROUTE */
+#define PRS_ROUTE_CH2PEN_DEFAULT             (_PRS_ROUTE_CH2PEN_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_ROUTE */
+#define PRS_ROUTE_CH3PEN                     (0x1UL << 3)                       /**< CH3 Pin Enable */
+#define _PRS_ROUTE_CH3PEN_SHIFT              3                                  /**< Shift value for PRS_CH3PEN */
+#define _PRS_ROUTE_CH3PEN_MASK               0x8UL                              /**< Bit mask for PRS_CH3PEN */
+#define _PRS_ROUTE_CH3PEN_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for PRS_ROUTE */
+#define PRS_ROUTE_CH3PEN_DEFAULT             (_PRS_ROUTE_CH3PEN_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_ROUTE */
+#define _PRS_ROUTE_LOCATION_SHIFT            8                                  /**< Shift value for PRS_LOCATION */
+#define _PRS_ROUTE_LOCATION_MASK             0x700UL                            /**< Bit mask for PRS_LOCATION */
+#define _PRS_ROUTE_LOCATION_LOC0             0x00000000UL                       /**< Mode LOC0 for PRS_ROUTE */
+#define _PRS_ROUTE_LOCATION_DEFAULT          0x00000000UL                       /**< Mode DEFAULT for PRS_ROUTE */
+#define _PRS_ROUTE_LOCATION_LOC1             0x00000001UL                       /**< Mode LOC1 for PRS_ROUTE */
+#define _PRS_ROUTE_LOCATION_LOC2             0x00000002UL                       /**< Mode LOC2 for PRS_ROUTE */
+#define _PRS_ROUTE_LOCATION_LOC3             0x00000003UL                       /**< Mode LOC3 for PRS_ROUTE */
+#define PRS_ROUTE_LOCATION_LOC0              (_PRS_ROUTE_LOCATION_LOC0 << 8)    /**< Shifted mode LOC0 for PRS_ROUTE */
+#define PRS_ROUTE_LOCATION_DEFAULT           (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */
+#define PRS_ROUTE_LOCATION_LOC1              (_PRS_ROUTE_LOCATION_LOC1 << 8)    /**< Shifted mode LOC1 for PRS_ROUTE */
+#define PRS_ROUTE_LOCATION_LOC2              (_PRS_ROUTE_LOCATION_LOC2 << 8)    /**< Shifted mode LOC2 for PRS_ROUTE */
+#define PRS_ROUTE_LOCATION_LOC3              (_PRS_ROUTE_LOCATION_LOC3 << 8)    /**< Shifted mode LOC3 for PRS_ROUTE */
+
+/* Bit fields for PRS CH_CTRL */
+#define _PRS_CH_CTRL_RESETVALUE              0x00000000UL                             /**< Default value for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_MASK                    0x133F0007UL                             /**< Mask for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_SHIFT            0                                        /**< Shift value for PRS_SIGSEL */
+#define _PRS_CH_CTRL_SIGSEL_MASK             0x7UL                                    /**< Bit mask for PRS_SIGSEL */
+#define _PRS_CH_CTRL_SIGSEL_VCMPOUT          0x00000000UL                             /**< Mode VCMPOUT for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT         0x00000000UL                             /**< Mode ACMP0OUT for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE       0x00000000UL                             /**< Mode ADC0SINGLE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0IRTX       0x00000000UL                             /**< Mode USART0IRTX for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1IRTX       0x00000000UL                             /**< Mode USART1IRTX for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0UF         0x00000000UL                             /**< Mode TIMER0UF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1UF         0x00000000UL                             /**< Mode TIMER1UF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER2UF         0x00000000UL                             /**< Mode TIMER2UF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USBSOF           0x00000000UL                             /**< Mode USBSOF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_RTCOF            0x00000000UL                             /**< Mode RTCOF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0         0x00000000UL                             /**< Mode GPIOPIN0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8         0x00000000UL                             /**< Mode GPIOPIN8 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC         0x00000000UL                             /**< Mode PCNT0TCC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN         0x00000001UL                             /**< Mode ADC0SCAN for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0TXC        0x00000001UL                             /**< Mode USART0TXC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1TXC        0x00000001UL                             /**< Mode USART1TXC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0OF         0x00000001UL                             /**< Mode TIMER0OF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1OF         0x00000001UL                             /**< Mode TIMER1OF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER2OF         0x00000001UL                             /**< Mode TIMER2OF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USBSOFSR         0x00000001UL                             /**< Mode USBSOFSR for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0         0x00000001UL                             /**< Mode RTCCOMP0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1         0x00000001UL                             /**< Mode GPIOPIN1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9         0x00000001UL                             /**< Mode GPIOPIN9 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV    0x00000002UL                             /**< Mode USART0RXDATAV for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV    0x00000002UL                             /**< Mode USART1RXDATAV for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0        0x00000002UL                             /**< Mode TIMER0CC0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0        0x00000002UL                             /**< Mode TIMER1CC0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0        0x00000002UL                             /**< Mode TIMER2CC0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1         0x00000002UL                             /**< Mode RTCCOMP1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2         0x00000002UL                             /**< Mode GPIOPIN2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10        0x00000002UL                             /**< Mode GPIOPIN10 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1        0x00000003UL                             /**< Mode TIMER0CC1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1        0x00000003UL                             /**< Mode TIMER1CC1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1        0x00000003UL                             /**< Mode TIMER2CC1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3         0x00000003UL                             /**< Mode GPIOPIN3 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11        0x00000003UL                             /**< Mode GPIOPIN11 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2        0x00000004UL                             /**< Mode TIMER0CC2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2        0x00000004UL                             /**< Mode TIMER1CC2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2        0x00000004UL                             /**< Mode TIMER2CC2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4         0x00000004UL                             /**< Mode GPIOPIN4 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12        0x00000004UL                             /**< Mode GPIOPIN12 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5         0x00000005UL                             /**< Mode GPIOPIN5 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13        0x00000005UL                             /**< Mode GPIOPIN13 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6         0x00000006UL                             /**< Mode GPIOPIN6 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14        0x00000006UL                             /**< Mode GPIOPIN14 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7         0x00000007UL                             /**< Mode GPIOPIN7 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15        0x00000007UL                             /**< Mode GPIOPIN15 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_VCMPOUT           (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)       /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ACMP0OUT          (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)      /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE        (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)    /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0IRTX        (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)    /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1IRTX        (_PRS_CH_CTRL_SIGSEL_USART1IRTX << 0)    /**< Shifted mode USART1IRTX for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0UF          (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)      /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1UF          (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)      /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER2UF          (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0)      /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USBSOF            (_PRS_CH_CTRL_SIGSEL_USBSOF << 0)        /**< Shifted mode USBSOF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_RTCOF             (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)         /**< Shifted mode RTCOF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN0          (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)      /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN8          (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)      /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PCNT0TCC          (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0)      /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ADC0SCAN          (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)      /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0TXC         (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)     /**< Shifted mode USART0TXC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1TXC         (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)     /**< Shifted mode USART1TXC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0OF          (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)      /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1OF          (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)      /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER2OF          (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0)      /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USBSOFSR          (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0)      /**< Shifted mode USBSOFSR for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_RTCCOMP0          (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)      /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN1          (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)      /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN9          (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)      /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC0         (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)     /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC0         (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)     /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER2CC0         (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0)     /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_RTCCOMP1          (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)      /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN2          (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)      /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN10         (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)     /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC1         (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)     /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC1         (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)     /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER2CC1         (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0)     /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN3          (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)      /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN11         (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)     /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC2         (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)     /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC2         (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)     /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER2CC2         (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0)     /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN4          (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)      /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN12         (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)     /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN5          (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)      /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN13         (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)     /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN6          (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)      /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN14         (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)     /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN7          (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)      /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN15         (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)     /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_SHIFT         16                                       /**< Shift value for PRS_SOURCESEL */
+#define _PRS_CH_CTRL_SOURCESEL_MASK          0x3F0000UL                               /**< Bit mask for PRS_SOURCESEL */
+#define _PRS_CH_CTRL_SOURCESEL_NONE          0x00000000UL                             /**< Mode NONE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_VCMP          0x00000001UL                             /**< Mode VCMP for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_ACMP0         0x00000002UL                             /**< Mode ACMP0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_ADC0          0x00000008UL                             /**< Mode ADC0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_USART0        0x00000010UL                             /**< Mode USART0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_USART1        0x00000011UL                             /**< Mode USART1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_TIMER0        0x0000001CUL                             /**< Mode TIMER0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_TIMER1        0x0000001DUL                             /**< Mode TIMER1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_TIMER2        0x0000001EUL                             /**< Mode TIMER2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_USB           0x00000024UL                             /**< Mode USB for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_RTC           0x00000028UL                             /**< Mode RTC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_GPIOL         0x00000030UL                             /**< Mode GPIOL for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_GPIOH         0x00000031UL                             /**< Mode GPIOH for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_PCNT0         0x00000036UL                             /**< Mode PCNT0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_NONE           (_PRS_CH_CTRL_SOURCESEL_NONE << 16)      /**< Shifted mode NONE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_VCMP           (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)      /**< Shifted mode VCMP for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_ACMP0          (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)     /**< Shifted mode ACMP0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_ADC0           (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16)      /**< Shifted mode ADC0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_USART0         (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)    /**< Shifted mode USART0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_USART1         (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)    /**< Shifted mode USART1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_TIMER0         (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)    /**< Shifted mode TIMER0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_TIMER1         (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)    /**< Shifted mode TIMER1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_TIMER2         (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16)    /**< Shifted mode TIMER2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_USB            (_PRS_CH_CTRL_SOURCESEL_USB << 16)       /**< Shifted mode USB for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_RTC            (_PRS_CH_CTRL_SOURCESEL_RTC << 16)       /**< Shifted mode RTC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_GPIOL          (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)     /**< Shifted mode GPIOL for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_GPIOH          (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)     /**< Shifted mode GPIOH for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_PCNT0          (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 16)     /**< Shifted mode PCNT0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_SHIFT             24                                       /**< Shift value for PRS_EDSEL */
+#define _PRS_CH_CTRL_EDSEL_MASK              0x3000000UL                              /**< Bit mask for PRS_EDSEL */
+#define _PRS_CH_CTRL_EDSEL_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_OFF               0x00000000UL                             /**< Mode OFF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_POSEDGE           0x00000001UL                             /**< Mode POSEDGE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_NEGEDGE           0x00000002UL                             /**< Mode NEGEDGE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_BOTHEDGES         0x00000003UL                             /**< Mode BOTHEDGES for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_DEFAULT            (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)       /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_OFF                (_PRS_CH_CTRL_EDSEL_OFF << 24)           /**< Shifted mode OFF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_POSEDGE            (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)       /**< Shifted mode POSEDGE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_NEGEDGE            (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)       /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_BOTHEDGES          (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)     /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ASYNC                    (0x1UL << 28)                            /**< Asynchronous reflex */
+#define _PRS_CH_CTRL_ASYNC_SHIFT             28                                       /**< Shift value for PRS_ASYNC */
+#define _PRS_CH_CTRL_ASYNC_MASK              0x10000000UL                             /**< Bit mask for PRS_ASYNC */
+#define _PRS_CH_CTRL_ASYNC_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ASYNC_DEFAULT            (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)       /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+
+/* Bit fields for PRS TRACECTRL */
+#define _PRS_TRACECTRL_RESETVALUE            0x00000000UL                           /**< Default value for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_MASK                  0x00000F0FUL                           /**< Mask for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTARTEN               (0x1UL << 0)                           /**< PRS TSTART Enable */
+#define _PRS_TRACECTRL_TSTARTEN_SHIFT        0                                      /**< Shift value for PRS_TSTARTEN */
+#define _PRS_TRACECTRL_TSTARTEN_MASK         0x1UL                                  /**< Bit mask for PRS_TSTARTEN */
+#define _PRS_TRACECTRL_TSTARTEN_DEFAULT      0x00000000UL                           /**< Mode DEFAULT for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTARTEN_DEFAULT       (_PRS_TRACECTRL_TSTARTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTART_SHIFT          1                                      /**< Shift value for PRS_TSTART */
+#define _PRS_TRACECTRL_TSTART_MASK           0xEUL                                  /**< Bit mask for PRS_TSTART */
+#define _PRS_TRACECTRL_TSTART_DEFAULT        0x00000000UL                           /**< Mode DEFAULT for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTART_PRSCH0         0x00000000UL                           /**< Mode PRSCH0 for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTART_PRSCH1         0x00000001UL                           /**< Mode PRSCH1 for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTART_PRSCH2         0x00000002UL                           /**< Mode PRSCH2 for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTART_PRSCH3         0x00000003UL                           /**< Mode PRSCH3 for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTART_PRSCH4         0x00000004UL                           /**< Mode PRSCH4 for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTART_PRSCH5         0x00000005UL                           /**< Mode PRSCH5 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTART_DEFAULT         (_PRS_TRACECTRL_TSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTART_PRSCH0          (_PRS_TRACECTRL_TSTART_PRSCH0 << 1)    /**< Shifted mode PRSCH0 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTART_PRSCH1          (_PRS_TRACECTRL_TSTART_PRSCH1 << 1)    /**< Shifted mode PRSCH1 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTART_PRSCH2          (_PRS_TRACECTRL_TSTART_PRSCH2 << 1)    /**< Shifted mode PRSCH2 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTART_PRSCH3          (_PRS_TRACECTRL_TSTART_PRSCH3 << 1)    /**< Shifted mode PRSCH3 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTART_PRSCH4          (_PRS_TRACECTRL_TSTART_PRSCH4 << 1)    /**< Shifted mode PRSCH4 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTART_PRSCH5          (_PRS_TRACECTRL_TSTART_PRSCH5 << 1)    /**< Shifted mode PRSCH5 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTOPEN                (0x1UL << 8)                           /**< PRS TSTOP Enable */
+#define _PRS_TRACECTRL_TSTOPEN_SHIFT         8                                      /**< Shift value for PRS_TSTOPEN */
+#define _PRS_TRACECTRL_TSTOPEN_MASK          0x100UL                                /**< Bit mask for PRS_TSTOPEN */
+#define _PRS_TRACECTRL_TSTOPEN_DEFAULT       0x00000000UL                           /**< Mode DEFAULT for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTOPEN_DEFAULT        (_PRS_TRACECTRL_TSTOPEN_DEFAULT << 8)  /**< Shifted mode DEFAULT for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTOP_SHIFT           9                                      /**< Shift value for PRS_TSTOP */
+#define _PRS_TRACECTRL_TSTOP_MASK            0xE00UL                                /**< Bit mask for PRS_TSTOP */
+#define _PRS_TRACECTRL_TSTOP_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTOP_PRSCH0          0x00000000UL                           /**< Mode PRSCH0 for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTOP_PRSCH1          0x00000001UL                           /**< Mode PRSCH1 for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTOP_PRSCH2          0x00000002UL                           /**< Mode PRSCH2 for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTOP_PRSCH3          0x00000003UL                           /**< Mode PRSCH3 for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTOP_PRSCH4          0x00000004UL                           /**< Mode PRSCH4 for PRS_TRACECTRL */
+#define _PRS_TRACECTRL_TSTOP_PRSCH5          0x00000005UL                           /**< Mode PRSCH5 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTOP_DEFAULT          (_PRS_TRACECTRL_TSTOP_DEFAULT << 9)    /**< Shifted mode DEFAULT for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTOP_PRSCH0           (_PRS_TRACECTRL_TSTOP_PRSCH0 << 9)     /**< Shifted mode PRSCH0 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTOP_PRSCH1           (_PRS_TRACECTRL_TSTOP_PRSCH1 << 9)     /**< Shifted mode PRSCH1 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTOP_PRSCH2           (_PRS_TRACECTRL_TSTOP_PRSCH2 << 9)     /**< Shifted mode PRSCH2 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTOP_PRSCH3           (_PRS_TRACECTRL_TSTOP_PRSCH3 << 9)     /**< Shifted mode PRSCH3 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTOP_PRSCH4           (_PRS_TRACECTRL_TSTOP_PRSCH4 << 9)     /**< Shifted mode PRSCH4 for PRS_TRACECTRL */
+#define PRS_TRACECTRL_TSTOP_PRSCH5           (_PRS_TRACECTRL_TSTOP_PRSCH5 << 9)     /**< Shifted mode PRSCH5 for PRS_TRACECTRL */
+
+/** @} End of group EFM32HG_PRS */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_prs_ch.h

@@ -0,0 +1,57 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_PRS_CH register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief PRS_CH EFM32HG PRS CH
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL; /**< Channel Control Register  */
+} PRS_CH_TypeDef;
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_prs_signals.h

@@ -0,0 +1,104 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_PRS_SIGNALS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFM32HG_PRS_Signals
+ * @{
+ * @brief PRS Signal names
+ ******************************************************************************/
+#define PRS_VCMP_OUT          ((1 << 16) + 0)  /**< PRS Voltage comparator output */
+#define PRS_ACMP0_OUT         ((2 << 16) + 0)  /**< PRS Analog comparator output */
+#define PRS_ADC0_SINGLE       ((8 << 16) + 0)  /**< PRS ADC single conversion done */
+#define PRS_ADC0_SCAN         ((8 << 16) + 1)  /**< PRS ADC scan conversion done */
+#define PRS_USART0_IRTX       ((16 << 16) + 0) /**< PRS USART 0 IRDA out */
+#define PRS_USART0_TXC        ((16 << 16) + 1) /**< PRS USART 0 TX complete */
+#define PRS_USART0_RXDATAV    ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */
+#define PRS_USART1_IRTX       ((17 << 16) + 0) /**< PRS USART 1 IRDA out */
+#define PRS_USART1_TXC        ((17 << 16) + 1) /**< PRS USART 1 TX complete */
+#define PRS_USART1_RXDATAV    ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */
+#define PRS_TIMER0_UF         ((28 << 16) + 0) /**< PRS Timer 0 Underflow */
+#define PRS_TIMER0_OF         ((28 << 16) + 1) /**< PRS Timer 0 Overflow */
+#define PRS_TIMER0_CC0        ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */
+#define PRS_TIMER0_CC1        ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */
+#define PRS_TIMER0_CC2        ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */
+#define PRS_TIMER1_UF         ((29 << 16) + 0) /**< PRS Timer 1 Underflow */
+#define PRS_TIMER1_OF         ((29 << 16) + 1) /**< PRS Timer 1 Overflow */
+#define PRS_TIMER1_CC0        ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */
+#define PRS_TIMER1_CC1        ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */
+#define PRS_TIMER1_CC2        ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */
+#define PRS_TIMER2_UF         ((30 << 16) + 0) /**< PRS Timer 2 Underflow */
+#define PRS_TIMER2_OF         ((30 << 16) + 1) /**< PRS Timer 2 Overflow */
+#define PRS_TIMER2_CC0        ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */
+#define PRS_TIMER2_CC1        ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */
+#define PRS_TIMER2_CC2        ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */
+#define PRS_USB_SOF           ((36 << 16) + 0) /**< PRS USB Start of Frame */
+#define PRS_USB_SOFSR         ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */
+#define PRS_RTC_OF            ((40 << 16) + 0) /**< PRS RTC Overflow */
+#define PRS_RTC_COMP0         ((40 << 16) + 1) /**< PRS RTC Compare 0 */
+#define PRS_RTC_COMP1         ((40 << 16) + 2) /**< PRS RTC Compare 1 */
+#define PRS_GPIO_PIN0         ((48 << 16) + 0) /**< PRS GPIO pin 0 */
+#define PRS_GPIO_PIN1         ((48 << 16) + 1) /**< PRS GPIO pin 1 */
+#define PRS_GPIO_PIN2         ((48 << 16) + 2) /**< PRS GPIO pin 2 */
+#define PRS_GPIO_PIN3         ((48 << 16) + 3) /**< PRS GPIO pin 3 */
+#define PRS_GPIO_PIN4         ((48 << 16) + 4) /**< PRS GPIO pin 4 */
+#define PRS_GPIO_PIN5         ((48 << 16) + 5) /**< PRS GPIO pin 5 */
+#define PRS_GPIO_PIN6         ((48 << 16) + 6) /**< PRS GPIO pin 6 */
+#define PRS_GPIO_PIN7         ((48 << 16) + 7) /**< PRS GPIO pin 7 */
+#define PRS_GPIO_PIN8         ((49 << 16) + 0) /**< PRS GPIO pin 8 */
+#define PRS_GPIO_PIN9         ((49 << 16) + 1) /**< PRS GPIO pin 9 */
+#define PRS_GPIO_PIN10        ((49 << 16) + 2) /**< PRS GPIO pin 10 */
+#define PRS_GPIO_PIN11        ((49 << 16) + 3) /**< PRS GPIO pin 11 */
+#define PRS_GPIO_PIN12        ((49 << 16) + 4) /**< PRS GPIO pin 12 */
+#define PRS_GPIO_PIN13        ((49 << 16) + 5) /**< PRS GPIO pin 13 */
+#define PRS_GPIO_PIN14        ((49 << 16) + 6) /**< PRS GPIO pin 14 */
+#define PRS_GPIO_PIN15        ((49 << 16) + 7) /**< PRS GPIO pin 15 */
+#define PRS_PCNT0_TCC         ((54 << 16) + 0) /**< PRS Triggered compare match */
+
+/** @} End of group EFM32HG_PRS */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_rmu.h

@@ -0,0 +1,144 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_RMU register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_RMU
+ * @{
+ * @brief EFM32HG_RMU Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;     /**< Control Register  */
+  __IM uint32_t  RSTCAUSE; /**< Reset Cause Register  */
+  __OM uint32_t  CMD;      /**< Command Register  */
+} RMU_TypeDef;             /**< RMU Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_RMU_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for RMU CTRL */
+#define _RMU_CTRL_RESETVALUE                 0x00000000UL                        /**< Default value for RMU_CTRL */
+#define _RMU_CTRL_MASK                       0x00000001UL                        /**< Mask for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRDIS                  (0x1UL << 0)                        /**< Lockup Reset Disable */
+#define _RMU_CTRL_LOCKUPRDIS_SHIFT           0                                   /**< Shift value for RMU_LOCKUPRDIS */
+#define _RMU_CTRL_LOCKUPRDIS_MASK            0x1UL                               /**< Bit mask for RMU_LOCKUPRDIS */
+#define _RMU_CTRL_LOCKUPRDIS_DEFAULT         0x00000000UL                        /**< Mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRDIS_DEFAULT          (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
+
+/* Bit fields for RMU RSTCAUSE */
+#define _RMU_RSTCAUSE_RESETVALUE             0x00000000UL                             /**< Default value for RMU_RSTCAUSE */
+#define _RMU_RSTCAUSE_MASK                   0x000007FFUL                             /**< Mask for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_PORST                   (0x1UL << 0)                             /**< Power On Reset */
+#define _RMU_RSTCAUSE_PORST_SHIFT            0                                        /**< Shift value for RMU_PORST */
+#define _RMU_RSTCAUSE_PORST_MASK             0x1UL                                    /**< Bit mask for RMU_PORST */
+#define _RMU_RSTCAUSE_PORST_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_PORST_DEFAULT           (_RMU_RSTCAUSE_PORST_DEFAULT << 0)       /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODUNREGRST             (0x1UL << 1)                             /**< Brown Out Detector Unregulated Domain Reset */
+#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT      1                                        /**< Shift value for RMU_BODUNREGRST */
+#define _RMU_RSTCAUSE_BODUNREGRST_MASK       0x2UL                                    /**< Bit mask for RMU_BODUNREGRST */
+#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT    0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT     (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODREGRST               (0x1UL << 2)                             /**< Brown Out Detector Regulated Domain Reset */
+#define _RMU_RSTCAUSE_BODREGRST_SHIFT        2                                        /**< Shift value for RMU_BODREGRST */
+#define _RMU_RSTCAUSE_BODREGRST_MASK         0x4UL                                    /**< Bit mask for RMU_BODREGRST */
+#define _RMU_RSTCAUSE_BODREGRST_DEFAULT      0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODREGRST_DEFAULT       (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2)   /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EXTRST                  (0x1UL << 3)                             /**< External Pin Reset */
+#define _RMU_RSTCAUSE_EXTRST_SHIFT           3                                        /**< Shift value for RMU_EXTRST */
+#define _RMU_RSTCAUSE_EXTRST_MASK            0x8UL                                    /**< Bit mask for RMU_EXTRST */
+#define _RMU_RSTCAUSE_EXTRST_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EXTRST_DEFAULT          (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3)      /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_WDOGRST                 (0x1UL << 4)                             /**< Watchdog Reset */
+#define _RMU_RSTCAUSE_WDOGRST_SHIFT          4                                        /**< Shift value for RMU_WDOGRST */
+#define _RMU_RSTCAUSE_WDOGRST_MASK           0x10UL                                   /**< Bit mask for RMU_WDOGRST */
+#define _RMU_RSTCAUSE_WDOGRST_DEFAULT        0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_WDOGRST_DEFAULT         (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4)     /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_LOCKUPRST               (0x1UL << 5)                             /**< LOCKUP Reset */
+#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT        5                                        /**< Shift value for RMU_LOCKUPRST */
+#define _RMU_RSTCAUSE_LOCKUPRST_MASK         0x20UL                                   /**< Bit mask for RMU_LOCKUPRST */
+#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT      0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT       (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5)   /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_SYSREQRST               (0x1UL << 6)                             /**< System Request Reset */
+#define _RMU_RSTCAUSE_SYSREQRST_SHIFT        6                                        /**< Shift value for RMU_SYSREQRST */
+#define _RMU_RSTCAUSE_SYSREQRST_MASK         0x40UL                                   /**< Bit mask for RMU_SYSREQRST */
+#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT      0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_SYSREQRST_DEFAULT       (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6)   /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4RST                  (0x1UL << 7)                             /**< EM4 Reset */
+#define _RMU_RSTCAUSE_EM4RST_SHIFT           7                                        /**< Shift value for RMU_EM4RST */
+#define _RMU_RSTCAUSE_EM4RST_MASK            0x80UL                                   /**< Bit mask for RMU_EM4RST */
+#define _RMU_RSTCAUSE_EM4RST_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4RST_DEFAULT          (_RMU_RSTCAUSE_EM4RST_DEFAULT << 7)      /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4WURST                (0x1UL << 8)                             /**< EM4 Wake-up Reset */
+#define _RMU_RSTCAUSE_EM4WURST_SHIFT         8                                        /**< Shift value for RMU_EM4WURST */
+#define _RMU_RSTCAUSE_EM4WURST_MASK          0x100UL                                  /**< Bit mask for RMU_EM4WURST */
+#define _RMU_RSTCAUSE_EM4WURST_DEFAULT       0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4WURST_DEFAULT        (_RMU_RSTCAUSE_EM4WURST_DEFAULT << 8)    /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODAVDD0                (0x1UL << 9)                             /**< AVDD0 Bod Reset */
+#define _RMU_RSTCAUSE_BODAVDD0_SHIFT         9                                        /**< Shift value for RMU_BODAVDD0 */
+#define _RMU_RSTCAUSE_BODAVDD0_MASK          0x200UL                                  /**< Bit mask for RMU_BODAVDD0 */
+#define _RMU_RSTCAUSE_BODAVDD0_DEFAULT       0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODAVDD0_DEFAULT        (_RMU_RSTCAUSE_BODAVDD0_DEFAULT << 9)    /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODAVDD1                (0x1UL << 10)                            /**< AVDD1 Bod Reset */
+#define _RMU_RSTCAUSE_BODAVDD1_SHIFT         10                                       /**< Shift value for RMU_BODAVDD1 */
+#define _RMU_RSTCAUSE_BODAVDD1_MASK          0x400UL                                  /**< Bit mask for RMU_BODAVDD1 */
+#define _RMU_RSTCAUSE_BODAVDD1_DEFAULT       0x00000000UL                             /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_BODAVDD1_DEFAULT        (_RMU_RSTCAUSE_BODAVDD1_DEFAULT << 10)   /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+
+/* Bit fields for RMU CMD */
+#define _RMU_CMD_RESETVALUE                  0x00000000UL                  /**< Default value for RMU_CMD */
+#define _RMU_CMD_MASK                        0x00000001UL                  /**< Mask for RMU_CMD */
+#define RMU_CMD_RCCLR                        (0x1UL << 0)                  /**< Reset Cause Clear */
+#define _RMU_CMD_RCCLR_SHIFT                 0                             /**< Shift value for RMU_RCCLR */
+#define _RMU_CMD_RCCLR_MASK                  0x1UL                         /**< Bit mask for RMU_RCCLR */
+#define _RMU_CMD_RCCLR_DEFAULT               0x00000000UL                  /**< Mode DEFAULT for RMU_CMD */
+#define RMU_CMD_RCCLR_DEFAULT                (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
+
+/** @} End of group EFM32HG_RMU */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_romtable.h

@@ -0,0 +1,84 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_ROMTABLE register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_ROMTABLE
+ * @{
+ * @brief Chip Information, Revision numbers
+ ******************************************************************************/
+typedef struct {
+  __IM uint32_t PID4; /**< JEP_106_BANK */
+  __IM uint32_t PID5; /**< Unused */
+  __IM uint32_t PID6; /**< Unused */
+  __IM uint32_t PID7; /**< Unused */
+  __IM uint32_t PID0; /**< Chip family LSB, chip major revision */
+  __IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */
+  __IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
+  __IM uint32_t PID3; /**< Chip minor rev LSB */
+  __IM uint32_t CID0; /**< Unused */
+} ROMTABLE_TypeDef;   /** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_ROMTABLE_BitFields
+ * @{
+ ******************************************************************************/
+/* Bit fields for EFM32HG_ROMTABLE */
+#define _ROMTABLE_PID0_FAMILYLSB_MASK       0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */
+#define _ROMTABLE_PID0_FAMILYLSB_SHIFT      6            /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */
+#define _ROMTABLE_PID0_REVMAJOR_MASK        0x0000003FUL /**< CHIP MAJOR Revison, mask */
+#define _ROMTABLE_PID0_REVMAJOR_SHIFT       0            /**< CHIP MAJOR Revison, shift */
+#define _ROMTABLE_PID1_FAMILYMSB_MASK       0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */
+#define _ROMTABLE_PID1_FAMILYMSB_SHIFT      0            /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */
+#define _ROMTABLE_PID2_REVMINORMSB_MASK     0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
+#define _ROMTABLE_PID2_REVMINORMSB_SHIFT    4            /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
+#define _ROMTABLE_PID3_REVMINORLSB_MASK     0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */
+#define _ROMTABLE_PID3_REVMINORLSB_SHIFT    4            /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
+
+/** @} End of group EFM32HG_ROMTABLE */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_rtc.h

@@ -0,0 +1,230 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_RTC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_RTC
+ * @{
+ * @brief EFM32HG_RTC Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;     /**< Control Register  */
+  __IOM uint32_t CNT;      /**< Counter Value Register  */
+  __IOM uint32_t COMP0;    /**< Compare Value Register 0  */
+  __IOM uint32_t COMP1;    /**< Compare Value Register 1  */
+  __IM uint32_t  IF;       /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;      /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;      /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;      /**< Interrupt Enable Register  */
+
+  __IOM uint32_t FREEZE;   /**< Freeze Register  */
+  __IM uint32_t  SYNCBUSY; /**< Synchronization Busy Register  */
+} RTC_TypeDef;             /**< RTC Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_RTC_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for RTC CTRL */
+#define _RTC_CTRL_RESETVALUE             0x00000000UL                      /**< Default value for RTC_CTRL */
+#define _RTC_CTRL_MASK                   0x00000007UL                      /**< Mask for RTC_CTRL */
+#define RTC_CTRL_EN                      (0x1UL << 0)                      /**< RTC Enable */
+#define _RTC_CTRL_EN_SHIFT               0                                 /**< Shift value for RTC_EN */
+#define _RTC_CTRL_EN_MASK                0x1UL                             /**< Bit mask for RTC_EN */
+#define _RTC_CTRL_EN_DEFAULT             0x00000000UL                      /**< Mode DEFAULT for RTC_CTRL */
+#define RTC_CTRL_EN_DEFAULT              (_RTC_CTRL_EN_DEFAULT << 0)       /**< Shifted mode DEFAULT for RTC_CTRL */
+#define RTC_CTRL_DEBUGRUN                (0x1UL << 1)                      /**< Debug Mode Run Enable */
+#define _RTC_CTRL_DEBUGRUN_SHIFT         1                                 /**< Shift value for RTC_DEBUGRUN */
+#define _RTC_CTRL_DEBUGRUN_MASK          0x2UL                             /**< Bit mask for RTC_DEBUGRUN */
+#define _RTC_CTRL_DEBUGRUN_DEFAULT       0x00000000UL                      /**< Mode DEFAULT for RTC_CTRL */
+#define RTC_CTRL_DEBUGRUN_DEFAULT        (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */
+#define RTC_CTRL_COMP0TOP                (0x1UL << 2)                      /**< Compare Channel 0 is Top Value */
+#define _RTC_CTRL_COMP0TOP_SHIFT         2                                 /**< Shift value for RTC_COMP0TOP */
+#define _RTC_CTRL_COMP0TOP_MASK          0x4UL                             /**< Bit mask for RTC_COMP0TOP */
+#define _RTC_CTRL_COMP0TOP_DEFAULT       0x00000000UL                      /**< Mode DEFAULT for RTC_CTRL */
+#define _RTC_CTRL_COMP0TOP_DISABLE       0x00000000UL                      /**< Mode DISABLE for RTC_CTRL */
+#define _RTC_CTRL_COMP0TOP_ENABLE        0x00000001UL                      /**< Mode ENABLE for RTC_CTRL */
+#define RTC_CTRL_COMP0TOP_DEFAULT        (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */
+#define RTC_CTRL_COMP0TOP_DISABLE        (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */
+#define RTC_CTRL_COMP0TOP_ENABLE         (_RTC_CTRL_COMP0TOP_ENABLE << 2)  /**< Shifted mode ENABLE for RTC_CTRL */
+
+/* Bit fields for RTC CNT */
+#define _RTC_CNT_RESETVALUE              0x00000000UL                /**< Default value for RTC_CNT */
+#define _RTC_CNT_MASK                    0x00FFFFFFUL                /**< Mask for RTC_CNT */
+#define _RTC_CNT_CNT_SHIFT               0                           /**< Shift value for RTC_CNT */
+#define _RTC_CNT_CNT_MASK                0xFFFFFFUL                  /**< Bit mask for RTC_CNT */
+#define _RTC_CNT_CNT_DEFAULT             0x00000000UL                /**< Mode DEFAULT for RTC_CNT */
+#define RTC_CNT_CNT_DEFAULT              (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */
+
+/* Bit fields for RTC COMP0 */
+#define _RTC_COMP0_RESETVALUE            0x00000000UL                    /**< Default value for RTC_COMP0 */
+#define _RTC_COMP0_MASK                  0x00FFFFFFUL                    /**< Mask for RTC_COMP0 */
+#define _RTC_COMP0_COMP0_SHIFT           0                               /**< Shift value for RTC_COMP0 */
+#define _RTC_COMP0_COMP0_MASK            0xFFFFFFUL                      /**< Bit mask for RTC_COMP0 */
+#define _RTC_COMP0_COMP0_DEFAULT         0x00000000UL                    /**< Mode DEFAULT for RTC_COMP0 */
+#define RTC_COMP0_COMP0_DEFAULT          (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */
+
+/* Bit fields for RTC COMP1 */
+#define _RTC_COMP1_RESETVALUE            0x00000000UL                    /**< Default value for RTC_COMP1 */
+#define _RTC_COMP1_MASK                  0x00FFFFFFUL                    /**< Mask for RTC_COMP1 */
+#define _RTC_COMP1_COMP1_SHIFT           0                               /**< Shift value for RTC_COMP1 */
+#define _RTC_COMP1_COMP1_MASK            0xFFFFFFUL                      /**< Bit mask for RTC_COMP1 */
+#define _RTC_COMP1_COMP1_DEFAULT         0x00000000UL                    /**< Mode DEFAULT for RTC_COMP1 */
+#define RTC_COMP1_COMP1_DEFAULT          (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */
+
+/* Bit fields for RTC IF */
+#define _RTC_IF_RESETVALUE               0x00000000UL                 /**< Default value for RTC_IF */
+#define _RTC_IF_MASK                     0x00000007UL                 /**< Mask for RTC_IF */
+#define RTC_IF_OF                        (0x1UL << 0)                 /**< Overflow Interrupt Flag */
+#define _RTC_IF_OF_SHIFT                 0                            /**< Shift value for RTC_OF */
+#define _RTC_IF_OF_MASK                  0x1UL                        /**< Bit mask for RTC_OF */
+#define _RTC_IF_OF_DEFAULT               0x00000000UL                 /**< Mode DEFAULT for RTC_IF */
+#define RTC_IF_OF_DEFAULT                (_RTC_IF_OF_DEFAULT << 0)    /**< Shifted mode DEFAULT for RTC_IF */
+#define RTC_IF_COMP0                     (0x1UL << 1)                 /**< Compare Match 0 Interrupt Flag */
+#define _RTC_IF_COMP0_SHIFT              1                            /**< Shift value for RTC_COMP0 */
+#define _RTC_IF_COMP0_MASK               0x2UL                        /**< Bit mask for RTC_COMP0 */
+#define _RTC_IF_COMP0_DEFAULT            0x00000000UL                 /**< Mode DEFAULT for RTC_IF */
+#define RTC_IF_COMP0_DEFAULT             (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */
+#define RTC_IF_COMP1                     (0x1UL << 2)                 /**< Compare Match 1 Interrupt Flag */
+#define _RTC_IF_COMP1_SHIFT              2                            /**< Shift value for RTC_COMP1 */
+#define _RTC_IF_COMP1_MASK               0x4UL                        /**< Bit mask for RTC_COMP1 */
+#define _RTC_IF_COMP1_DEFAULT            0x00000000UL                 /**< Mode DEFAULT for RTC_IF */
+#define RTC_IF_COMP1_DEFAULT             (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */
+
+/* Bit fields for RTC IFS */
+#define _RTC_IFS_RESETVALUE              0x00000000UL                  /**< Default value for RTC_IFS */
+#define _RTC_IFS_MASK                    0x00000007UL                  /**< Mask for RTC_IFS */
+#define RTC_IFS_OF                       (0x1UL << 0)                  /**< Set Overflow Interrupt Flag */
+#define _RTC_IFS_OF_SHIFT                0                             /**< Shift value for RTC_OF */
+#define _RTC_IFS_OF_MASK                 0x1UL                         /**< Bit mask for RTC_OF */
+#define _RTC_IFS_OF_DEFAULT              0x00000000UL                  /**< Mode DEFAULT for RTC_IFS */
+#define RTC_IFS_OF_DEFAULT               (_RTC_IFS_OF_DEFAULT << 0)    /**< Shifted mode DEFAULT for RTC_IFS */
+#define RTC_IFS_COMP0                    (0x1UL << 1)                  /**< Set Compare match 0 Interrupt Flag */
+#define _RTC_IFS_COMP0_SHIFT             1                             /**< Shift value for RTC_COMP0 */
+#define _RTC_IFS_COMP0_MASK              0x2UL                         /**< Bit mask for RTC_COMP0 */
+#define _RTC_IFS_COMP0_DEFAULT           0x00000000UL                  /**< Mode DEFAULT for RTC_IFS */
+#define RTC_IFS_COMP0_DEFAULT            (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */
+#define RTC_IFS_COMP1                    (0x1UL << 2)                  /**< Set Compare match 1 Interrupt Flag */
+#define _RTC_IFS_COMP1_SHIFT             2                             /**< Shift value for RTC_COMP1 */
+#define _RTC_IFS_COMP1_MASK              0x4UL                         /**< Bit mask for RTC_COMP1 */
+#define _RTC_IFS_COMP1_DEFAULT           0x00000000UL                  /**< Mode DEFAULT for RTC_IFS */
+#define RTC_IFS_COMP1_DEFAULT            (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */
+
+/* Bit fields for RTC IFC */
+#define _RTC_IFC_RESETVALUE              0x00000000UL                  /**< Default value for RTC_IFC */
+#define _RTC_IFC_MASK                    0x00000007UL                  /**< Mask for RTC_IFC */
+#define RTC_IFC_OF                       (0x1UL << 0)                  /**< Clear Overflow Interrupt Flag */
+#define _RTC_IFC_OF_SHIFT                0                             /**< Shift value for RTC_OF */
+#define _RTC_IFC_OF_MASK                 0x1UL                         /**< Bit mask for RTC_OF */
+#define _RTC_IFC_OF_DEFAULT              0x00000000UL                  /**< Mode DEFAULT for RTC_IFC */
+#define RTC_IFC_OF_DEFAULT               (_RTC_IFC_OF_DEFAULT << 0)    /**< Shifted mode DEFAULT for RTC_IFC */
+#define RTC_IFC_COMP0                    (0x1UL << 1)                  /**< Clear Compare match 0 Interrupt Flag */
+#define _RTC_IFC_COMP0_SHIFT             1                             /**< Shift value for RTC_COMP0 */
+#define _RTC_IFC_COMP0_MASK              0x2UL                         /**< Bit mask for RTC_COMP0 */
+#define _RTC_IFC_COMP0_DEFAULT           0x00000000UL                  /**< Mode DEFAULT for RTC_IFC */
+#define RTC_IFC_COMP0_DEFAULT            (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */
+#define RTC_IFC_COMP1                    (0x1UL << 2)                  /**< Clear Compare match 1 Interrupt Flag */
+#define _RTC_IFC_COMP1_SHIFT             2                             /**< Shift value for RTC_COMP1 */
+#define _RTC_IFC_COMP1_MASK              0x4UL                         /**< Bit mask for RTC_COMP1 */
+#define _RTC_IFC_COMP1_DEFAULT           0x00000000UL                  /**< Mode DEFAULT for RTC_IFC */
+#define RTC_IFC_COMP1_DEFAULT            (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */
+
+/* Bit fields for RTC IEN */
+#define _RTC_IEN_RESETVALUE              0x00000000UL                  /**< Default value for RTC_IEN */
+#define _RTC_IEN_MASK                    0x00000007UL                  /**< Mask for RTC_IEN */
+#define RTC_IEN_OF                       (0x1UL << 0)                  /**< Overflow Interrupt Enable */
+#define _RTC_IEN_OF_SHIFT                0                             /**< Shift value for RTC_OF */
+#define _RTC_IEN_OF_MASK                 0x1UL                         /**< Bit mask for RTC_OF */
+#define _RTC_IEN_OF_DEFAULT              0x00000000UL                  /**< Mode DEFAULT for RTC_IEN */
+#define RTC_IEN_OF_DEFAULT               (_RTC_IEN_OF_DEFAULT << 0)    /**< Shifted mode DEFAULT for RTC_IEN */
+#define RTC_IEN_COMP0                    (0x1UL << 1)                  /**< Compare Match 0 Interrupt Enable */
+#define _RTC_IEN_COMP0_SHIFT             1                             /**< Shift value for RTC_COMP0 */
+#define _RTC_IEN_COMP0_MASK              0x2UL                         /**< Bit mask for RTC_COMP0 */
+#define _RTC_IEN_COMP0_DEFAULT           0x00000000UL                  /**< Mode DEFAULT for RTC_IEN */
+#define RTC_IEN_COMP0_DEFAULT            (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */
+#define RTC_IEN_COMP1                    (0x1UL << 2)                  /**< Compare Match 1 Interrupt Enable */
+#define _RTC_IEN_COMP1_SHIFT             2                             /**< Shift value for RTC_COMP1 */
+#define _RTC_IEN_COMP1_MASK              0x4UL                         /**< Bit mask for RTC_COMP1 */
+#define _RTC_IEN_COMP1_DEFAULT           0x00000000UL                  /**< Mode DEFAULT for RTC_IEN */
+#define RTC_IEN_COMP1_DEFAULT            (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */
+
+/* Bit fields for RTC FREEZE */
+#define _RTC_FREEZE_RESETVALUE           0x00000000UL                         /**< Default value for RTC_FREEZE */
+#define _RTC_FREEZE_MASK                 0x00000001UL                         /**< Mask for RTC_FREEZE */
+#define RTC_FREEZE_REGFREEZE             (0x1UL << 0)                         /**< Register Update Freeze */
+#define _RTC_FREEZE_REGFREEZE_SHIFT      0                                    /**< Shift value for RTC_REGFREEZE */
+#define _RTC_FREEZE_REGFREEZE_MASK       0x1UL                                /**< Bit mask for RTC_REGFREEZE */
+#define _RTC_FREEZE_REGFREEZE_DEFAULT    0x00000000UL                         /**< Mode DEFAULT for RTC_FREEZE */
+#define _RTC_FREEZE_REGFREEZE_UPDATE     0x00000000UL                         /**< Mode UPDATE for RTC_FREEZE */
+#define _RTC_FREEZE_REGFREEZE_FREEZE     0x00000001UL                         /**< Mode FREEZE for RTC_FREEZE */
+#define RTC_FREEZE_REGFREEZE_DEFAULT     (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */
+#define RTC_FREEZE_REGFREEZE_UPDATE      (_RTC_FREEZE_REGFREEZE_UPDATE << 0)  /**< Shifted mode UPDATE for RTC_FREEZE */
+#define RTC_FREEZE_REGFREEZE_FREEZE      (_RTC_FREEZE_REGFREEZE_FREEZE << 0)  /**< Shifted mode FREEZE for RTC_FREEZE */
+
+/* Bit fields for RTC SYNCBUSY */
+#define _RTC_SYNCBUSY_RESETVALUE         0x00000000UL                       /**< Default value for RTC_SYNCBUSY */
+#define _RTC_SYNCBUSY_MASK               0x00000007UL                       /**< Mask for RTC_SYNCBUSY */
+#define RTC_SYNCBUSY_CTRL                (0x1UL << 0)                       /**< CTRL Register Busy */
+#define _RTC_SYNCBUSY_CTRL_SHIFT         0                                  /**< Shift value for RTC_CTRL */
+#define _RTC_SYNCBUSY_CTRL_MASK          0x1UL                              /**< Bit mask for RTC_CTRL */
+#define _RTC_SYNCBUSY_CTRL_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for RTC_SYNCBUSY */
+#define RTC_SYNCBUSY_CTRL_DEFAULT        (_RTC_SYNCBUSY_CTRL_DEFAULT << 0)  /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
+#define RTC_SYNCBUSY_COMP0               (0x1UL << 1)                       /**< COMP0 Register Busy */
+#define _RTC_SYNCBUSY_COMP0_SHIFT        1                                  /**< Shift value for RTC_COMP0 */
+#define _RTC_SYNCBUSY_COMP0_MASK         0x2UL                              /**< Bit mask for RTC_COMP0 */
+#define _RTC_SYNCBUSY_COMP0_DEFAULT      0x00000000UL                       /**< Mode DEFAULT for RTC_SYNCBUSY */
+#define RTC_SYNCBUSY_COMP0_DEFAULT       (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
+#define RTC_SYNCBUSY_COMP1               (0x1UL << 2)                       /**< COMP1 Register Busy */
+#define _RTC_SYNCBUSY_COMP1_SHIFT        2                                  /**< Shift value for RTC_COMP1 */
+#define _RTC_SYNCBUSY_COMP1_MASK         0x4UL                              /**< Bit mask for RTC_COMP1 */
+#define _RTC_SYNCBUSY_COMP1_DEFAULT      0x00000000UL                       /**< Mode DEFAULT for RTC_SYNCBUSY */
+#define RTC_SYNCBUSY_COMP1_DEFAULT       (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
+
+/** @} End of group EFM32HG_RTC */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_timer.h

@@ -0,0 +1,967 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_TIMER register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_TIMER
+ * @{
+ * @brief EFM32HG_TIMER Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t   CTRL;          /**< Control Register  */
+  __IOM uint32_t   CMD;           /**< Command Register  */
+  __IM uint32_t    STATUS;        /**< Status Register  */
+  __IOM uint32_t   IEN;           /**< Interrupt Enable Register  */
+  __IM uint32_t    IF;            /**< Interrupt Flag Register  */
+  __IOM uint32_t   IFS;           /**< Interrupt Flag Set Register  */
+  __IOM uint32_t   IFC;           /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t   TOP;           /**< Counter Top Value Register  */
+  __IOM uint32_t   TOPB;          /**< Counter Top Value Buffer Register  */
+  __IOM uint32_t   CNT;           /**< Counter Value Register  */
+  __IOM uint32_t   ROUTE;         /**< I/O Routing Register  */
+
+  uint32_t         RESERVED0[1U]; /**< Reserved registers */
+  TIMER_CC_TypeDef CC[3U];        /**< Compare/Capture Channel */
+
+  uint32_t         RESERVED1[4U]; /**< Reserved for future use **/
+  __IOM uint32_t   DTCTRL;        /**< DTI Control Register  */
+  __IOM uint32_t   DTTIME;        /**< DTI Time Control Register  */
+  __IOM uint32_t   DTFC;          /**< DTI Fault Configuration Register  */
+  __IOM uint32_t   DTOGEN;        /**< DTI Output Generation Enable Register  */
+  __IM uint32_t    DTFAULT;       /**< DTI Fault Register  */
+  __OM uint32_t    DTFAULTC;      /**< DTI Fault Clear Register  */
+  __IOM uint32_t   DTLOCK;        /**< DTI Configuration Lock Register  */
+} TIMER_TypeDef;                  /**< TIMER Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_TIMER_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for TIMER CTRL */
+#define _TIMER_CTRL_RESETVALUE                     0x00000000UL                             /**< Default value for TIMER_CTRL */
+#define _TIMER_CTRL_MASK                           0x3F032FFBUL                             /**< Mask for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_SHIFT                     0                                        /**< Shift value for TIMER_MODE */
+#define _TIMER_CTRL_MODE_MASK                      0x3UL                                    /**< Bit mask for TIMER_MODE */
+#define _TIMER_CTRL_MODE_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_UP                        0x00000000UL                             /**< Mode UP for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_DOWN                      0x00000001UL                             /**< Mode DOWN for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_UPDOWN                    0x00000002UL                             /**< Mode UPDOWN for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_QDEC                      0x00000003UL                             /**< Mode QDEC for TIMER_CTRL */
+#define TIMER_CTRL_MODE_DEFAULT                    (_TIMER_CTRL_MODE_DEFAULT << 0)          /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_MODE_UP                         (_TIMER_CTRL_MODE_UP << 0)               /**< Shifted mode UP for TIMER_CTRL */
+#define TIMER_CTRL_MODE_DOWN                       (_TIMER_CTRL_MODE_DOWN << 0)             /**< Shifted mode DOWN for TIMER_CTRL */
+#define TIMER_CTRL_MODE_UPDOWN                     (_TIMER_CTRL_MODE_UPDOWN << 0)           /**< Shifted mode UPDOWN for TIMER_CTRL */
+#define TIMER_CTRL_MODE_QDEC                       (_TIMER_CTRL_MODE_QDEC << 0)             /**< Shifted mode QDEC for TIMER_CTRL */
+#define TIMER_CTRL_SYNC                            (0x1UL << 3)                             /**< Timer Start/Stop/Reload Synchronization */
+#define _TIMER_CTRL_SYNC_SHIFT                     3                                        /**< Shift value for TIMER_SYNC */
+#define _TIMER_CTRL_SYNC_MASK                      0x8UL                                    /**< Bit mask for TIMER_SYNC */
+#define _TIMER_CTRL_SYNC_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_SYNC_DEFAULT                    (_TIMER_CTRL_SYNC_DEFAULT << 3)          /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_OSMEN                           (0x1UL << 4)                             /**< One-shot Mode Enable */
+#define _TIMER_CTRL_OSMEN_SHIFT                    4                                        /**< Shift value for TIMER_OSMEN */
+#define _TIMER_CTRL_OSMEN_MASK                     0x10UL                                   /**< Bit mask for TIMER_OSMEN */
+#define _TIMER_CTRL_OSMEN_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_OSMEN_DEFAULT                   (_TIMER_CTRL_OSMEN_DEFAULT << 4)         /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_QDM                             (0x1UL << 5)                             /**< Quadrature Decoder Mode Selection */
+#define _TIMER_CTRL_QDM_SHIFT                      5                                        /**< Shift value for TIMER_QDM */
+#define _TIMER_CTRL_QDM_MASK                       0x20UL                                   /**< Bit mask for TIMER_QDM */
+#define _TIMER_CTRL_QDM_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_QDM_X2                         0x00000000UL                             /**< Mode X2 for TIMER_CTRL */
+#define _TIMER_CTRL_QDM_X4                         0x00000001UL                             /**< Mode X4 for TIMER_CTRL */
+#define TIMER_CTRL_QDM_DEFAULT                     (_TIMER_CTRL_QDM_DEFAULT << 5)           /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_QDM_X2                          (_TIMER_CTRL_QDM_X2 << 5)                /**< Shifted mode X2 for TIMER_CTRL */
+#define TIMER_CTRL_QDM_X4                          (_TIMER_CTRL_QDM_X4 << 5)                /**< Shifted mode X4 for TIMER_CTRL */
+#define TIMER_CTRL_DEBUGRUN                        (0x1UL << 6)                             /**< Debug Mode Run Enable */
+#define _TIMER_CTRL_DEBUGRUN_SHIFT                 6                                        /**< Shift value for TIMER_DEBUGRUN */
+#define _TIMER_CTRL_DEBUGRUN_MASK                  0x40UL                                   /**< Bit mask for TIMER_DEBUGRUN */
+#define _TIMER_CTRL_DEBUGRUN_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_DEBUGRUN_DEFAULT                (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6)      /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_DMACLRACT                       (0x1UL << 7)                             /**< DMA Request Clear on Active */
+#define _TIMER_CTRL_DMACLRACT_SHIFT                7                                        /**< Shift value for TIMER_DMACLRACT */
+#define _TIMER_CTRL_DMACLRACT_MASK                 0x80UL                                   /**< Bit mask for TIMER_DMACLRACT */
+#define _TIMER_CTRL_DMACLRACT_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_DMACLRACT_DEFAULT               (_TIMER_CTRL_DMACLRACT_DEFAULT << 7)     /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_SHIFT                    8                                        /**< Shift value for TIMER_RISEA */
+#define _TIMER_CTRL_RISEA_MASK                     0x300UL                                  /**< Bit mask for TIMER_RISEA */
+#define _TIMER_CTRL_RISEA_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_NONE                     0x00000000UL                             /**< Mode NONE for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_START                    0x00000001UL                             /**< Mode START for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_STOP                     0x00000002UL                             /**< Mode STOP for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_RELOADSTART              0x00000003UL                             /**< Mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_DEFAULT                   (_TIMER_CTRL_RISEA_DEFAULT << 8)         /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_NONE                      (_TIMER_CTRL_RISEA_NONE << 8)            /**< Shifted mode NONE for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_START                     (_TIMER_CTRL_RISEA_START << 8)           /**< Shifted mode START for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_STOP                      (_TIMER_CTRL_RISEA_STOP << 8)            /**< Shifted mode STOP for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_RELOADSTART               (_TIMER_CTRL_RISEA_RELOADSTART << 8)     /**< Shifted mode RELOADSTART for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_SHIFT                    10                                       /**< Shift value for TIMER_FALLA */
+#define _TIMER_CTRL_FALLA_MASK                     0xC00UL                                  /**< Bit mask for TIMER_FALLA */
+#define _TIMER_CTRL_FALLA_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_NONE                     0x00000000UL                             /**< Mode NONE for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_START                    0x00000001UL                             /**< Mode START for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_STOP                     0x00000002UL                             /**< Mode STOP for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_RELOADSTART              0x00000003UL                             /**< Mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_DEFAULT                   (_TIMER_CTRL_FALLA_DEFAULT << 10)        /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_NONE                      (_TIMER_CTRL_FALLA_NONE << 10)           /**< Shifted mode NONE for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_START                     (_TIMER_CTRL_FALLA_START << 10)          /**< Shifted mode START for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_STOP                      (_TIMER_CTRL_FALLA_STOP << 10)           /**< Shifted mode STOP for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_RELOADSTART               (_TIMER_CTRL_FALLA_RELOADSTART << 10)    /**< Shifted mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_X2CNT                           (0x1UL << 13)                            /**< 2x Count Mode */
+#define _TIMER_CTRL_X2CNT_SHIFT                    13                                       /**< Shift value for TIMER_X2CNT */
+#define _TIMER_CTRL_X2CNT_MASK                     0x2000UL                                 /**< Bit mask for TIMER_X2CNT */
+#define _TIMER_CTRL_X2CNT_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_X2CNT_DEFAULT                   (_TIMER_CTRL_X2CNT_DEFAULT << 13)        /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_SHIFT                   16                                       /**< Shift value for TIMER_CLKSEL */
+#define _TIMER_CTRL_CLKSEL_MASK                    0x30000UL                                /**< Bit mask for TIMER_CLKSEL */
+#define _TIMER_CTRL_CLKSEL_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK           0x00000000UL                             /**< Mode PRESCHFPERCLK for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_CC1                     0x00000001UL                             /**< Mode CC1 for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_TIMEROUF                0x00000002UL                             /**< Mode TIMEROUF for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_DEFAULT                  (_TIMER_CTRL_CLKSEL_DEFAULT << 16)       /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK            (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_CC1                      (_TIMER_CTRL_CLKSEL_CC1 << 16)           /**< Shifted mode CC1 for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_TIMEROUF                 (_TIMER_CTRL_CLKSEL_TIMEROUF << 16)      /**< Shifted mode TIMEROUF for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_SHIFT                    24                                       /**< Shift value for TIMER_PRESC */
+#define _TIMER_CTRL_PRESC_MASK                     0xF000000UL                              /**< Bit mask for TIMER_PRESC */
+#define _TIMER_CTRL_PRESC_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV1                     0x00000000UL                             /**< Mode DIV1 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV2                     0x00000001UL                             /**< Mode DIV2 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV4                     0x00000002UL                             /**< Mode DIV4 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV8                     0x00000003UL                             /**< Mode DIV8 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV16                    0x00000004UL                             /**< Mode DIV16 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV32                    0x00000005UL                             /**< Mode DIV32 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV64                    0x00000006UL                             /**< Mode DIV64 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV128                   0x00000007UL                             /**< Mode DIV128 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV256                   0x00000008UL                             /**< Mode DIV256 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV512                   0x00000009UL                             /**< Mode DIV512 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV1024                  0x0000000AUL                             /**< Mode DIV1024 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DEFAULT                   (_TIMER_CTRL_PRESC_DEFAULT << 24)        /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV1                      (_TIMER_CTRL_PRESC_DIV1 << 24)           /**< Shifted mode DIV1 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV2                      (_TIMER_CTRL_PRESC_DIV2 << 24)           /**< Shifted mode DIV2 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV4                      (_TIMER_CTRL_PRESC_DIV4 << 24)           /**< Shifted mode DIV4 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV8                      (_TIMER_CTRL_PRESC_DIV8 << 24)           /**< Shifted mode DIV8 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV16                     (_TIMER_CTRL_PRESC_DIV16 << 24)          /**< Shifted mode DIV16 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV32                     (_TIMER_CTRL_PRESC_DIV32 << 24)          /**< Shifted mode DIV32 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV64                     (_TIMER_CTRL_PRESC_DIV64 << 24)          /**< Shifted mode DIV64 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV128                    (_TIMER_CTRL_PRESC_DIV128 << 24)         /**< Shifted mode DIV128 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV256                    (_TIMER_CTRL_PRESC_DIV256 << 24)         /**< Shifted mode DIV256 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV512                    (_TIMER_CTRL_PRESC_DIV512 << 24)         /**< Shifted mode DIV512 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV1024                   (_TIMER_CTRL_PRESC_DIV1024 << 24)        /**< Shifted mode DIV1024 for TIMER_CTRL */
+#define TIMER_CTRL_ATI                             (0x1UL << 28)                            /**< Always Track Inputs */
+#define _TIMER_CTRL_ATI_SHIFT                      28                                       /**< Shift value for TIMER_ATI */
+#define _TIMER_CTRL_ATI_MASK                       0x10000000UL                             /**< Bit mask for TIMER_ATI */
+#define _TIMER_CTRL_ATI_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_ATI_DEFAULT                     (_TIMER_CTRL_ATI_DEFAULT << 28)          /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_RSSCOIST                        (0x1UL << 29)                            /**< Reload-Start Sets Compare Output initial State */
+#define _TIMER_CTRL_RSSCOIST_SHIFT                 29                                       /**< Shift value for TIMER_RSSCOIST */
+#define _TIMER_CTRL_RSSCOIST_MASK                  0x20000000UL                             /**< Bit mask for TIMER_RSSCOIST */
+#define _TIMER_CTRL_RSSCOIST_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_RSSCOIST_DEFAULT                (_TIMER_CTRL_RSSCOIST_DEFAULT << 29)     /**< Shifted mode DEFAULT for TIMER_CTRL */
+
+/* Bit fields for TIMER CMD */
+#define _TIMER_CMD_RESETVALUE                      0x00000000UL                    /**< Default value for TIMER_CMD */
+#define _TIMER_CMD_MASK                            0x00000003UL                    /**< Mask for TIMER_CMD */
+#define TIMER_CMD_START                            (0x1UL << 0)                    /**< Start Timer */
+#define _TIMER_CMD_START_SHIFT                     0                               /**< Shift value for TIMER_START */
+#define _TIMER_CMD_START_MASK                      0x1UL                           /**< Bit mask for TIMER_START */
+#define _TIMER_CMD_START_DEFAULT                   0x00000000UL                    /**< Mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_START_DEFAULT                    (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_STOP                             (0x1UL << 1)                    /**< Stop Timer */
+#define _TIMER_CMD_STOP_SHIFT                      1                               /**< Shift value for TIMER_STOP */
+#define _TIMER_CMD_STOP_MASK                       0x2UL                           /**< Bit mask for TIMER_STOP */
+#define _TIMER_CMD_STOP_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_STOP_DEFAULT                     (_TIMER_CMD_STOP_DEFAULT << 1)  /**< Shifted mode DEFAULT for TIMER_CMD */
+
+/* Bit fields for TIMER STATUS */
+#define _TIMER_STATUS_RESETVALUE                   0x00000000UL                          /**< Default value for TIMER_STATUS */
+#define _TIMER_STATUS_MASK                         0x07070707UL                          /**< Mask for TIMER_STATUS */
+#define TIMER_STATUS_RUNNING                       (0x1UL << 0)                          /**< Running */
+#define _TIMER_STATUS_RUNNING_SHIFT                0                                     /**< Shift value for TIMER_RUNNING */
+#define _TIMER_STATUS_RUNNING_MASK                 0x1UL                                 /**< Bit mask for TIMER_RUNNING */
+#define _TIMER_STATUS_RUNNING_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_RUNNING_DEFAULT               (_TIMER_STATUS_RUNNING_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_DIR                           (0x1UL << 1)                          /**< Direction */
+#define _TIMER_STATUS_DIR_SHIFT                    1                                     /**< Shift value for TIMER_DIR */
+#define _TIMER_STATUS_DIR_MASK                     0x2UL                                 /**< Bit mask for TIMER_DIR */
+#define _TIMER_STATUS_DIR_DEFAULT                  0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_DIR_UP                       0x00000000UL                          /**< Mode UP for TIMER_STATUS */
+#define _TIMER_STATUS_DIR_DOWN                     0x00000001UL                          /**< Mode DOWN for TIMER_STATUS */
+#define TIMER_STATUS_DIR_DEFAULT                   (_TIMER_STATUS_DIR_DEFAULT << 1)      /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_DIR_UP                        (_TIMER_STATUS_DIR_UP << 1)           /**< Shifted mode UP for TIMER_STATUS */
+#define TIMER_STATUS_DIR_DOWN                      (_TIMER_STATUS_DIR_DOWN << 1)         /**< Shifted mode DOWN for TIMER_STATUS */
+#define TIMER_STATUS_TOPBV                         (0x1UL << 2)                          /**< TOPB Valid */
+#define _TIMER_STATUS_TOPBV_SHIFT                  2                                     /**< Shift value for TIMER_TOPBV */
+#define _TIMER_STATUS_TOPBV_MASK                   0x4UL                                 /**< Bit mask for TIMER_TOPBV */
+#define _TIMER_STATUS_TOPBV_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_TOPBV_DEFAULT                 (_TIMER_STATUS_TOPBV_DEFAULT << 2)    /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV0                        (0x1UL << 8)                          /**< CC0 CCVB Valid */
+#define _TIMER_STATUS_CCVBV0_SHIFT                 8                                     /**< Shift value for TIMER_CCVBV0 */
+#define _TIMER_STATUS_CCVBV0_MASK                  0x100UL                               /**< Bit mask for TIMER_CCVBV0 */
+#define _TIMER_STATUS_CCVBV0_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV0_DEFAULT                (_TIMER_STATUS_CCVBV0_DEFAULT << 8)   /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV1                        (0x1UL << 9)                          /**< CC1 CCVB Valid */
+#define _TIMER_STATUS_CCVBV1_SHIFT                 9                                     /**< Shift value for TIMER_CCVBV1 */
+#define _TIMER_STATUS_CCVBV1_MASK                  0x200UL                               /**< Bit mask for TIMER_CCVBV1 */
+#define _TIMER_STATUS_CCVBV1_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV1_DEFAULT                (_TIMER_STATUS_CCVBV1_DEFAULT << 9)   /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV2                        (0x1UL << 10)                         /**< CC2 CCVB Valid */
+#define _TIMER_STATUS_CCVBV2_SHIFT                 10                                    /**< Shift value for TIMER_CCVBV2 */
+#define _TIMER_STATUS_CCVBV2_MASK                  0x400UL                               /**< Bit mask for TIMER_CCVBV2 */
+#define _TIMER_STATUS_CCVBV2_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV2_DEFAULT                (_TIMER_STATUS_CCVBV2_DEFAULT << 10)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV0                          (0x1UL << 16)                         /**< CC0 Input Capture Valid */
+#define _TIMER_STATUS_ICV0_SHIFT                   16                                    /**< Shift value for TIMER_ICV0 */
+#define _TIMER_STATUS_ICV0_MASK                    0x10000UL                             /**< Bit mask for TIMER_ICV0 */
+#define _TIMER_STATUS_ICV0_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV0_DEFAULT                  (_TIMER_STATUS_ICV0_DEFAULT << 16)    /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV1                          (0x1UL << 17)                         /**< CC1 Input Capture Valid */
+#define _TIMER_STATUS_ICV1_SHIFT                   17                                    /**< Shift value for TIMER_ICV1 */
+#define _TIMER_STATUS_ICV1_MASK                    0x20000UL                             /**< Bit mask for TIMER_ICV1 */
+#define _TIMER_STATUS_ICV1_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV1_DEFAULT                  (_TIMER_STATUS_ICV1_DEFAULT << 17)    /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV2                          (0x1UL << 18)                         /**< CC2 Input Capture Valid */
+#define _TIMER_STATUS_ICV2_SHIFT                   18                                    /**< Shift value for TIMER_ICV2 */
+#define _TIMER_STATUS_ICV2_MASK                    0x40000UL                             /**< Bit mask for TIMER_ICV2 */
+#define _TIMER_STATUS_ICV2_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV2_DEFAULT                  (_TIMER_STATUS_ICV2_DEFAULT << 18)    /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0                        (0x1UL << 24)                         /**< CC0 Polarity */
+#define _TIMER_STATUS_CCPOL0_SHIFT                 24                                    /**< Shift value for TIMER_CCPOL0 */
+#define _TIMER_STATUS_CCPOL0_MASK                  0x1000000UL                           /**< Bit mask for TIMER_CCPOL0 */
+#define _TIMER_STATUS_CCPOL0_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL0_LOWRISE               0x00000000UL                          /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL0_HIGHFALL              0x00000001UL                          /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_DEFAULT                (_TIMER_STATUS_CCPOL0_DEFAULT << 24)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_LOWRISE                (_TIMER_STATUS_CCPOL0_LOWRISE << 24)  /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_HIGHFALL               (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1                        (0x1UL << 25)                         /**< CC1 Polarity */
+#define _TIMER_STATUS_CCPOL1_SHIFT                 25                                    /**< Shift value for TIMER_CCPOL1 */
+#define _TIMER_STATUS_CCPOL1_MASK                  0x2000000UL                           /**< Bit mask for TIMER_CCPOL1 */
+#define _TIMER_STATUS_CCPOL1_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL1_LOWRISE               0x00000000UL                          /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL1_HIGHFALL              0x00000001UL                          /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_DEFAULT                (_TIMER_STATUS_CCPOL1_DEFAULT << 25)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_LOWRISE                (_TIMER_STATUS_CCPOL1_LOWRISE << 25)  /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_HIGHFALL               (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2                        (0x1UL << 26)                         /**< CC2 Polarity */
+#define _TIMER_STATUS_CCPOL2_SHIFT                 26                                    /**< Shift value for TIMER_CCPOL2 */
+#define _TIMER_STATUS_CCPOL2_MASK                  0x4000000UL                           /**< Bit mask for TIMER_CCPOL2 */
+#define _TIMER_STATUS_CCPOL2_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL2_LOWRISE               0x00000000UL                          /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL2_HIGHFALL              0x00000001UL                          /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_DEFAULT                (_TIMER_STATUS_CCPOL2_DEFAULT << 26)  /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_LOWRISE                (_TIMER_STATUS_CCPOL2_LOWRISE << 26)  /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_HIGHFALL               (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+
+/* Bit fields for TIMER IEN */
+#define _TIMER_IEN_RESETVALUE                      0x00000000UL                      /**< Default value for TIMER_IEN */
+#define _TIMER_IEN_MASK                            0x00000773UL                      /**< Mask for TIMER_IEN */
+#define TIMER_IEN_OF                               (0x1UL << 0)                      /**< Overflow Interrupt Enable */
+#define _TIMER_IEN_OF_SHIFT                        0                                 /**< Shift value for TIMER_OF */
+#define _TIMER_IEN_OF_MASK                         0x1UL                             /**< Bit mask for TIMER_OF */
+#define _TIMER_IEN_OF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_OF_DEFAULT                       (_TIMER_IEN_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_UF                               (0x1UL << 1)                      /**< Underflow Interrupt Enable */
+#define _TIMER_IEN_UF_SHIFT                        1                                 /**< Shift value for TIMER_UF */
+#define _TIMER_IEN_UF_MASK                         0x2UL                             /**< Bit mask for TIMER_UF */
+#define _TIMER_IEN_UF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_UF_DEFAULT                       (_TIMER_IEN_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC0                              (0x1UL << 4)                      /**< CC Channel 0 Interrupt Enable */
+#define _TIMER_IEN_CC0_SHIFT                       4                                 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IEN_CC0_MASK                        0x10UL                            /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IEN_CC0_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC0_DEFAULT                      (_TIMER_IEN_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC1                              (0x1UL << 5)                      /**< CC Channel 1 Interrupt Enable */
+#define _TIMER_IEN_CC1_SHIFT                       5                                 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IEN_CC1_MASK                        0x20UL                            /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IEN_CC1_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC1_DEFAULT                      (_TIMER_IEN_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC2                              (0x1UL << 6)                      /**< CC Channel 2 Interrupt Enable */
+#define _TIMER_IEN_CC2_SHIFT                       6                                 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IEN_CC2_MASK                        0x40UL                            /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IEN_CC2_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC2_DEFAULT                      (_TIMER_IEN_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF0                           (0x1UL << 8)                      /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Enable */
+#define _TIMER_IEN_ICBOF0_SHIFT                    8                                 /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IEN_ICBOF0_MASK                     0x100UL                           /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IEN_ICBOF0_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF0_DEFAULT                   (_TIMER_IEN_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF1                           (0x1UL << 9)                      /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Enable */
+#define _TIMER_IEN_ICBOF1_SHIFT                    9                                 /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IEN_ICBOF1_MASK                     0x200UL                           /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IEN_ICBOF1_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF1_DEFAULT                   (_TIMER_IEN_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF2                           (0x1UL << 10)                     /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Enable */
+#define _TIMER_IEN_ICBOF2_SHIFT                    10                                /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IEN_ICBOF2_MASK                     0x400UL                           /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IEN_ICBOF2_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF2_DEFAULT                   (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */
+
+/* Bit fields for TIMER IF */
+#define _TIMER_IF_RESETVALUE                       0x00000000UL                     /**< Default value for TIMER_IF */
+#define _TIMER_IF_MASK                             0x00000773UL                     /**< Mask for TIMER_IF */
+#define TIMER_IF_OF                                (0x1UL << 0)                     /**< Overflow Interrupt Flag */
+#define _TIMER_IF_OF_SHIFT                         0                                /**< Shift value for TIMER_OF */
+#define _TIMER_IF_OF_MASK                          0x1UL                            /**< Bit mask for TIMER_OF */
+#define _TIMER_IF_OF_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_OF_DEFAULT                        (_TIMER_IF_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_UF                                (0x1UL << 1)                     /**< Underflow Interrupt Flag */
+#define _TIMER_IF_UF_SHIFT                         1                                /**< Shift value for TIMER_UF */
+#define _TIMER_IF_UF_MASK                          0x2UL                            /**< Bit mask for TIMER_UF */
+#define _TIMER_IF_UF_DEFAULT                       0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_UF_DEFAULT                        (_TIMER_IF_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC0                               (0x1UL << 4)                     /**< CC Channel 0 Interrupt Flag */
+#define _TIMER_IF_CC0_SHIFT                        4                                /**< Shift value for TIMER_CC0 */
+#define _TIMER_IF_CC0_MASK                         0x10UL                           /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IF_CC0_DEFAULT                      0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC0_DEFAULT                       (_TIMER_IF_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC1                               (0x1UL << 5)                     /**< CC Channel 1 Interrupt Flag */
+#define _TIMER_IF_CC1_SHIFT                        5                                /**< Shift value for TIMER_CC1 */
+#define _TIMER_IF_CC1_MASK                         0x20UL                           /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IF_CC1_DEFAULT                      0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC1_DEFAULT                       (_TIMER_IF_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC2                               (0x1UL << 6)                     /**< CC Channel 2 Interrupt Flag */
+#define _TIMER_IF_CC2_SHIFT                        6                                /**< Shift value for TIMER_CC2 */
+#define _TIMER_IF_CC2_MASK                         0x40UL                           /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IF_CC2_DEFAULT                      0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC2_DEFAULT                       (_TIMER_IF_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF0                            (0x1UL << 8)                     /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF0_SHIFT                     8                                /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IF_ICBOF0_MASK                      0x100UL                          /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IF_ICBOF0_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF0_DEFAULT                    (_TIMER_IF_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF1                            (0x1UL << 9)                     /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF1_SHIFT                     9                                /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IF_ICBOF1_MASK                      0x200UL                          /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IF_ICBOF1_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF1_DEFAULT                    (_TIMER_IF_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF2                            (0x1UL << 10)                    /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF2_SHIFT                     10                               /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IF_ICBOF2_MASK                      0x400UL                          /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IF_ICBOF2_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF2_DEFAULT                    (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */
+
+/* Bit fields for TIMER IFS */
+#define _TIMER_IFS_RESETVALUE                      0x00000000UL                      /**< Default value for TIMER_IFS */
+#define _TIMER_IFS_MASK                            0x00000773UL                      /**< Mask for TIMER_IFS */
+#define TIMER_IFS_OF                               (0x1UL << 0)                      /**< Overflow Interrupt Flag Set */
+#define _TIMER_IFS_OF_SHIFT                        0                                 /**< Shift value for TIMER_OF */
+#define _TIMER_IFS_OF_MASK                         0x1UL                             /**< Bit mask for TIMER_OF */
+#define _TIMER_IFS_OF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_OF_DEFAULT                       (_TIMER_IFS_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_UF                               (0x1UL << 1)                      /**< Underflow Interrupt Flag Set */
+#define _TIMER_IFS_UF_SHIFT                        1                                 /**< Shift value for TIMER_UF */
+#define _TIMER_IFS_UF_MASK                         0x2UL                             /**< Bit mask for TIMER_UF */
+#define _TIMER_IFS_UF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_UF_DEFAULT                       (_TIMER_IFS_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC0                              (0x1UL << 4)                      /**< CC Channel 0 Interrupt Flag Set */
+#define _TIMER_IFS_CC0_SHIFT                       4                                 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IFS_CC0_MASK                        0x10UL                            /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IFS_CC0_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC0_DEFAULT                      (_TIMER_IFS_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC1                              (0x1UL << 5)                      /**< CC Channel 1 Interrupt Flag Set */
+#define _TIMER_IFS_CC1_SHIFT                       5                                 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IFS_CC1_MASK                        0x20UL                            /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IFS_CC1_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC1_DEFAULT                      (_TIMER_IFS_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC2                              (0x1UL << 6)                      /**< CC Channel 2 Interrupt Flag Set */
+#define _TIMER_IFS_CC2_SHIFT                       6                                 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IFS_CC2_MASK                        0x40UL                            /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IFS_CC2_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC2_DEFAULT                      (_TIMER_IFS_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF0                           (0x1UL << 8)                      /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set */
+#define _TIMER_IFS_ICBOF0_SHIFT                    8                                 /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IFS_ICBOF0_MASK                     0x100UL                           /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IFS_ICBOF0_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF0_DEFAULT                   (_TIMER_IFS_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF1                           (0x1UL << 9)                      /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set */
+#define _TIMER_IFS_ICBOF1_SHIFT                    9                                 /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IFS_ICBOF1_MASK                     0x200UL                           /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IFS_ICBOF1_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF1_DEFAULT                   (_TIMER_IFS_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF2                           (0x1UL << 10)                     /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set */
+#define _TIMER_IFS_ICBOF2_SHIFT                    10                                /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IFS_ICBOF2_MASK                     0x400UL                           /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IFS_ICBOF2_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF2_DEFAULT                   (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */
+
+/* Bit fields for TIMER IFC */
+#define _TIMER_IFC_RESETVALUE                      0x00000000UL                      /**< Default value for TIMER_IFC */
+#define _TIMER_IFC_MASK                            0x00000773UL                      /**< Mask for TIMER_IFC */
+#define TIMER_IFC_OF                               (0x1UL << 0)                      /**< Overflow Interrupt Flag Clear */
+#define _TIMER_IFC_OF_SHIFT                        0                                 /**< Shift value for TIMER_OF */
+#define _TIMER_IFC_OF_MASK                         0x1UL                             /**< Bit mask for TIMER_OF */
+#define _TIMER_IFC_OF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_OF_DEFAULT                       (_TIMER_IFC_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_UF                               (0x1UL << 1)                      /**< Underflow Interrupt Flag Clear */
+#define _TIMER_IFC_UF_SHIFT                        1                                 /**< Shift value for TIMER_UF */
+#define _TIMER_IFC_UF_MASK                         0x2UL                             /**< Bit mask for TIMER_UF */
+#define _TIMER_IFC_UF_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_UF_DEFAULT                       (_TIMER_IFC_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC0                              (0x1UL << 4)                      /**< CC Channel 0 Interrupt Flag Clear */
+#define _TIMER_IFC_CC0_SHIFT                       4                                 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IFC_CC0_MASK                        0x10UL                            /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IFC_CC0_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC0_DEFAULT                      (_TIMER_IFC_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC1                              (0x1UL << 5)                      /**< CC Channel 1 Interrupt Flag Clear */
+#define _TIMER_IFC_CC1_SHIFT                       5                                 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IFC_CC1_MASK                        0x20UL                            /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IFC_CC1_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC1_DEFAULT                      (_TIMER_IFC_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC2                              (0x1UL << 6)                      /**< CC Channel 2 Interrupt Flag Clear */
+#define _TIMER_IFC_CC2_SHIFT                       6                                 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IFC_CC2_MASK                        0x40UL                            /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IFC_CC2_DEFAULT                     0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC2_DEFAULT                      (_TIMER_IFC_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF0                           (0x1UL << 8)                      /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear */
+#define _TIMER_IFC_ICBOF0_SHIFT                    8                                 /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IFC_ICBOF0_MASK                     0x100UL                           /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IFC_ICBOF0_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF0_DEFAULT                   (_TIMER_IFC_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF1                           (0x1UL << 9)                      /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear */
+#define _TIMER_IFC_ICBOF1_SHIFT                    9                                 /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IFC_ICBOF1_MASK                     0x200UL                           /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IFC_ICBOF1_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF1_DEFAULT                   (_TIMER_IFC_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF2                           (0x1UL << 10)                     /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear */
+#define _TIMER_IFC_ICBOF2_SHIFT                    10                                /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IFC_ICBOF2_MASK                     0x400UL                           /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IFC_ICBOF2_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF2_DEFAULT                   (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */
+
+/* Bit fields for TIMER TOP */
+#define _TIMER_TOP_RESETVALUE                      0x0000FFFFUL                  /**< Default value for TIMER_TOP */
+#define _TIMER_TOP_MASK                            0x0000FFFFUL                  /**< Mask for TIMER_TOP */
+#define _TIMER_TOP_TOP_SHIFT                       0                             /**< Shift value for TIMER_TOP */
+#define _TIMER_TOP_TOP_MASK                        0xFFFFUL                      /**< Bit mask for TIMER_TOP */
+#define _TIMER_TOP_TOP_DEFAULT                     0x0000FFFFUL                  /**< Mode DEFAULT for TIMER_TOP */
+#define TIMER_TOP_TOP_DEFAULT                      (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */
+
+/* Bit fields for TIMER TOPB */
+#define _TIMER_TOPB_RESETVALUE                     0x00000000UL                    /**< Default value for TIMER_TOPB */
+#define _TIMER_TOPB_MASK                           0x0000FFFFUL                    /**< Mask for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_SHIFT                     0                               /**< Shift value for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_MASK                      0xFFFFUL                        /**< Bit mask for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_DEFAULT                   0x00000000UL                    /**< Mode DEFAULT for TIMER_TOPB */
+#define TIMER_TOPB_TOPB_DEFAULT                    (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */
+
+/* Bit fields for TIMER CNT */
+#define _TIMER_CNT_RESETVALUE                      0x00000000UL                  /**< Default value for TIMER_CNT */
+#define _TIMER_CNT_MASK                            0x0000FFFFUL                  /**< Mask for TIMER_CNT */
+#define _TIMER_CNT_CNT_SHIFT                       0                             /**< Shift value for TIMER_CNT */
+#define _TIMER_CNT_CNT_MASK                        0xFFFFUL                      /**< Bit mask for TIMER_CNT */
+#define _TIMER_CNT_CNT_DEFAULT                     0x00000000UL                  /**< Mode DEFAULT for TIMER_CNT */
+#define TIMER_CNT_CNT_DEFAULT                      (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */
+
+/* Bit fields for TIMER ROUTE */
+#define _TIMER_ROUTE_RESETVALUE                    0x00000000UL                          /**< Default value for TIMER_ROUTE */
+#define _TIMER_ROUTE_MASK                          0x00070707UL                          /**< Mask for TIMER_ROUTE */
+#define TIMER_ROUTE_CC0PEN                         (0x1UL << 0)                          /**< CC Channel 0 Pin Enable */
+#define _TIMER_ROUTE_CC0PEN_SHIFT                  0                                     /**< Shift value for TIMER_CC0PEN */
+#define _TIMER_ROUTE_CC0PEN_MASK                   0x1UL                                 /**< Bit mask for TIMER_CC0PEN */
+#define _TIMER_ROUTE_CC0PEN_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CC0PEN_DEFAULT                 (_TIMER_ROUTE_CC0PEN_DEFAULT << 0)    /**< Shifted mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CC1PEN                         (0x1UL << 1)                          /**< CC Channel 1 Pin Enable */
+#define _TIMER_ROUTE_CC1PEN_SHIFT                  1                                     /**< Shift value for TIMER_CC1PEN */
+#define _TIMER_ROUTE_CC1PEN_MASK                   0x2UL                                 /**< Bit mask for TIMER_CC1PEN */
+#define _TIMER_ROUTE_CC1PEN_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CC1PEN_DEFAULT                 (_TIMER_ROUTE_CC1PEN_DEFAULT << 1)    /**< Shifted mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CC2PEN                         (0x1UL << 2)                          /**< CC Channel 2 Pin Enable */
+#define _TIMER_ROUTE_CC2PEN_SHIFT                  2                                     /**< Shift value for TIMER_CC2PEN */
+#define _TIMER_ROUTE_CC2PEN_MASK                   0x4UL                                 /**< Bit mask for TIMER_CC2PEN */
+#define _TIMER_ROUTE_CC2PEN_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CC2PEN_DEFAULT                 (_TIMER_ROUTE_CC2PEN_DEFAULT << 2)    /**< Shifted mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CDTI0PEN                       (0x1UL << 8)                          /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
+#define _TIMER_ROUTE_CDTI0PEN_SHIFT                8                                     /**< Shift value for TIMER_CDTI0PEN */
+#define _TIMER_ROUTE_CDTI0PEN_MASK                 0x100UL                               /**< Bit mask for TIMER_CDTI0PEN */
+#define _TIMER_ROUTE_CDTI0PEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CDTI0PEN_DEFAULT               (_TIMER_ROUTE_CDTI0PEN_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CDTI1PEN                       (0x1UL << 9)                          /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
+#define _TIMER_ROUTE_CDTI1PEN_SHIFT                9                                     /**< Shift value for TIMER_CDTI1PEN */
+#define _TIMER_ROUTE_CDTI1PEN_MASK                 0x200UL                               /**< Bit mask for TIMER_CDTI1PEN */
+#define _TIMER_ROUTE_CDTI1PEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CDTI1PEN_DEFAULT               (_TIMER_ROUTE_CDTI1PEN_DEFAULT << 9)  /**< Shifted mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CDTI2PEN                       (0x1UL << 10)                         /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
+#define _TIMER_ROUTE_CDTI2PEN_SHIFT                10                                    /**< Shift value for TIMER_CDTI2PEN */
+#define _TIMER_ROUTE_CDTI2PEN_MASK                 0x400UL                               /**< Bit mask for TIMER_CDTI2PEN */
+#define _TIMER_ROUTE_CDTI2PEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_CDTI2PEN_DEFAULT               (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTE */
+#define _TIMER_ROUTE_LOCATION_SHIFT                16                                    /**< Shift value for TIMER_LOCATION */
+#define _TIMER_ROUTE_LOCATION_MASK                 0x70000UL                             /**< Bit mask for TIMER_LOCATION */
+#define _TIMER_ROUTE_LOCATION_LOC0                 0x00000000UL                          /**< Mode LOC0 for TIMER_ROUTE */
+#define _TIMER_ROUTE_LOCATION_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_ROUTE */
+#define _TIMER_ROUTE_LOCATION_LOC1                 0x00000001UL                          /**< Mode LOC1 for TIMER_ROUTE */
+#define _TIMER_ROUTE_LOCATION_LOC2                 0x00000002UL                          /**< Mode LOC2 for TIMER_ROUTE */
+#define _TIMER_ROUTE_LOCATION_LOC3                 0x00000003UL                          /**< Mode LOC3 for TIMER_ROUTE */
+#define _TIMER_ROUTE_LOCATION_LOC4                 0x00000004UL                          /**< Mode LOC4 for TIMER_ROUTE */
+#define _TIMER_ROUTE_LOCATION_LOC5                 0x00000005UL                          /**< Mode LOC5 for TIMER_ROUTE */
+#define _TIMER_ROUTE_LOCATION_LOC6                 0x00000006UL                          /**< Mode LOC6 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC0                  (_TIMER_ROUTE_LOCATION_LOC0 << 16)    /**< Shifted mode LOC0 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_DEFAULT               (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC1                  (_TIMER_ROUTE_LOCATION_LOC1 << 16)    /**< Shifted mode LOC1 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC2                  (_TIMER_ROUTE_LOCATION_LOC2 << 16)    /**< Shifted mode LOC2 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC3                  (_TIMER_ROUTE_LOCATION_LOC3 << 16)    /**< Shifted mode LOC3 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC4                  (_TIMER_ROUTE_LOCATION_LOC4 << 16)    /**< Shifted mode LOC4 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC5                  (_TIMER_ROUTE_LOCATION_LOC5 << 16)    /**< Shifted mode LOC5 for TIMER_ROUTE */
+#define TIMER_ROUTE_LOCATION_LOC6                  (_TIMER_ROUTE_LOCATION_LOC6 << 16)    /**< Shifted mode LOC6 for TIMER_ROUTE */
+
+/* Bit fields for TIMER CC_CTRL */
+#define _TIMER_CC_CTRL_RESETVALUE                  0x00000000UL                                    /**< Default value for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MASK                        0x1F373F17UL                                    /**< Mask for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_SHIFT                  0                                               /**< Shift value for TIMER_MODE */
+#define _TIMER_CC_CTRL_MODE_MASK                   0x3UL                                           /**< Bit mask for TIMER_MODE */
+#define _TIMER_CC_CTRL_MODE_DEFAULT                0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_OFF                    0x00000000UL                                    /**< Mode OFF for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE           0x00000001UL                                    /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE          0x00000002UL                                    /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_PWM                    0x00000003UL                                    /**< Mode PWM for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_DEFAULT                 (_TIMER_CC_CTRL_MODE_DEFAULT << 0)              /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_OFF                     (_TIMER_CC_CTRL_MODE_OFF << 0)                  /**< Shifted mode OFF for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_INPUTCAPTURE            (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0)         /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE           (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0)        /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_PWM                     (_TIMER_CC_CTRL_MODE_PWM << 0)                  /**< Shifted mode PWM for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_OUTINV                       (0x1UL << 2)                                    /**< Output Invert */
+#define _TIMER_CC_CTRL_OUTINV_SHIFT                2                                               /**< Shift value for TIMER_OUTINV */
+#define _TIMER_CC_CTRL_OUTINV_MASK                 0x4UL                                           /**< Bit mask for TIMER_OUTINV */
+#define _TIMER_CC_CTRL_OUTINV_DEFAULT              0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_OUTINV_DEFAULT               (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2)            /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COIST                        (0x1UL << 4)                                    /**< Compare Output Initial State */
+#define _TIMER_CC_CTRL_COIST_SHIFT                 4                                               /**< Shift value for TIMER_COIST */
+#define _TIMER_CC_CTRL_COIST_MASK                  0x10UL                                          /**< Bit mask for TIMER_COIST */
+#define _TIMER_CC_CTRL_COIST_DEFAULT               0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COIST_DEFAULT                (_TIMER_CC_CTRL_COIST_DEFAULT << 4)             /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_SHIFT                  8                                               /**< Shift value for TIMER_CMOA */
+#define _TIMER_CC_CTRL_CMOA_MASK                   0x300UL                                         /**< Bit mask for TIMER_CMOA */
+#define _TIMER_CC_CTRL_CMOA_DEFAULT                0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_NONE                   0x00000000UL                                    /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_TOGGLE                 0x00000001UL                                    /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_CLEAR                  0x00000002UL                                    /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_SET                    0x00000003UL                                    /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_DEFAULT                 (_TIMER_CC_CTRL_CMOA_DEFAULT << 8)              /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_NONE                    (_TIMER_CC_CTRL_CMOA_NONE << 8)                 /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_TOGGLE                  (_TIMER_CC_CTRL_CMOA_TOGGLE << 8)               /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_CLEAR                   (_TIMER_CC_CTRL_CMOA_CLEAR << 8)                /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_SET                     (_TIMER_CC_CTRL_CMOA_SET << 8)                  /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_SHIFT                 10                                              /**< Shift value for TIMER_COFOA */
+#define _TIMER_CC_CTRL_COFOA_MASK                  0xC00UL                                         /**< Bit mask for TIMER_COFOA */
+#define _TIMER_CC_CTRL_COFOA_DEFAULT               0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_NONE                  0x00000000UL                                    /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_TOGGLE                0x00000001UL                                    /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_CLEAR                 0x00000002UL                                    /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_SET                   0x00000003UL                                    /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_DEFAULT                (_TIMER_CC_CTRL_COFOA_DEFAULT << 10)            /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_NONE                   (_TIMER_CC_CTRL_COFOA_NONE << 10)               /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_TOGGLE                 (_TIMER_CC_CTRL_COFOA_TOGGLE << 10)             /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_CLEAR                  (_TIMER_CC_CTRL_COFOA_CLEAR << 10)              /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_SET                    (_TIMER_CC_CTRL_COFOA_SET << 10)                /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_SHIFT                 12                                              /**< Shift value for TIMER_CUFOA */
+#define _TIMER_CC_CTRL_CUFOA_MASK                  0x3000UL                                        /**< Bit mask for TIMER_CUFOA */
+#define _TIMER_CC_CTRL_CUFOA_DEFAULT               0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_NONE                  0x00000000UL                                    /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_TOGGLE                0x00000001UL                                    /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_CLEAR                 0x00000002UL                                    /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_SET                   0x00000003UL                                    /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_DEFAULT                (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12)            /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_NONE                   (_TIMER_CC_CTRL_CUFOA_NONE << 12)               /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_TOGGLE                 (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12)             /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_CLEAR                  (_TIMER_CC_CTRL_CUFOA_CLEAR << 12)              /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_SET                    (_TIMER_CC_CTRL_CUFOA_SET << 12)                /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_SHIFT                16                                              /**< Shift value for TIMER_PRSSEL */
+#define _TIMER_CC_CTRL_PRSSEL_MASK                 0x70000UL                                       /**< Bit mask for TIMER_PRSSEL */
+#define _TIMER_CC_CTRL_PRSSEL_DEFAULT              0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH0               0x00000000UL                                    /**< Mode PRSCH0 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH1               0x00000001UL                                    /**< Mode PRSCH1 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH2               0x00000002UL                                    /**< Mode PRSCH2 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH3               0x00000003UL                                    /**< Mode PRSCH3 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH4               0x00000004UL                                    /**< Mode PRSCH4 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH5               0x00000005UL                                    /**< Mode PRSCH5 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_DEFAULT               (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16)           /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH0                (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16)            /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH1                (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16)            /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH2                (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16)            /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH3                (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16)            /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH4                (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16)            /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH5                (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16)            /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL                        (0x1UL << 20)                                   /**< Input Selection */
+#define _TIMER_CC_CTRL_INSEL_SHIFT                 20                                              /**< Shift value for TIMER_INSEL */
+#define _TIMER_CC_CTRL_INSEL_MASK                  0x100000UL                                      /**< Bit mask for TIMER_INSEL */
+#define _TIMER_CC_CTRL_INSEL_DEFAULT               0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_INSEL_PIN                   0x00000000UL                                    /**< Mode PIN for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_INSEL_PRS                   0x00000001UL                                    /**< Mode PRS for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL_DEFAULT                (_TIMER_CC_CTRL_INSEL_DEFAULT << 20)            /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL_PIN                    (_TIMER_CC_CTRL_INSEL_PIN << 20)                /**< Shifted mode PIN for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL_PRS                    (_TIMER_CC_CTRL_INSEL_PRS << 20)                /**< Shifted mode PRS for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT                         (0x1UL << 21)                                   /**< Digital Filter */
+#define _TIMER_CC_CTRL_FILT_SHIFT                  21                                              /**< Shift value for TIMER_FILT */
+#define _TIMER_CC_CTRL_FILT_MASK                   0x200000UL                                      /**< Bit mask for TIMER_FILT */
+#define _TIMER_CC_CTRL_FILT_DEFAULT                0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_FILT_DISABLE                0x00000000UL                                    /**< Mode DISABLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_FILT_ENABLE                 0x00000001UL                                    /**< Mode ENABLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT_DEFAULT                 (_TIMER_CC_CTRL_FILT_DEFAULT << 21)             /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT_DISABLE                 (_TIMER_CC_CTRL_FILT_DISABLE << 21)             /**< Shifted mode DISABLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT_ENABLE                  (_TIMER_CC_CTRL_FILT_ENABLE << 21)              /**< Shifted mode ENABLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_SHIFT                24                                              /**< Shift value for TIMER_ICEDGE */
+#define _TIMER_CC_CTRL_ICEDGE_MASK                 0x3000000UL                                     /**< Bit mask for TIMER_ICEDGE */
+#define _TIMER_CC_CTRL_ICEDGE_DEFAULT              0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_RISING               0x00000000UL                                    /**< Mode RISING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_FALLING              0x00000001UL                                    /**< Mode FALLING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_BOTH                 0x00000002UL                                    /**< Mode BOTH for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_NONE                 0x00000003UL                                    /**< Mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_DEFAULT               (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24)           /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_RISING                (_TIMER_CC_CTRL_ICEDGE_RISING << 24)            /**< Shifted mode RISING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_FALLING               (_TIMER_CC_CTRL_ICEDGE_FALLING << 24)           /**< Shifted mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_BOTH                  (_TIMER_CC_CTRL_ICEDGE_BOTH << 24)              /**< Shifted mode BOTH for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_NONE                  (_TIMER_CC_CTRL_ICEDGE_NONE << 24)              /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT              26                                              /**< Shift value for TIMER_ICEVCTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_MASK               0xC000000UL                                     /**< Bit mask for TIMER_ICEVCTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT            0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE          0x00000000UL                                    /**< Mode EVERYEDGE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE    0x00000001UL                                    /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_RISING             0x00000002UL                                    /**< Mode RISING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_FALLING            0x00000003UL                                    /**< Mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT             (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26)         /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE           (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26)       /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE     (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_RISING              (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26)          /**< Shifted mode RISING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_FALLING             (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26)         /**< Shifted mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF                      (0x1UL << 28)                                   /**< PRS Configuration */
+#define _TIMER_CC_CTRL_PRSCONF_SHIFT               28                                              /**< Shift value for TIMER_PRSCONF */
+#define _TIMER_CC_CTRL_PRSCONF_MASK                0x10000000UL                                    /**< Bit mask for TIMER_PRSCONF */
+#define _TIMER_CC_CTRL_PRSCONF_DEFAULT             0x00000000UL                                    /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSCONF_PULSE               0x00000000UL                                    /**< Mode PULSE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSCONF_LEVEL               0x00000001UL                                    /**< Mode LEVEL for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF_DEFAULT              (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28)          /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF_PULSE                (_TIMER_CC_CTRL_PRSCONF_PULSE << 28)            /**< Shifted mode PULSE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF_LEVEL                (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28)            /**< Shifted mode LEVEL for TIMER_CC_CTRL */
+
+/* Bit fields for TIMER CC_CCV */
+#define _TIMER_CC_CCV_RESETVALUE                   0x00000000UL                     /**< Default value for TIMER_CC_CCV */
+#define _TIMER_CC_CCV_MASK                         0x0000FFFFUL                     /**< Mask for TIMER_CC_CCV */
+#define _TIMER_CC_CCV_CCV_SHIFT                    0                                /**< Shift value for TIMER_CCV */
+#define _TIMER_CC_CCV_CCV_MASK                     0xFFFFUL                         /**< Bit mask for TIMER_CCV */
+#define _TIMER_CC_CCV_CCV_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for TIMER_CC_CCV */
+#define TIMER_CC_CCV_CCV_DEFAULT                   (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */
+
+/* Bit fields for TIMER CC_CCVP */
+#define _TIMER_CC_CCVP_RESETVALUE                  0x00000000UL                       /**< Default value for TIMER_CC_CCVP */
+#define _TIMER_CC_CCVP_MASK                        0x0000FFFFUL                       /**< Mask for TIMER_CC_CCVP */
+#define _TIMER_CC_CCVP_CCVP_SHIFT                  0                                  /**< Shift value for TIMER_CCVP */
+#define _TIMER_CC_CCVP_CCVP_MASK                   0xFFFFUL                           /**< Bit mask for TIMER_CCVP */
+#define _TIMER_CC_CCVP_CCVP_DEFAULT                0x00000000UL                       /**< Mode DEFAULT for TIMER_CC_CCVP */
+#define TIMER_CC_CCVP_CCVP_DEFAULT                 (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */
+
+/* Bit fields for TIMER CC_CCVB */
+#define _TIMER_CC_CCVB_RESETVALUE                  0x00000000UL                       /**< Default value for TIMER_CC_CCVB */
+#define _TIMER_CC_CCVB_MASK                        0x0000FFFFUL                       /**< Mask for TIMER_CC_CCVB */
+#define _TIMER_CC_CCVB_CCVB_SHIFT                  0                                  /**< Shift value for TIMER_CCVB */
+#define _TIMER_CC_CCVB_CCVB_MASK                   0xFFFFUL                           /**< Bit mask for TIMER_CCVB */
+#define _TIMER_CC_CCVB_CCVB_DEFAULT                0x00000000UL                       /**< Mode DEFAULT for TIMER_CC_CCVB */
+#define TIMER_CC_CCVB_CCVB_DEFAULT                 (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */
+
+/* Bit fields for TIMER DTCTRL */
+#define _TIMER_DTCTRL_RESETVALUE                   0x00000000UL                          /**< Default value for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_MASK                         0x0100007FUL                          /**< Mask for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTEN                          (0x1UL << 0)                          /**< DTI Enable */
+#define _TIMER_DTCTRL_DTEN_SHIFT                   0                                     /**< Shift value for TIMER_DTEN */
+#define _TIMER_DTCTRL_DTEN_MASK                    0x1UL                                 /**< Bit mask for TIMER_DTEN */
+#define _TIMER_DTCTRL_DTEN_DEFAULT                 0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTEN_DEFAULT                  (_TIMER_DTCTRL_DTEN_DEFAULT << 0)     /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS                         (0x1UL << 1)                          /**< DTI Automatic Start-up Functionality */
+#define _TIMER_DTCTRL_DTDAS_SHIFT                  1                                     /**< Shift value for TIMER_DTDAS */
+#define _TIMER_DTCTRL_DTDAS_MASK                   0x2UL                                 /**< Bit mask for TIMER_DTDAS */
+#define _TIMER_DTCTRL_DTDAS_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTDAS_NORESTART              0x00000000UL                          /**< Mode NORESTART for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTDAS_RESTART                0x00000001UL                          /**< Mode RESTART for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS_DEFAULT                 (_TIMER_DTCTRL_DTDAS_DEFAULT << 1)    /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS_NORESTART               (_TIMER_DTCTRL_DTDAS_NORESTART << 1)  /**< Shifted mode NORESTART for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS_RESTART                 (_TIMER_DTCTRL_DTDAS_RESTART << 1)    /**< Shifted mode RESTART for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTIPOL                        (0x1UL << 2)                          /**< DTI Inactive Polarity */
+#define _TIMER_DTCTRL_DTIPOL_SHIFT                 2                                     /**< Shift value for TIMER_DTIPOL */
+#define _TIMER_DTCTRL_DTIPOL_MASK                  0x4UL                                 /**< Bit mask for TIMER_DTIPOL */
+#define _TIMER_DTCTRL_DTIPOL_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTIPOL_DEFAULT                (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2)   /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTCINV                        (0x1UL << 3)                          /**< DTI Complementary Output Invert. */
+#define _TIMER_DTCTRL_DTCINV_SHIFT                 3                                     /**< Shift value for TIMER_DTCINV */
+#define _TIMER_DTCTRL_DTCINV_MASK                  0x8UL                                 /**< Bit mask for TIMER_DTCINV */
+#define _TIMER_DTCTRL_DTCINV_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTCINV_DEFAULT                (_TIMER_DTCTRL_DTCINV_DEFAULT << 3)   /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_SHIFT               4                                     /**< Shift value for TIMER_DTPRSSEL */
+#define _TIMER_DTCTRL_DTPRSSEL_MASK                0x70UL                                /**< Bit mask for TIMER_DTPRSSEL */
+#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0              0x00000000UL                          /**< Mode PRSCH0 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1              0x00000001UL                          /**< Mode PRSCH1 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2              0x00000002UL                          /**< Mode PRSCH2 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3              0x00000003UL                          /**< Mode PRSCH3 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4              0x00000004UL                          /**< Mode PRSCH4 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5              0x00000005UL                          /**< Mode PRSCH5 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_DEFAULT              (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH0               (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4)  /**< Shifted mode PRSCH0 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH1               (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4)  /**< Shifted mode PRSCH1 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH2               (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4)  /**< Shifted mode PRSCH2 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH3               (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4)  /**< Shifted mode PRSCH3 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH4               (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4)  /**< Shifted mode PRSCH4 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH5               (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4)  /**< Shifted mode PRSCH5 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSEN                       (0x1UL << 24)                         /**< DTI PRS Source Enable */
+#define _TIMER_DTCTRL_DTPRSEN_SHIFT                24                                    /**< Shift value for TIMER_DTPRSEN */
+#define _TIMER_DTCTRL_DTPRSEN_MASK                 0x1000000UL                           /**< Bit mask for TIMER_DTPRSEN */
+#define _TIMER_DTCTRL_DTPRSEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSEN_DEFAULT               (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+
+/* Bit fields for TIMER DTTIME */
+#define _TIMER_DTTIME_RESETVALUE                   0x00000000UL                          /**< Default value for TIMER_DTTIME */
+#define _TIMER_DTTIME_MASK                         0x003F3F0FUL                          /**< Mask for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_SHIFT                0                                     /**< Shift value for TIMER_DTPRESC */
+#define _TIMER_DTTIME_DTPRESC_MASK                 0xFUL                                 /**< Bit mask for TIMER_DTPRESC */
+#define _TIMER_DTTIME_DTPRESC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV1                 0x00000000UL                          /**< Mode DIV1 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV2                 0x00000001UL                          /**< Mode DIV2 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV4                 0x00000002UL                          /**< Mode DIV4 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV8                 0x00000003UL                          /**< Mode DIV8 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV16                0x00000004UL                          /**< Mode DIV16 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV32                0x00000005UL                          /**< Mode DIV32 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV64                0x00000006UL                          /**< Mode DIV64 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV128               0x00000007UL                          /**< Mode DIV128 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV256               0x00000008UL                          /**< Mode DIV256 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV512               0x00000009UL                          /**< Mode DIV512 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV1024              0x0000000AUL                          /**< Mode DIV1024 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DEFAULT               (_TIMER_DTTIME_DTPRESC_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV1                  (_TIMER_DTTIME_DTPRESC_DIV1 << 0)     /**< Shifted mode DIV1 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV2                  (_TIMER_DTTIME_DTPRESC_DIV2 << 0)     /**< Shifted mode DIV2 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV4                  (_TIMER_DTTIME_DTPRESC_DIV4 << 0)     /**< Shifted mode DIV4 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV8                  (_TIMER_DTTIME_DTPRESC_DIV8 << 0)     /**< Shifted mode DIV8 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV16                 (_TIMER_DTTIME_DTPRESC_DIV16 << 0)    /**< Shifted mode DIV16 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV32                 (_TIMER_DTTIME_DTPRESC_DIV32 << 0)    /**< Shifted mode DIV32 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV64                 (_TIMER_DTTIME_DTPRESC_DIV64 << 0)    /**< Shifted mode DIV64 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV128                (_TIMER_DTTIME_DTPRESC_DIV128 << 0)   /**< Shifted mode DIV128 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV256                (_TIMER_DTTIME_DTPRESC_DIV256 << 0)   /**< Shifted mode DIV256 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV512                (_TIMER_DTTIME_DTPRESC_DIV512 << 0)   /**< Shifted mode DIV512 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV1024               (_TIMER_DTTIME_DTPRESC_DIV1024 << 0)  /**< Shifted mode DIV1024 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTRISET_SHIFT                8                                     /**< Shift value for TIMER_DTRISET */
+#define _TIMER_DTTIME_DTRISET_MASK                 0x3F00UL                              /**< Bit mask for TIMER_DTRISET */
+#define _TIMER_DTTIME_DTRISET_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_DTTIME */
+#define TIMER_DTTIME_DTRISET_DEFAULT               (_TIMER_DTTIME_DTRISET_DEFAULT << 8)  /**< Shifted mode DEFAULT for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTFALLT_SHIFT                16                                    /**< Shift value for TIMER_DTFALLT */
+#define _TIMER_DTTIME_DTFALLT_MASK                 0x3F0000UL                            /**< Bit mask for TIMER_DTFALLT */
+#define _TIMER_DTTIME_DTFALLT_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_DTTIME */
+#define TIMER_DTTIME_DTFALLT_DEFAULT               (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */
+
+/* Bit fields for TIMER DTFC */
+#define _TIMER_DTFC_RESETVALUE                     0x00000000UL                            /**< Default value for TIMER_DTFC */
+#define _TIMER_DTFC_MASK                           0x0F030707UL                            /**< Mask for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_SHIFT               0                                       /**< Shift value for TIMER_DTPRS0FSEL */
+#define _TIMER_DTFC_DTPRS0FSEL_MASK                0x7UL                                   /**< Bit mask for TIMER_DTPRS0FSEL */
+#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0              0x00000000UL                            /**< Mode PRSCH0 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1              0x00000001UL                            /**< Mode PRSCH1 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2              0x00000002UL                            /**< Mode PRSCH2 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3              0x00000003UL                            /**< Mode PRSCH3 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4              0x00000004UL                            /**< Mode PRSCH4 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5              0x00000005UL                            /**< Mode PRSCH5 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6              0x00000006UL                            /**< Mode PRSCH6 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7              0x00000007UL                            /**< Mode PRSCH7 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_DEFAULT              (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH0               (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0)    /**< Shifted mode PRSCH0 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH1               (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0)    /**< Shifted mode PRSCH1 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH2               (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0)    /**< Shifted mode PRSCH2 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH3               (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0)    /**< Shifted mode PRSCH3 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH4               (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0)    /**< Shifted mode PRSCH4 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH5               (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0)    /**< Shifted mode PRSCH5 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH6               (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0)    /**< Shifted mode PRSCH6 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH7               (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0)    /**< Shifted mode PRSCH7 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_SHIFT               8                                       /**< Shift value for TIMER_DTPRS1FSEL */
+#define _TIMER_DTFC_DTPRS1FSEL_MASK                0x700UL                                 /**< Bit mask for TIMER_DTPRS1FSEL */
+#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0              0x00000000UL                            /**< Mode PRSCH0 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1              0x00000001UL                            /**< Mode PRSCH1 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2              0x00000002UL                            /**< Mode PRSCH2 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3              0x00000003UL                            /**< Mode PRSCH3 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4              0x00000004UL                            /**< Mode PRSCH4 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5              0x00000005UL                            /**< Mode PRSCH5 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6              0x00000006UL                            /**< Mode PRSCH6 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7              0x00000007UL                            /**< Mode PRSCH7 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_DEFAULT              (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8)   /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH0               (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8)    /**< Shifted mode PRSCH0 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH1               (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8)    /**< Shifted mode PRSCH1 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH2               (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8)    /**< Shifted mode PRSCH2 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH3               (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8)    /**< Shifted mode PRSCH3 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH4               (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8)    /**< Shifted mode PRSCH4 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH5               (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8)    /**< Shifted mode PRSCH5 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH6               (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8)    /**< Shifted mode PRSCH6 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH7               (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8)    /**< Shifted mode PRSCH7 for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_SHIFT                     16                                      /**< Shift value for TIMER_DTFA */
+#define _TIMER_DTFC_DTFA_MASK                      0x30000UL                               /**< Bit mask for TIMER_DTFA */
+#define _TIMER_DTFC_DTFA_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_NONE                      0x00000000UL                            /**< Mode NONE for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_INACTIVE                  0x00000001UL                            /**< Mode INACTIVE for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_CLEAR                     0x00000002UL                            /**< Mode CLEAR for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_TRISTATE                  0x00000003UL                            /**< Mode TRISTATE for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_DEFAULT                    (_TIMER_DTFC_DTFA_DEFAULT << 16)        /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_NONE                       (_TIMER_DTFC_DTFA_NONE << 16)           /**< Shifted mode NONE for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_INACTIVE                   (_TIMER_DTFC_DTFA_INACTIVE << 16)       /**< Shifted mode INACTIVE for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_CLEAR                      (_TIMER_DTFC_DTFA_CLEAR << 16)          /**< Shifted mode CLEAR for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_TRISTATE                   (_TIMER_DTFC_DTFA_TRISTATE << 16)       /**< Shifted mode TRISTATE for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FEN                       (0x1UL << 24)                           /**< DTI PRS 0 Fault Enable */
+#define _TIMER_DTFC_DTPRS0FEN_SHIFT                24                                      /**< Shift value for TIMER_DTPRS0FEN */
+#define _TIMER_DTFC_DTPRS0FEN_MASK                 0x1000000UL                             /**< Bit mask for TIMER_DTPRS0FEN */
+#define _TIMER_DTFC_DTPRS0FEN_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FEN_DEFAULT               (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24)   /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FEN                       (0x1UL << 25)                           /**< DTI PRS 1 Fault Enable */
+#define _TIMER_DTFC_DTPRS1FEN_SHIFT                25                                      /**< Shift value for TIMER_DTPRS1FEN */
+#define _TIMER_DTFC_DTPRS1FEN_MASK                 0x2000000UL                             /**< Bit mask for TIMER_DTPRS1FEN */
+#define _TIMER_DTFC_DTPRS1FEN_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FEN_DEFAULT               (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25)   /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTDBGFEN                        (0x1UL << 26)                           /**< DTI Debugger Fault Enable */
+#define _TIMER_DTFC_DTDBGFEN_SHIFT                 26                                      /**< Shift value for TIMER_DTDBGFEN */
+#define _TIMER_DTFC_DTDBGFEN_MASK                  0x4000000UL                             /**< Bit mask for TIMER_DTDBGFEN */
+#define _TIMER_DTFC_DTDBGFEN_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTDBGFEN_DEFAULT                (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26)    /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTLOCKUPFEN                     (0x1UL << 27)                           /**< DTI Lockup Fault Enable */
+#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT              27                                      /**< Shift value for TIMER_DTLOCKUPFEN */
+#define _TIMER_DTFC_DTLOCKUPFEN_MASK               0x8000000UL                             /**< Bit mask for TIMER_DTLOCKUPFEN */
+#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT             (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */
+
+/* Bit fields for TIMER DTOGEN */
+#define _TIMER_DTOGEN_RESETVALUE                   0x00000000UL                             /**< Default value for TIMER_DTOGEN */
+#define _TIMER_DTOGEN_MASK                         0x0000003FUL                             /**< Mask for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC0EN                     (0x1UL << 0)                             /**< DTI CC0 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT              0                                        /**< Shift value for TIMER_DTOGCC0EN */
+#define _TIMER_DTOGEN_DTOGCC0EN_MASK               0x1UL                                    /**< Bit mask for TIMER_DTOGCC0EN */
+#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT             (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0)   /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC1EN                     (0x1UL << 1)                             /**< DTI CC1 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT              1                                        /**< Shift value for TIMER_DTOGCC1EN */
+#define _TIMER_DTOGEN_DTOGCC1EN_MASK               0x2UL                                    /**< Bit mask for TIMER_DTOGCC1EN */
+#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT             (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1)   /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC2EN                     (0x1UL << 2)                             /**< DTI CC2 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT              2                                        /**< Shift value for TIMER_DTOGCC2EN */
+#define _TIMER_DTOGEN_DTOGCC2EN_MASK               0x4UL                                    /**< Bit mask for TIMER_DTOGCC2EN */
+#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT             (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2)   /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI0EN                   (0x1UL << 3)                             /**< DTI CDTI0 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT            3                                        /**< Shift value for TIMER_DTOGCDTI0EN */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK             0x8UL                                    /**< Bit mask for TIMER_DTOGCDTI0EN */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT           (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI1EN                   (0x1UL << 4)                             /**< DTI CDTI1 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT            4                                        /**< Shift value for TIMER_DTOGCDTI1EN */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK             0x10UL                                   /**< Bit mask for TIMER_DTOGCDTI1EN */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT           (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI2EN                   (0x1UL << 5)                             /**< DTI CDTI2 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT            5                                        /**< Shift value for TIMER_DTOGCDTI2EN */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK             0x20UL                                   /**< Bit mask for TIMER_DTOGCDTI2EN */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT           (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+
+/* Bit fields for TIMER DTFAULT */
+#define _TIMER_DTFAULT_RESETVALUE                  0x00000000UL                            /**< Default value for TIMER_DTFAULT */
+#define _TIMER_DTFAULT_MASK                        0x0000000FUL                            /**< Mask for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS0F                      (0x1UL << 0)                            /**< DTI PRS 0 Fault */
+#define _TIMER_DTFAULT_DTPRS0F_SHIFT               0                                       /**< Shift value for TIMER_DTPRS0F */
+#define _TIMER_DTFAULT_DTPRS0F_MASK                0x1UL                                   /**< Bit mask for TIMER_DTPRS0F */
+#define _TIMER_DTFAULT_DTPRS0F_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS0F_DEFAULT              (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0)   /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS1F                      (0x1UL << 1)                            /**< DTI PRS 1 Fault */
+#define _TIMER_DTFAULT_DTPRS1F_SHIFT               1                                       /**< Shift value for TIMER_DTPRS1F */
+#define _TIMER_DTFAULT_DTPRS1F_MASK                0x2UL                                   /**< Bit mask for TIMER_DTPRS1F */
+#define _TIMER_DTFAULT_DTPRS1F_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS1F_DEFAULT              (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1)   /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTDBGF                       (0x1UL << 2)                            /**< DTI Debugger Fault */
+#define _TIMER_DTFAULT_DTDBGF_SHIFT                2                                       /**< Shift value for TIMER_DTDBGF */
+#define _TIMER_DTFAULT_DTDBGF_MASK                 0x4UL                                   /**< Bit mask for TIMER_DTDBGF */
+#define _TIMER_DTFAULT_DTDBGF_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTDBGF_DEFAULT               (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2)    /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTLOCKUPF                    (0x1UL << 3)                            /**< DTI Lockup Fault */
+#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT             3                                       /**< Shift value for TIMER_DTLOCKUPF */
+#define _TIMER_DTFAULT_DTLOCKUPF_MASK              0x8UL                                   /**< Bit mask for TIMER_DTLOCKUPF */
+#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT            (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+
+/* Bit fields for TIMER DTFAULTC */
+#define _TIMER_DTFAULTC_RESETVALUE                 0x00000000UL                             /**< Default value for TIMER_DTFAULTC */
+#define _TIMER_DTFAULTC_MASK                       0x0000000FUL                             /**< Mask for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS0FC                    (0x1UL << 0)                             /**< DTI PRS0 Fault Clear */
+#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT             0                                        /**< Shift value for TIMER_DTPRS0FC */
+#define _TIMER_DTFAULTC_DTPRS0FC_MASK              0x1UL                                    /**< Bit mask for TIMER_DTPRS0FC */
+#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT            (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS1FC                    (0x1UL << 1)                             /**< DTI PRS1 Fault Clear */
+#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT             1                                        /**< Shift value for TIMER_DTPRS1FC */
+#define _TIMER_DTFAULTC_DTPRS1FC_MASK              0x2UL                                    /**< Bit mask for TIMER_DTPRS1FC */
+#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT            (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1)  /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTDBGFC                     (0x1UL << 2)                             /**< DTI Debugger Fault Clear */
+#define _TIMER_DTFAULTC_DTDBGFC_SHIFT              2                                        /**< Shift value for TIMER_DTDBGFC */
+#define _TIMER_DTFAULTC_DTDBGFC_MASK               0x4UL                                    /**< Bit mask for TIMER_DTDBGFC */
+#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTDBGFC_DEFAULT             (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2)   /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_TLOCKUPFC                   (0x1UL << 3)                             /**< DTI Lockup Fault Clear */
+#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT            3                                        /**< Shift value for TIMER_TLOCKUPFC */
+#define _TIMER_DTFAULTC_TLOCKUPFC_MASK             0x8UL                                    /**< Bit mask for TIMER_TLOCKUPFC */
+#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT           (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+
+/* Bit fields for TIMER DTLOCK */
+#define _TIMER_DTLOCK_RESETVALUE                   0x00000000UL                          /**< Default value for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_MASK                         0x0000FFFFUL                          /**< Mask for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_SHIFT                0                                     /**< Shift value for TIMER_LOCKKEY */
+#define _TIMER_DTLOCK_LOCKKEY_MASK                 0xFFFFUL                              /**< Bit mask for TIMER_LOCKKEY */
+#define _TIMER_DTLOCK_LOCKKEY_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED             0x00000000UL                          /**< Mode UNLOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCK                 0x00000000UL                          /**< Mode LOCK for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCKED               0x00000001UL                          /**< Mode LOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_UNLOCK               0x0000CE80UL                          /**< Mode UNLOCK for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_DEFAULT               (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_UNLOCKED              (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCK                  (_TIMER_DTLOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCKED                (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_UNLOCK                (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for TIMER_DTLOCK */
+
+/** @} End of group EFM32HG_TIMER */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_timer_cc.h

@@ -0,0 +1,60 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_TIMER_CC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief TIMER_CC EFM32HG TIMER CC
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL; /**< CC Channel Control Register  */
+  __IOM uint32_t CCV;  /**< CC Channel Value Register  */
+  __IM uint32_t  CCVP; /**< CC Channel Value Peek Register  */
+  __IOM uint32_t CCVB; /**< CC Channel Buffer Register  */
+} TIMER_CC_TypeDef;
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_usb_diep.h

@@ -0,0 +1,64 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_USB_DIEP register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief USB_DIEP EFM32HG USB DIEP
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTL;           /**< Device IN Endpoint x+1 Control Register  */
+  uint32_t       RESERVED0[1U]; /**< Reserved for future use **/
+  __IOM uint32_t INT;           /**< Device IN Endpoint x+1 Interrupt Register  */
+  uint32_t       RESERVED1[1U]; /**< Reserved for future use **/
+  __IOM uint32_t TSIZ;          /**< Device IN Endpoint x+1 Transfer Size Register  */
+  __IOM uint32_t DMAADDR;       /**< Device IN Endpoint x+1 DMA Address Register  */
+  __IM uint32_t  TXFSTS;        /**< Device IN Endpoint x+1 Transmit FIFO Status Register  */
+  uint32_t       RESERVED2[1U]; /**< Reserved future */
+} USB_DIEP_TypeDef;
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_usb_doep.h

@@ -0,0 +1,63 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_USB_DOEP register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief USB_DOEP EFM32HG USB DOEP
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTL;           /**< Device OUT Endpoint x+1 Control Register  */
+  uint32_t       RESERVED0[1U]; /**< Reserved for future use **/
+  __IOM uint32_t INT;           /**< Device OUT Endpoint x+1 Interrupt Register  */
+  uint32_t       RESERVED1[1U]; /**< Reserved for future use **/
+  __IOM uint32_t TSIZ;          /**< Device OUT Endpoint x+1 Transfer Size Register  */
+  __IOM uint32_t DMAADDR;       /**< Device OUT Endpoint x+1 DMA Address Register  */
+  uint32_t       RESERVED2[2U]; /**< Reserved future */
+} USB_DOEP_TypeDef;
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_vcmp.h

@@ -0,0 +1,212 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_VCMP register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_VCMP
+ * @{
+ * @brief EFM32HG_VCMP Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;     /**< Control Register  */
+  __IOM uint32_t INPUTSEL; /**< Input Selection Register  */
+  __IM uint32_t  STATUS;   /**< Status Register  */
+  __IOM uint32_t IEN;      /**< Interrupt Enable Register  */
+  __IM uint32_t  IF;       /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;      /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;      /**< Interrupt Flag Clear Register  */
+} VCMP_TypeDef;            /**< VCMP Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_VCMP_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for VCMP CTRL */
+#define _VCMP_CTRL_RESETVALUE               0x47000000UL                         /**< Default value for VCMP_CTRL */
+#define _VCMP_CTRL_MASK                     0x4F030715UL                         /**< Mask for VCMP_CTRL */
+#define VCMP_CTRL_EN                        (0x1UL << 0)                         /**< Voltage Supply Comparator Enable */
+#define _VCMP_CTRL_EN_SHIFT                 0                                    /**< Shift value for VCMP_EN */
+#define _VCMP_CTRL_EN_MASK                  0x1UL                                /**< Bit mask for VCMP_EN */
+#define _VCMP_CTRL_EN_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_EN_DEFAULT                (_VCMP_CTRL_EN_DEFAULT << 0)         /**< Shifted mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_INACTVAL                  (0x1UL << 2)                         /**< Inactive Value */
+#define _VCMP_CTRL_INACTVAL_SHIFT           2                                    /**< Shift value for VCMP_INACTVAL */
+#define _VCMP_CTRL_INACTVAL_MASK            0x4UL                                /**< Bit mask for VCMP_INACTVAL */
+#define _VCMP_CTRL_INACTVAL_DEFAULT         0x00000000UL                         /**< Mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_INACTVAL_DEFAULT          (_VCMP_CTRL_INACTVAL_DEFAULT << 2)   /**< Shifted mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_HYSTEN                    (0x1UL << 4)                         /**< Hysteresis Enable */
+#define _VCMP_CTRL_HYSTEN_SHIFT             4                                    /**< Shift value for VCMP_HYSTEN */
+#define _VCMP_CTRL_HYSTEN_MASK              0x10UL                               /**< Bit mask for VCMP_HYSTEN */
+#define _VCMP_CTRL_HYSTEN_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_HYSTEN_DEFAULT            (_VCMP_CTRL_HYSTEN_DEFAULT << 4)     /**< Shifted mode DEFAULT for VCMP_CTRL */
+#define _VCMP_CTRL_WARMTIME_SHIFT           8                                    /**< Shift value for VCMP_WARMTIME */
+#define _VCMP_CTRL_WARMTIME_MASK            0x700UL                              /**< Bit mask for VCMP_WARMTIME */
+#define _VCMP_CTRL_WARMTIME_DEFAULT         0x00000000UL                         /**< Mode DEFAULT for VCMP_CTRL */
+#define _VCMP_CTRL_WARMTIME_4CYCLES         0x00000000UL                         /**< Mode 4CYCLES for VCMP_CTRL */
+#define _VCMP_CTRL_WARMTIME_8CYCLES         0x00000001UL                         /**< Mode 8CYCLES for VCMP_CTRL */
+#define _VCMP_CTRL_WARMTIME_16CYCLES        0x00000002UL                         /**< Mode 16CYCLES for VCMP_CTRL */
+#define _VCMP_CTRL_WARMTIME_32CYCLES        0x00000003UL                         /**< Mode 32CYCLES for VCMP_CTRL */
+#define _VCMP_CTRL_WARMTIME_64CYCLES        0x00000004UL                         /**< Mode 64CYCLES for VCMP_CTRL */
+#define _VCMP_CTRL_WARMTIME_128CYCLES       0x00000005UL                         /**< Mode 128CYCLES for VCMP_CTRL */
+#define _VCMP_CTRL_WARMTIME_256CYCLES       0x00000006UL                         /**< Mode 256CYCLES for VCMP_CTRL */
+#define _VCMP_CTRL_WARMTIME_512CYCLES       0x00000007UL                         /**< Mode 512CYCLES for VCMP_CTRL */
+#define VCMP_CTRL_WARMTIME_DEFAULT          (_VCMP_CTRL_WARMTIME_DEFAULT << 8)   /**< Shifted mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_WARMTIME_4CYCLES          (_VCMP_CTRL_WARMTIME_4CYCLES << 8)   /**< Shifted mode 4CYCLES for VCMP_CTRL */
+#define VCMP_CTRL_WARMTIME_8CYCLES          (_VCMP_CTRL_WARMTIME_8CYCLES << 8)   /**< Shifted mode 8CYCLES for VCMP_CTRL */
+#define VCMP_CTRL_WARMTIME_16CYCLES         (_VCMP_CTRL_WARMTIME_16CYCLES << 8)  /**< Shifted mode 16CYCLES for VCMP_CTRL */
+#define VCMP_CTRL_WARMTIME_32CYCLES         (_VCMP_CTRL_WARMTIME_32CYCLES << 8)  /**< Shifted mode 32CYCLES for VCMP_CTRL */
+#define VCMP_CTRL_WARMTIME_64CYCLES         (_VCMP_CTRL_WARMTIME_64CYCLES << 8)  /**< Shifted mode 64CYCLES for VCMP_CTRL */
+#define VCMP_CTRL_WARMTIME_128CYCLES        (_VCMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for VCMP_CTRL */
+#define VCMP_CTRL_WARMTIME_256CYCLES        (_VCMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for VCMP_CTRL */
+#define VCMP_CTRL_WARMTIME_512CYCLES        (_VCMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for VCMP_CTRL */
+#define VCMP_CTRL_IRISE                     (0x1UL << 16)                        /**< Rising Edge Interrupt Sense */
+#define _VCMP_CTRL_IRISE_SHIFT              16                                   /**< Shift value for VCMP_IRISE */
+#define _VCMP_CTRL_IRISE_MASK               0x10000UL                            /**< Bit mask for VCMP_IRISE */
+#define _VCMP_CTRL_IRISE_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_IRISE_DEFAULT             (_VCMP_CTRL_IRISE_DEFAULT << 16)     /**< Shifted mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_IFALL                     (0x1UL << 17)                        /**< Falling Edge Interrupt Sense */
+#define _VCMP_CTRL_IFALL_SHIFT              17                                   /**< Shift value for VCMP_IFALL */
+#define _VCMP_CTRL_IFALL_MASK               0x20000UL                            /**< Bit mask for VCMP_IFALL */
+#define _VCMP_CTRL_IFALL_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_IFALL_DEFAULT             (_VCMP_CTRL_IFALL_DEFAULT << 17)     /**< Shifted mode DEFAULT for VCMP_CTRL */
+#define _VCMP_CTRL_BIASPROG_SHIFT           24                                   /**< Shift value for VCMP_BIASPROG */
+#define _VCMP_CTRL_BIASPROG_MASK            0xF000000UL                          /**< Bit mask for VCMP_BIASPROG */
+#define _VCMP_CTRL_BIASPROG_DEFAULT         0x00000007UL                         /**< Mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_BIASPROG_DEFAULT          (_VCMP_CTRL_BIASPROG_DEFAULT << 24)  /**< Shifted mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_HALFBIAS                  (0x1UL << 30)                        /**< Half Bias Current */
+#define _VCMP_CTRL_HALFBIAS_SHIFT           30                                   /**< Shift value for VCMP_HALFBIAS */
+#define _VCMP_CTRL_HALFBIAS_MASK            0x40000000UL                         /**< Bit mask for VCMP_HALFBIAS */
+#define _VCMP_CTRL_HALFBIAS_DEFAULT         0x00000001UL                         /**< Mode DEFAULT for VCMP_CTRL */
+#define VCMP_CTRL_HALFBIAS_DEFAULT          (_VCMP_CTRL_HALFBIAS_DEFAULT << 30)  /**< Shifted mode DEFAULT for VCMP_CTRL */
+
+/* Bit fields for VCMP INPUTSEL */
+#define _VCMP_INPUTSEL_RESETVALUE           0x00000000UL                            /**< Default value for VCMP_INPUTSEL */
+#define _VCMP_INPUTSEL_MASK                 0x0000013FUL                            /**< Mask for VCMP_INPUTSEL */
+#define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT      0                                       /**< Shift value for VCMP_TRIGLEVEL */
+#define _VCMP_INPUTSEL_TRIGLEVEL_MASK       0x3FUL                                  /**< Bit mask for VCMP_TRIGLEVEL */
+#define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT    0x00000000UL                            /**< Mode DEFAULT for VCMP_INPUTSEL */
+#define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT     (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
+#define VCMP_INPUTSEL_LPREF                 (0x1UL << 8)                            /**< Low Power Reference */
+#define _VCMP_INPUTSEL_LPREF_SHIFT          8                                       /**< Shift value for VCMP_LPREF */
+#define _VCMP_INPUTSEL_LPREF_MASK           0x100UL                                 /**< Bit mask for VCMP_LPREF */
+#define _VCMP_INPUTSEL_LPREF_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for VCMP_INPUTSEL */
+#define VCMP_INPUTSEL_LPREF_DEFAULT         (_VCMP_INPUTSEL_LPREF_DEFAULT << 8)     /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
+
+/* Bit fields for VCMP STATUS */
+#define _VCMP_STATUS_RESETVALUE             0x00000000UL                        /**< Default value for VCMP_STATUS */
+#define _VCMP_STATUS_MASK                   0x00000003UL                        /**< Mask for VCMP_STATUS */
+#define VCMP_STATUS_VCMPACT                 (0x1UL << 0)                        /**< Voltage Supply Comparator Active */
+#define _VCMP_STATUS_VCMPACT_SHIFT          0                                   /**< Shift value for VCMP_VCMPACT */
+#define _VCMP_STATUS_VCMPACT_MASK           0x1UL                               /**< Bit mask for VCMP_VCMPACT */
+#define _VCMP_STATUS_VCMPACT_DEFAULT        0x00000000UL                        /**< Mode DEFAULT for VCMP_STATUS */
+#define VCMP_STATUS_VCMPACT_DEFAULT         (_VCMP_STATUS_VCMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_STATUS */
+#define VCMP_STATUS_VCMPOUT                 (0x1UL << 1)                        /**< Voltage Supply Comparator Output */
+#define _VCMP_STATUS_VCMPOUT_SHIFT          1                                   /**< Shift value for VCMP_VCMPOUT */
+#define _VCMP_STATUS_VCMPOUT_MASK           0x2UL                               /**< Bit mask for VCMP_VCMPOUT */
+#define _VCMP_STATUS_VCMPOUT_DEFAULT        0x00000000UL                        /**< Mode DEFAULT for VCMP_STATUS */
+#define VCMP_STATUS_VCMPOUT_DEFAULT         (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_STATUS */
+
+/* Bit fields for VCMP IEN */
+#define _VCMP_IEN_RESETVALUE                0x00000000UL                    /**< Default value for VCMP_IEN */
+#define _VCMP_IEN_MASK                      0x00000003UL                    /**< Mask for VCMP_IEN */
+#define VCMP_IEN_EDGE                       (0x1UL << 0)                    /**< Edge Trigger Interrupt Enable */
+#define _VCMP_IEN_EDGE_SHIFT                0                               /**< Shift value for VCMP_EDGE */
+#define _VCMP_IEN_EDGE_MASK                 0x1UL                           /**< Bit mask for VCMP_EDGE */
+#define _VCMP_IEN_EDGE_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for VCMP_IEN */
+#define VCMP_IEN_EDGE_DEFAULT               (_VCMP_IEN_EDGE_DEFAULT << 0)   /**< Shifted mode DEFAULT for VCMP_IEN */
+#define VCMP_IEN_WARMUP                     (0x1UL << 1)                    /**< Warm-up Interrupt Enable */
+#define _VCMP_IEN_WARMUP_SHIFT              1                               /**< Shift value for VCMP_WARMUP */
+#define _VCMP_IEN_WARMUP_MASK               0x2UL                           /**< Bit mask for VCMP_WARMUP */
+#define _VCMP_IEN_WARMUP_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for VCMP_IEN */
+#define VCMP_IEN_WARMUP_DEFAULT             (_VCMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IEN */
+
+/* Bit fields for VCMP IF */
+#define _VCMP_IF_RESETVALUE                 0x00000000UL                   /**< Default value for VCMP_IF */
+#define _VCMP_IF_MASK                       0x00000003UL                   /**< Mask for VCMP_IF */
+#define VCMP_IF_EDGE                        (0x1UL << 0)                   /**< Edge Triggered Interrupt Flag */
+#define _VCMP_IF_EDGE_SHIFT                 0                              /**< Shift value for VCMP_EDGE */
+#define _VCMP_IF_EDGE_MASK                  0x1UL                          /**< Bit mask for VCMP_EDGE */
+#define _VCMP_IF_EDGE_DEFAULT               0x00000000UL                   /**< Mode DEFAULT for VCMP_IF */
+#define VCMP_IF_EDGE_DEFAULT                (_VCMP_IF_EDGE_DEFAULT << 0)   /**< Shifted mode DEFAULT for VCMP_IF */
+#define VCMP_IF_WARMUP                      (0x1UL << 1)                   /**< Warm-up Interrupt Flag */
+#define _VCMP_IF_WARMUP_SHIFT               1                              /**< Shift value for VCMP_WARMUP */
+#define _VCMP_IF_WARMUP_MASK                0x2UL                          /**< Bit mask for VCMP_WARMUP */
+#define _VCMP_IF_WARMUP_DEFAULT             0x00000000UL                   /**< Mode DEFAULT for VCMP_IF */
+#define VCMP_IF_WARMUP_DEFAULT              (_VCMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IF */
+
+/* Bit fields for VCMP IFS */
+#define _VCMP_IFS_RESETVALUE                0x00000000UL                    /**< Default value for VCMP_IFS */
+#define _VCMP_IFS_MASK                      0x00000003UL                    /**< Mask for VCMP_IFS */
+#define VCMP_IFS_EDGE                       (0x1UL << 0)                    /**< Edge Triggered Interrupt Flag Set */
+#define _VCMP_IFS_EDGE_SHIFT                0                               /**< Shift value for VCMP_EDGE */
+#define _VCMP_IFS_EDGE_MASK                 0x1UL                           /**< Bit mask for VCMP_EDGE */
+#define _VCMP_IFS_EDGE_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for VCMP_IFS */
+#define VCMP_IFS_EDGE_DEFAULT               (_VCMP_IFS_EDGE_DEFAULT << 0)   /**< Shifted mode DEFAULT for VCMP_IFS */
+#define VCMP_IFS_WARMUP                     (0x1UL << 1)                    /**< Warm-up Interrupt Flag Set */
+#define _VCMP_IFS_WARMUP_SHIFT              1                               /**< Shift value for VCMP_WARMUP */
+#define _VCMP_IFS_WARMUP_MASK               0x2UL                           /**< Bit mask for VCMP_WARMUP */
+#define _VCMP_IFS_WARMUP_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for VCMP_IFS */
+#define VCMP_IFS_WARMUP_DEFAULT             (_VCMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFS */
+
+/* Bit fields for VCMP IFC */
+#define _VCMP_IFC_RESETVALUE                0x00000000UL                    /**< Default value for VCMP_IFC */
+#define _VCMP_IFC_MASK                      0x00000003UL                    /**< Mask for VCMP_IFC */
+#define VCMP_IFC_EDGE                       (0x1UL << 0)                    /**< Edge Triggered Interrupt Flag Clear */
+#define _VCMP_IFC_EDGE_SHIFT                0                               /**< Shift value for VCMP_EDGE */
+#define _VCMP_IFC_EDGE_MASK                 0x1UL                           /**< Bit mask for VCMP_EDGE */
+#define _VCMP_IFC_EDGE_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for VCMP_IFC */
+#define VCMP_IFC_EDGE_DEFAULT               (_VCMP_IFC_EDGE_DEFAULT << 0)   /**< Shifted mode DEFAULT for VCMP_IFC */
+#define VCMP_IFC_WARMUP                     (0x1UL << 1)                    /**< Warm-up Interrupt Flag Clear */
+#define _VCMP_IFC_WARMUP_SHIFT              1                               /**< Shift value for VCMP_WARMUP */
+#define _VCMP_IFC_WARMUP_MASK               0x2UL                           /**< Bit mask for VCMP_WARMUP */
+#define _VCMP_IFC_WARMUP_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for VCMP_IFC */
+#define VCMP_IFC_WARMUP_DEFAULT             (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
+
+/** @} End of group EFM32HG_VCMP */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/efm32hg_wdog.h

@@ -0,0 +1,148 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32HG_WDOG register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32HG_WDOG
+ * @{
+ * @brief EFM32HG_WDOG Register Declaration
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;     /**< Control Register  */
+  __IOM uint32_t CMD;      /**< Command Register  */
+
+  __IM uint32_t  SYNCBUSY; /**< Synchronization Busy Register  */
+} WDOG_TypeDef;            /**< WDOG Register Declaration *//** @} */
+
+/***************************************************************************//**
+ * @defgroup EFM32HG_WDOG_BitFields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for WDOG CTRL */
+#define _WDOG_CTRL_RESETVALUE            0x00000F00UL                         /**< Default value for WDOG_CTRL */
+#define _WDOG_CTRL_MASK                  0x00003F7FUL                         /**< Mask for WDOG_CTRL */
+#define WDOG_CTRL_EN                     (0x1UL << 0)                         /**< Watchdog Timer Enable */
+#define _WDOG_CTRL_EN_SHIFT              0                                    /**< Shift value for WDOG_EN */
+#define _WDOG_CTRL_EN_MASK               0x1UL                                /**< Bit mask for WDOG_EN */
+#define _WDOG_CTRL_EN_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EN_DEFAULT             (_WDOG_CTRL_EN_DEFAULT << 0)         /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_DEBUGRUN               (0x1UL << 1)                         /**< Debug Mode Run Enable */
+#define _WDOG_CTRL_DEBUGRUN_SHIFT        1                                    /**< Shift value for WDOG_DEBUGRUN */
+#define _WDOG_CTRL_DEBUGRUN_MASK         0x2UL                                /**< Bit mask for WDOG_DEBUGRUN */
+#define _WDOG_CTRL_DEBUGRUN_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_DEBUGRUN_DEFAULT       (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1)   /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM2RUN                 (0x1UL << 2)                         /**< Energy Mode 2 Run Enable */
+#define _WDOG_CTRL_EM2RUN_SHIFT          2                                    /**< Shift value for WDOG_EM2RUN */
+#define _WDOG_CTRL_EM2RUN_MASK           0x4UL                                /**< Bit mask for WDOG_EM2RUN */
+#define _WDOG_CTRL_EM2RUN_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM2RUN_DEFAULT         (_WDOG_CTRL_EM2RUN_DEFAULT << 2)     /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM3RUN                 (0x1UL << 3)                         /**< Energy Mode 3 Run Enable */
+#define _WDOG_CTRL_EM3RUN_SHIFT          3                                    /**< Shift value for WDOG_EM3RUN */
+#define _WDOG_CTRL_EM3RUN_MASK           0x8UL                                /**< Bit mask for WDOG_EM3RUN */
+#define _WDOG_CTRL_EM3RUN_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM3RUN_DEFAULT         (_WDOG_CTRL_EM3RUN_DEFAULT << 3)     /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_LOCK                   (0x1UL << 4)                         /**< Configuration lock */
+#define _WDOG_CTRL_LOCK_SHIFT            4                                    /**< Shift value for WDOG_LOCK */
+#define _WDOG_CTRL_LOCK_MASK             0x10UL                               /**< Bit mask for WDOG_LOCK */
+#define _WDOG_CTRL_LOCK_DEFAULT          0x00000000UL                         /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_LOCK_DEFAULT           (_WDOG_CTRL_LOCK_DEFAULT << 4)       /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM4BLOCK               (0x1UL << 5)                         /**< Energy Mode 4 Block */
+#define _WDOG_CTRL_EM4BLOCK_SHIFT        5                                    /**< Shift value for WDOG_EM4BLOCK */
+#define _WDOG_CTRL_EM4BLOCK_MASK         0x20UL                               /**< Bit mask for WDOG_EM4BLOCK */
+#define _WDOG_CTRL_EM4BLOCK_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM4BLOCK_DEFAULT       (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5)   /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_SWOSCBLOCK             (0x1UL << 6)                         /**< Software Oscillator Disable Block */
+#define _WDOG_CTRL_SWOSCBLOCK_SHIFT      6                                    /**< Shift value for WDOG_SWOSCBLOCK */
+#define _WDOG_CTRL_SWOSCBLOCK_MASK       0x40UL                               /**< Bit mask for WDOG_SWOSCBLOCK */
+#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT    0x00000000UL                         /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_SWOSCBLOCK_DEFAULT     (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_PERSEL_SHIFT          8                                    /**< Shift value for WDOG_PERSEL */
+#define _WDOG_CTRL_PERSEL_MASK           0xF00UL                              /**< Bit mask for WDOG_PERSEL */
+#define _WDOG_CTRL_PERSEL_DEFAULT        0x0000000FUL                         /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_PERSEL_DEFAULT         (_WDOG_CTRL_PERSEL_DEFAULT << 8)     /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_SHIFT          12                                   /**< Shift value for WDOG_CLKSEL */
+#define _WDOG_CTRL_CLKSEL_MASK           0x3000UL                             /**< Bit mask for WDOG_CLKSEL */
+#define _WDOG_CTRL_CLKSEL_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_ULFRCO         0x00000000UL                         /**< Mode ULFRCO for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_LFRCO          0x00000001UL                         /**< Mode LFRCO for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_LFXO           0x00000002UL                         /**< Mode LFXO for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_DEFAULT         (_WDOG_CTRL_CLKSEL_DEFAULT << 12)    /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_ULFRCO          (_WDOG_CTRL_CLKSEL_ULFRCO << 12)     /**< Shifted mode ULFRCO for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_LFRCO           (_WDOG_CTRL_CLKSEL_LFRCO << 12)      /**< Shifted mode LFRCO for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_LFXO            (_WDOG_CTRL_CLKSEL_LFXO << 12)       /**< Shifted mode LFXO for WDOG_CTRL */
+
+/* Bit fields for WDOG CMD */
+#define _WDOG_CMD_RESETVALUE             0x00000000UL                     /**< Default value for WDOG_CMD */
+#define _WDOG_CMD_MASK                   0x00000001UL                     /**< Mask for WDOG_CMD */
+#define WDOG_CMD_CLEAR                   (0x1UL << 0)                     /**< Watchdog Timer Clear */
+#define _WDOG_CMD_CLEAR_SHIFT            0                                /**< Shift value for WDOG_CLEAR */
+#define _WDOG_CMD_CLEAR_MASK             0x1UL                            /**< Bit mask for WDOG_CLEAR */
+#define _WDOG_CMD_CLEAR_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for WDOG_CMD */
+#define _WDOG_CMD_CLEAR_UNCHANGED        0x00000000UL                     /**< Mode UNCHANGED for WDOG_CMD */
+#define _WDOG_CMD_CLEAR_CLEARED          0x00000001UL                     /**< Mode CLEARED for WDOG_CMD */
+#define WDOG_CMD_CLEAR_DEFAULT           (_WDOG_CMD_CLEAR_DEFAULT << 0)   /**< Shifted mode DEFAULT for WDOG_CMD */
+#define WDOG_CMD_CLEAR_UNCHANGED         (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
+#define WDOG_CMD_CLEAR_CLEARED           (_WDOG_CMD_CLEAR_CLEARED << 0)   /**< Shifted mode CLEARED for WDOG_CMD */
+
+/* Bit fields for WDOG SYNCBUSY */
+#define _WDOG_SYNCBUSY_RESETVALUE        0x00000000UL                       /**< Default value for WDOG_SYNCBUSY */
+#define _WDOG_SYNCBUSY_MASK              0x00000003UL                       /**< Mask for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CTRL               (0x1UL << 0)                       /**< CTRL Register Busy */
+#define _WDOG_SYNCBUSY_CTRL_SHIFT        0                                  /**< Shift value for WDOG_CTRL */
+#define _WDOG_SYNCBUSY_CTRL_MASK         0x1UL                              /**< Bit mask for WDOG_CTRL */
+#define _WDOG_SYNCBUSY_CTRL_DEFAULT      0x00000000UL                       /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CTRL_DEFAULT       (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CMD                (0x1UL << 1)                       /**< CMD Register Busy */
+#define _WDOG_SYNCBUSY_CMD_SHIFT         1                                  /**< Shift value for WDOG_CMD */
+#define _WDOG_SYNCBUSY_CMD_MASK          0x2UL                              /**< Bit mask for WDOG_CMD */
+#define _WDOG_SYNCBUSY_CMD_DEFAULT       0x00000000UL                       /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CMD_DEFAULT        (_WDOG_SYNCBUSY_CMD_DEFAULT << 1)  /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+
+/** @} End of group EFM32HG_WDOG */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/em_device.h

@@ -0,0 +1,116 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
+ *        microcontroller devices
+ *
+ * This is a convenience header file for defining the part number on the
+ * build command line, instead of specifying the part specific header file.
+ *
+ * @verbatim
+ * Example: Add "-DEFM32G890F128" to your build options, to define part
+ *          Add "#include "em_device.h" to your source files
+ * @endverbatim
+ *
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifndef EM_DEVICE_H
+#define EM_DEVICE_H
+
+#if defined(EFM32HG108F32)
+#include "efm32hg108f32.h"
+
+#elif defined(EFM32HG108F64)
+#include "efm32hg108f64.h"
+
+#elif defined(EFM32HG110F32)
+#include "efm32hg110f32.h"
+
+#elif defined(EFM32HG110F64)
+#include "efm32hg110f64.h"
+
+#elif defined(EFM32HG210F32)
+#include "efm32hg210f32.h"
+
+#elif defined(EFM32HG210F64)
+#include "efm32hg210f64.h"
+
+#elif defined(EFM32HG222F32)
+#include "efm32hg222f32.h"
+
+#elif defined(EFM32HG222F64)
+#include "efm32hg222f64.h"
+
+#elif defined(EFM32HG308F32)
+#include "efm32hg308f32.h"
+
+#elif defined(EFM32HG308F64)
+#include "efm32hg308f64.h"
+
+#elif defined(EFM32HG309F32)
+#include "efm32hg309f32.h"
+
+#elif defined(EFM32HG309F64)
+#include "efm32hg309f64.h"
+
+#elif defined(EFM32HG310F32)
+#include "efm32hg310f32.h"
+
+#elif defined(EFM32HG310F64)
+#include "efm32hg310f64.h"
+
+#elif defined(EFM32HG321F32)
+#include "efm32hg321f32.h"
+
+#elif defined(EFM32HG321F64)
+#include "efm32hg321f64.h"
+
+#elif defined(EFM32HG322F32)
+#include "efm32hg322f32.h"
+
+#elif defined(EFM32HG322F64)
+#include "efm32hg322f64.h"
+
+#elif defined(EFM32HG350F32)
+#include "efm32hg350f32.h"
+
+#elif defined(EFM32HG350F64)
+#include "efm32hg350f64.h"
+
+#else
+#error "em_device.h: PART NUMBER undefined"
+#endif
+#endif /* EM_DEVICE_H */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32hg/include/vendor/system_efm32hg.h

@@ -0,0 +1,144 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M System Layer for EFM32 devices.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_EFM32HG_H
+#define SYSTEM_EFM32HG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFM32HG EFM32HG
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ ******************************   TYPEDEFS   ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+  void (*pFunc)(void);
+  void *topOfStack;
+} tVectorEntry;
+
+/*******************************************************************************
+ **************************   GLOBAL VARIABLES   *******************************
+ ******************************************************************************/
+
+extern uint32_t SystemCoreClock;    /**< System Clock Frequency (Core Clock) */
+
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__)    /* IAR requires the __vector_table symbol */
+#define __Vectors    __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
+
+/*******************************************************************************
+ *****************************   PROTOTYPES   **********************************
+ ******************************************************************************/
+
+/* Interrupt routines - prototypes */
+void Reset_Handler(void);           /**< Reset Handler */
+void NMI_Handler(void);             /**< NMI Handler */
+void HardFault_Handler(void);       /**< Hard Fault Handler */
+void SVC_Handler(void);             /**< SVCall Handler */
+void PendSV_Handler(void);          /**< PendSV Handler */
+void SysTick_Handler(void);         /**< SysTick Handler */
+
+void DMA_IRQHandler(void);          /**< DMA IRQ Handler */
+void GPIO_EVEN_IRQHandler(void);    /**< GPIO EVEN IRQ Handler */
+void TIMER0_IRQHandler(void);       /**< TIMER0 IRQ Handler */
+void ACMP0_IRQHandler(void);        /**< ACMP0 IRQ Handler */
+void ADC0_IRQHandler(void);         /**< ADC0 IRQ Handler */
+void I2C0_IRQHandler(void);         /**< I2C0 IRQ Handler */
+void GPIO_ODD_IRQHandler(void);     /**< GPIO ODD IRQ Handler */
+void TIMER1_IRQHandler(void);       /**< TIMER1 IRQ Handler */
+void USART1_RX_IRQHandler(void);    /**< USART1 RX IRQ Handler */
+void USART1_TX_IRQHandler(void);    /**< USART1 TX IRQ Handler */
+void LEUART0_IRQHandler(void);      /**< LEUART0 IRQ Handler */
+void PCNT0_IRQHandler(void);        /**< PCNT0 IRQ Handler */
+void RTC_IRQHandler(void);          /**< RTC IRQ Handler */
+void CMU_IRQHandler(void);          /**< CMU IRQ Handler */
+void VCMP_IRQHandler(void);         /**< VCMP IRQ Handler */
+void MSC_IRQHandler(void);          /**< MSC IRQ Handler */
+void AES_IRQHandler(void);          /**< AES IRQ Handler */
+void USART0_RX_IRQHandler(void);    /**< USART0 RX IRQ Handler */
+void USART0_TX_IRQHandler(void);    /**< USART0 TX IRQ Handler */
+void USB_IRQHandler(void);          /**< USB IRQ Handler */
+void TIMER2_IRQHandler(void);       /**< TIMER2 IRQ Handler */
+
+uint32_t SystemCoreClockGet(void);
+uint32_t SystemMaxCoreClockGet(void);
+
+/***************************************************************************//**
+ * @brief
+ *   Update CMSIS SystemCoreClock variable.
+ *
+ * @details
+ *   CMSIS defines a global variable SystemCoreClock that shall hold the
+ *   core frequency in Hz. If the core frequency is dynamically changed, the
+ *   variable must be kept updated in order to be CMSIS compliant.
+ *
+ *   Notice that if only changing core clock frequency through the EFM32 CMU
+ *   API, this variable will be kept updated. This function is only provided
+ *   for CMSIS compliance and if a user modifies the the core clock outside
+ *   the CMU API.
+ ******************************************************************************/
+static __INLINE void SystemCoreClockUpdate(void)
+{
+  (void)SystemCoreClockGet();
+}
+
+void SystemInit(void);
+uint32_t SystemHFClockGet(void);
+uint32_t SystemHFXOClockGet(void);
+void SystemHFXOClockSet(uint32_t freq);
+uint32_t SystemLFRCOClockGet(void);
+uint32_t SystemULFRCOClockGet(void);
+uint32_t SystemLFXOClockGet(void);
+void SystemLFXOClockSet(uint32_t freq);
+
+/** @} End of group EFM32HG */
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_EFM32HG_H */

cpu/efm32/families/efm32hg/system.c

@@ -0,0 +1,387 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M0+ System Layer for EFM32HG devices.
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+#include "em_device.h"
+
+/*******************************************************************************
+ ******************************   DEFINES   ************************************
+ ******************************************************************************/
+
+/** LFRCO frequency, tuned to below frequency during manufacturing. */
+#define EFM32_LFRCO_FREQ  (32768UL)
+/** ULFRCO frequency. */
+#define EFM32_ULFRCO_FREQ (1000UL)
+
+/*******************************************************************************
+ **************************   LOCAL VARIABLES   ********************************
+ ******************************************************************************/
+
+/* System oscillator frequencies. These frequencies are normally constant */
+/* for a target, but they are made configurable in order to allow run-time */
+/* handling of different boards. The crystal oscillator clocks can be set */
+/* compile time to a non-default value by defining respective EFM32_nFXO_FREQ */
+/* values according to board design. By defining the EFM32_nFXO_FREQ to 0, */
+/* one indicates that the oscillator is not present, in order to save some */
+/* SW footprint. */
+
+#ifndef EFM32_HFXO_FREQ
+/** HFXO frequency. */
+#define EFM32_HFXO_FREQ (24000000UL)
+#endif
+
+/** Maximum HFRCO frequency. */
+#define EFM32_HFRCO_MAX_FREQ (21000000UL)
+
+/* Do not define variable if HF crystal oscillator not present */
+#if (EFM32_HFXO_FREQ > 0U)
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/** System HFXO clock. */
+static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
+/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
+#endif
+
+#ifndef EFM32_LFXO_FREQ
+/** LFXO frequency. */
+#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
+#endif
+
+/* Do not define variable if LF crystal oscillator not present */
+#if (EFM32_LFXO_FREQ > 0U)
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/** System LFXO clock. */
+static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
+/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
+#endif
+
+/*******************************************************************************
+ **************************   GLOBAL VARIABLES   *******************************
+ ******************************************************************************/
+
+/**
+ * @brief
+ *   System System Clock Frequency (Core Clock).
+ *
+ * @details
+ *   Required CMSIS global variable that must be kept up-to-date.
+ */
+uint32_t SystemCoreClock = 14000000UL;
+
+/*******************************************************************************
+ **************************   GLOBAL FUNCTIONS   *******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ *   Get the current core clock frequency.
+ *
+ * @details
+ *   Calculate and get the current core clock frequency based on the current
+ *   configuration. Assuming that the SystemCoreClock global variable is
+ *   maintained, the core clock frequency is stored in that variable as well.
+ *   This function will however calculate the core clock based on actual HW
+ *   configuration. It will also update the SystemCoreClock global variable.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   The current core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemCoreClockGet(void)
+{
+  uint32_t ret;
+
+  ret = SystemHFClockGet();
+  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
+          >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
+
+  /* Keep CMSIS variable up-to-date just in case */
+  SystemCoreClock = ret;
+
+  return ret;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get the maximum core clock frequency.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   The maximum core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemMaxCoreClockGet(void)
+{
+#if (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ)
+  return EFM32_HFRCO_MAX_FREQ;
+#else
+  return EFM32_HFXO_FREQ;
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get the current HFCLK frequency.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   The current HFCLK frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemHFClockGet(void)
+{
+  uint32_t ret;
+
+  switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL
+                         | CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL
+#if defined(CMU_STATUS_USHFRCODIV2SEL)
+                         | CMU_STATUS_USHFRCODIV2SEL
+#endif
+                         )) {
+    case CMU_STATUS_LFXOSEL:
+#if (EFM32_LFXO_FREQ > 0U)
+      ret = SystemLFXOClock;
+#else
+      /* We should not get here, since core should not be clocked. May */
+      /* be caused by a misconfiguration though. */
+      ret = 0U;
+#endif
+      break;
+
+    case CMU_STATUS_LFRCOSEL:
+      ret = EFM32_LFRCO_FREQ;
+      break;
+
+    case CMU_STATUS_HFXOSEL:
+#if (EFM32_HFXO_FREQ > 0U)
+      ret = SystemHFXOClock;
+#else
+      /* We should not get here, since core should not be clocked. May */
+      /* be caused by a misconfiguration though. */
+      ret = 0U;
+#endif
+      break;
+
+#if defined(CMU_STATUS_USHFRCODIV2SEL)
+    case CMU_STATUS_USHFRCODIV2SEL:
+      ret = 24000000U;
+      break;
+#endif
+
+    default: /* CMU_STATUS_HFRCOSEL */
+      switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) {
+        case CMU_HFRCOCTRL_BAND_21MHZ:
+          ret = 21000000U;
+          break;
+
+        case CMU_HFRCOCTRL_BAND_14MHZ:
+          ret = 14000000U;
+          break;
+
+        case CMU_HFRCOCTRL_BAND_11MHZ:
+          ret = 11000000U;
+          break;
+
+        case CMU_HFRCOCTRL_BAND_7MHZ:
+          ret = 6600000U;
+          break;
+
+        case CMU_HFRCOCTRL_BAND_1MHZ:
+          ret = 1200000U;
+          break;
+
+        default:
+          ret = 0U;
+          break;
+      }
+      break;
+  }
+
+  return ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
+                      >> _CMU_CTRL_HFCLKDIV_SHIFT));
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get high frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   HFXO frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemHFXOClockGet(void)
+{
+  /* External crystal oscillator present? */
+#if (EFM32_HFXO_FREQ > 0U)
+  return SystemHFXOClock;
+#else
+  return 0U;
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set high frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ *   This function is mainly provided for being able to handle target systems
+ *   with different HF crystal oscillator frequencies run-time. If used, it
+ *   should probably only be used once during system startup.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @param[in] freq
+ *   HFXO frequency in Hz used for target.
+ ******************************************************************************/
+void SystemHFXOClockSet(uint32_t freq)
+{
+  /* External crystal oscillator present? */
+#if (EFM32_HFXO_FREQ > 0U)
+  SystemHFXOClock = freq;
+
+  /* Update core clock frequency if HFXO is used to clock core */
+  if ((CMU->STATUS & CMU_STATUS_HFXOSEL) != 0U) {
+    /* The function will update the global variable */
+    (void)SystemCoreClockGet();
+  }
+#else
+  (void)freq; /* Unused parameter */
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Initialize the system.
+ *
+ * @details
+ *   Do required generic HW system init.
+ *
+ * @note
+ *   This function is invoked during system init, before the main() routine
+ *   and any data has been initialized. For this reason, it cannot do any
+ *   initialization of variables etc.
+ ******************************************************************************/
+void SystemInit(void)
+{
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t)&__Vectors;
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get low frequency RC oscillator clock frequency for target system.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   LFRCO frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemLFRCOClockGet(void)
+{
+  /* Currently we assume that this frequency is properly tuned during */
+  /* manufacturing and is not changed after reset. If future requirements */
+  /* for re-tuning by user, we can add support for that. */
+  return EFM32_LFRCO_FREQ;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get ultra low frequency RC oscillator clock frequency for target system.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   ULFRCO frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemULFRCOClockGet(void)
+{
+  /* The ULFRCO frequency is not tuned, and can be very inaccurate */
+  return EFM32_ULFRCO_FREQ;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Get low frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ *   LFXO frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemLFXOClockGet(void)
+{
+  /* External crystal oscillator present? */
+#if (EFM32_LFXO_FREQ > 0U)
+  return SystemLFXOClock;
+#else
+  return 0U;
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Set low frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ *   This function is mainly provided for being able to handle target systems
+ *   with different HF crystal oscillator frequencies run-time. If used, it
+ *   should probably only be used once during system startup.
+ *
+ * @note
+ *   This is an EFM32 proprietary function, not part of the CMSIS definition.
+ *
+ * @param[in] freq
+ *   LFXO frequency in Hz used for target.
+ ******************************************************************************/
+void SystemLFXOClockSet(uint32_t freq)
+{
+  /* External crystal oscillator present? */
+#if (EFM32_LFXO_FREQ > 0U)
+  SystemLFXOClock = freq;
+
+  /* Update core clock frequency if LFXO is used to clock core */
+  if ((CMU->STATUS & CMU_STATUS_LFXOSEL) != 0U) {
+    /* The function will update the global variable */
+    (void)SystemCoreClockGet();
+  }
+#else
+  (void)freq; /* Unused parameter */
+#endif
+}

cpu/efm32/families/efm32hg/vectors.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2015-2018 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_efm32hg
+ * @{
+ *
+ * @file
+ * @brief       Startup code and interrupt vector definition
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author      Bas Stottelaar <basstottelaar@gmail.com>
+ *
+ * @}
+ */
+
+#include "vectors_cortexm.h"
+
+/* define a local dummy handler as it needs to be in the same compilation unit
+ * as the alias definition */
+void dummy_handler(void)
+{
+    dummy_handler_default();
+}
+
+/* Silicon Labs specific interrupt vector */
+WEAK_DEFAULT void isr_dma(void);
+WEAK_DEFAULT void isr_gpio_even(void);
+WEAK_DEFAULT void isr_timer0(void);
+WEAK_DEFAULT void isr_acmp0(void);
+WEAK_DEFAULT void isr_adc0(void);
+WEAK_DEFAULT void isr_i2c0(void);
+WEAK_DEFAULT void isr_gpio_odd(void);
+WEAK_DEFAULT void isr_timer1(void);
+WEAK_DEFAULT void isr_usart1_rx(void);
+WEAK_DEFAULT void isr_usart1_tx(void);
+WEAK_DEFAULT void isr_leuart0(void);
+WEAK_DEFAULT void isr_pcnt0(void);
+WEAK_DEFAULT void isr_rtc(void);
+WEAK_DEFAULT void isr_cmu(void);
+WEAK_DEFAULT void isr_vcmp(void);
+WEAK_DEFAULT void isr_msc(void);
+WEAK_DEFAULT void isr_aes(void);
+WEAK_DEFAULT void isr_usart0_rx(void);
+WEAK_DEFAULT void isr_usart0_tx(void);
+WEAK_DEFAULT void isr_usb(void);
+WEAK_DEFAULT void isr_timer2(void);
+
+/* interrupt vector table */
+ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
+    [ 0] = isr_dma,                /* DMA */
+    [ 1] = isr_gpio_even,          /* GPIO_EVEN */
+    [ 2] = isr_timer0,             /* TIMER0 */
+    [ 3] = isr_acmp0,              /* ACMP0 */
+    [ 4] = isr_adc0,               /* ADC0 */
+    [ 5] = isr_i2c0,               /* I2C0 */
+    [ 6] = isr_gpio_odd,           /* GPIO_ODD */
+    [ 7] = isr_timer1,             /* TIMER1 */
+    [ 8] = isr_usart1_rx,          /* USART1_RX */
+    [ 9] = isr_usart1_tx,          /* USART1_TX */
+    [10] = isr_leuart0,            /* LEUART0 */
+    [11] = isr_pcnt0,              /* PCNT0 */
+    [12] = isr_rtc,                /* RTC */
+    [13] = isr_cmu,                /* CMU */
+    [14] = isr_vcmp,               /* VCMP */
+    [15] = isr_msc,                /* MSC */
+    [16] = isr_aes,                /* AES */
+    [17] = isr_usart0_rx,          /* USART0_RX */
+    [18] = isr_usart0_tx,          /* USART0_TX */
+    [19] = isr_usb,                /* USB */
+    [20] = isr_timer2,             /* TIMER2 */
+};